JPH0216050B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a latch circuit belonging to a binary-defined digital logic circuit.

An example of a conventional latch circuit is shown in FIG. 1st
In the circuit configuration shown in the figure, the data input signal from the data signal input terminal 1 and the OR
The output signal from the signal output 3 of the circuit 6 is applied via a data signal gate circuit 4 and a latch gate circuit 5. The latch enable signal from the latch enable signal input terminal 2 is used to control the data signal gate circuit 4 and the latch gate circuit 5.

Next, the operation will be explained. Since the latch enable signal passes through an inverting circuit (not shown), in its inactive state, data signal gate circuit 4 is open and latch gate circuit 5 is closed. Therefore, only the data input signal passes through the OR circuit 6 and is output as an output signal. On the other hand, when the latch enable signal is active, data signal gate circuit 4 is closed and latch gate circuit 5 is open. Therefore, the OR circuit 6 maintains a stable state in which the input and output are coupled and not affected by the data input signal. However, the logic of this stable state is the logic of the input of the latch gate circuit 5, that is, the logic of the output of the OR circuit 6 at the moment when the latch enable signal becomes active.

In a conventional latch circuit having such a configuration, the data input signal is latched at the moment the latch enable signal becomes active. Therefore, when the data input signal is a short single pulse, the data input is not latched unless the transition of the latch control signal to the active state coincides with the input of the single data pulse.

This invention was made to eliminate the above-mentioned drawbacks, and by combining a conventional latch circuit with a few gate circuits, it senses changes in the logic of the data input signal and automatically operates the latch without the intervention of a latch enable signal. The object is to provide a circuit for latching data input signals. The present invention will be explained below based on the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention. In FIG. 2, the same symbols as in FIG. 1 indicate the same components, and the output of the OR circuit 6 is inputted to the data signal gate circuit 4 and the latch gate circuit 5 through the catch enable gate circuit 8 and the latch enable NOR circuit 9. has been done. The latch enable signal from the latch enable signal input terminal 2 is inputted to the data signal gate circuit 4 and the latch gate circuit 5 through the latch enable NOR circuit 9. 7 is a catch enable signal input terminal.

Next, the operation will be explained. When the catch enable signal input terminal 7 is inactive, only the latch enable signal input terminal 2 is enabled, and the configuration is equivalent to that of a conventional latch circuit. Under the above conditions, and the latch enable signal input terminal 2
When is inactive, the data input signal input to the data signal input terminal 1 reaches the signal output terminal 3 as is. Further, the data input signal is captured and latched at the moment the latch enable signal input terminal 2 transitions to the active state.

When the catch enable signal input 7 is in the active state, the transition of the data signal input 1 to the active state is transmitted to the data signal gate circuit 4 and the latch gate circuit 5 through the catch enable gate circuit 8. Therefore, the data signal gate circuit 4 is closed, the latch gate circuit 5 is opened, and this latch circuit enters a stable state (latched state).

That is, if the catch enable signal input terminal 7 is kept active, when a data input signal is received, it will be automatically latched. Therefore, as long as the catch enable signal input terminal 7 is kept active, even if a very short single pulse is input as an input signal, this signal can be latched, and the latch enable signal No need to think about timing.

As explained above, according to the present invention, the input signal itself is configured to be used as a latch enable signal, so the catch enable signal is applied to the catch enable gate circuit to activate the catch enable gate circuit. By doing so, even if the data input signal is an irregular single pulse, there is an advantage that it can be latched without considering the timing of the latch enable signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional latch circuit, and FIG. 2 is a block diagram of a latch circuit showing an embodiment of the present invention. In the figure, 1 is a data signal input terminal, 2 is a latch enable signal input terminal, 3 is a signal output terminal, 4 is a data signal gate circuit, 5 is a latch gate circuit, and 6 is a latch gate circuit.
OR circuit, 7 is catch enable signal input terminal,
8 is a catch enable gate circuit, 9 is a latch enable NOR circuit, 10 is an inverter circuit,
11 is an OR circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data signal gate circuit having a data signal input terminal to which a digital input signal is applied, a latch gate circuit that performs opening and closing operations opposite to that of the data signal gate circuit, and a latch gate circuit that receives the outputs of the data signal gate circuit and the latch gate circuit. In a latch circuit, the output from the signal output terminal is applied to the latch circuit, which includes an OR circuit that outputs the output of the OR circuit, and a signal output terminal that takes out the output of the OR circuit, and the output of the signal output terminal is connected to the input side of the latch gate circuit. a catch enable gate circuit whose opening and closing are controlled by a catch enable signal, and an output terminal of this catch enable gate circuit connected to the other input terminal of a latch enable NOR circuit whose opening and closing are controlled by a latch enable signal, This latch enable
A latch circuit characterized in that the output of the NOR circuit is connected to the control side inputs of the data signal gate circuit and the latch gate circuit.