JPH02159750A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02159750A JPH02159750A JP31527588A JP31527588A JPH02159750A JP H02159750 A JPH02159750 A JP H02159750A JP 31527588 A JP31527588 A JP 31527588A JP 31527588 A JP31527588 A JP 31527588A JP H02159750 A JPH02159750 A JP H02159750A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- pin
- resin
- sectional area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 238000000465 moulding Methods 0.000 abstract description 10
- 239000000725 suspension Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に樹脂絶縁型
半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a resin-insulated semiconductor device.
従来の樹脂絶縁型半導体装置の製造方法について図面を
参照して説明する。A conventional method for manufacturing a resin-insulated semiconductor device will be described with reference to the drawings.
第２図は従来の樹脂絶縁型半導体装置における半導体素
子を搭載したリードフレームの上面図である。FIG. 2 is a top view of a lead frame on which a semiconductor element is mounted in a conventional resin-insulated semiconductor device.
半導体素子１はリードフレームのアイランド２に熱抵抗
の小さい半田によってマウントされており、さらに半導
体素子１は外部リード３とワイヤー４によって電気的に
接続されている。The semiconductor element 1 is mounted on an island 2 of a lead frame with solder having low thermal resistance, and furthermore, the semiconductor element 1 is electrically connected to an external lead 3 by a wire 4.
また、アイランド２は、少なくとも１つの外部リードを
形成し下部外枠部によって支持され、さらにアイランド
２は他のグイとともに吊りリード５によって上部外枠部
で支持されている。Further, the island 2 forms at least one external lead and is supported by the lower outer frame part, and the island 2 is further supported by the upper outer frame part by a hanging lead 5 together with other guides.
アイランド２は、半導体素子１で発生する熱を放出する
為の放熱板としての機能を持ち、取付は穴６は製品を支
持固定すると共に放熱効果を高める為のフィン等の取付
けにも使用する。The island 2 has a function as a heat sink for dissipating the heat generated by the semiconductor element 1, and the mounting hole 6 is used to support and fix the product and also to attach a fin or the like to enhance the heat dissipation effect.
第３図は従来の樹脂絶縁型半導体装置の一例の断面図で
ある。FIG. 3 is a cross-sectional view of an example of a conventional resin-insulated semiconductor device.
半導体素子１はリードフレームのアイランド２にマウン
トされると共に外部リード３にワイヤー４によって電気
的に接続されている。また、リーしフレームは外部リー
ト３と取付は六６を除きすべて樹脂７によって覆われて
いる。A semiconductor element 1 is mounted on an island 2 of a lead frame and is electrically connected to external leads 3 by wires 4. Further, the lee frame is entirely covered with resin 7 except for the outer leat 3 and the mounting 66.
第２図及び第３図に示した従来の樹脂絶縁型半導体装置
の特徴は、放熱板となるアイランドを樹脂によって絶縁
を取ることで、製品を取付ける際の絶縁板の排除及び絶
縁板の位置すれ等により信頼性低下防止を図ることにあ
った。A feature of the conventional resin-insulated semiconductor device shown in FIGS. 2 and 3 is that the island, which serves as a heat sink, is insulated with resin, which eliminates the need for the insulating plate when installing the product and allows for easy positioning of the insulating plate. The aim was to prevent reliability from decreasing.
上述した従来の樹脂絶縁型半導体装置は、放熱板となる
アイラン′ドを樹脂によって覆う為に、放・熱効果の低
下が懸念され、これを回避する目的で放熱側のアイラン
ドはＯ］−〜０．４ｍｍと薄く樹脂が覆われている。従
って、成形工程ての位置精度を確保する為、アイランド
を互いに吊りリードによって」二部外枠部て支持する必
要があったのて、切断後の製品においては吊りリードの
破断面が露出し、絶縁耐量の低下、ひいては信頼性の著
しい低下を招くという欠点かあった。In the conventional resin-insulated semiconductor device described above, since the island serving as the heat sink is covered with resin, there is a concern that the heat dissipation effect will deteriorate.In order to avoid this, the island on the heat dissipation side is It is covered with resin as thin as 0.4mm. Therefore, in order to ensure positional accuracy during the molding process, it was necessary to support each other by means of hanging leads on the two outer frames. This had the disadvantage of causing a decrease in dielectric strength and, in turn, a significant decrease in reliability.
本発明の半導体装置の製造方法は、半導体素子を搭載し
たリードフレームを樹脂封止する金型の前記リードフレ
ームの外部リードとは反対側のリードフレーム端部側に
前記金型を垂直に貫通する孔を設け、前記孔を通るピン
を設け、前記リードフレームを前記金型にセットする時
前記ピンと同一サイズの水平断面積を持つ絶縁物柱を前
記ピンによって前記リードフレームの位置まて突上け、
前記リードフレームの端部を前記絶縁物柱と共に支持し
てから樹脂封止を行うものである。The method for manufacturing a semiconductor device of the present invention includes vertically penetrating the mold to the end of the lead frame opposite to the external leads of the mold for resin-sealing a lead frame on which a semiconductor element is mounted. A hole is provided, a pin passing through the hole is provided, and when the lead frame is set in the mold, an insulator column having a horizontal cross-sectional area of the same size as the pin is pushed up to the position of the lead frame by the pin. ,
The ends of the lead frame are supported together with the insulator pillars and then resin-sealed.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の製造方法を説明するための
断面図である。FIG. 1 is a sectional view for explaining a manufacturing method according to an embodiment of the present invention.
半導体素子１はアイランド２によってマウン１〜されワ
イヤー４で外部リード３と電気的な接続がされている。A semiconductor element 1 is mounted by an island 2 and electrically connected to an external lead 3 by a wire 4.
リードフレームが成形金型１２゜１３にセットされる時
、下部の成形金型１２のピン８はこれと同一サイズの水
平断面積をもつ絶縁物柱１０がリードフレームを下方向
から押し上げ、又上部の成形金型１３のピン９はこれと
同一サイズの水平断面積をもつ絶縁物柱１１がリードフ
レームを上方向から押し下げ、ピン８及びピン９によっ
てリードフレームの一端を支えている。When the lead frame is set in the molding die 12° 13, the pin 8 of the lower molding die 12 causes the insulator column 10 with the same horizontal cross-sectional area to push up the lead frame from below, and An insulator column 11 having a horizontal cross-sectional area of the same size as the pin 9 of the molding die 13 pushes down the lead frame from above, and pins 8 and 9 support one end of the lead frame.
このようにリードフレームを支持すれば、従来必要とさ
れた吊りリードを使用しなくても位置ずれを生ずること
なく、精度良く樹脂封止することができる。By supporting the lead frame in this manner, resin sealing can be performed with high precision without causing any positional shift, even without using the conventionally required suspension leads.
上記実施例において絶縁物を突き上げるピンは、樹脂封
止後リードフレームを成形金型から取出す為のノックア
ウトピンを兼用しても差支えない。In the above embodiment, the pin that pushes up the insulator may also be used as a knockout pin for taking out the lead frame from the molding die after resin sealing.
以上説明したように、本発明は、リードフレームが成形
金型にセットされたときに、ピンと同一サイズの水平断
面積をもつ絶縁物柱を上記ピンによってリードフレーム
の位置まで突き上げ、リードフレームの一端部を支持す
ることにより吊りリードが不要となり、吊りリードの破
断面が露出することがない為、耐絶縁性が著しく向上し
、高い信頼度を得ることができるという効果を有する。As explained above, in the present invention, when a lead frame is set in a mold, an insulator column having a horizontal cross-sectional area of the same size as the pin is pushed up to the position of the lead frame by the pin, and one end of the lead frame is By supporting the suspension lead, the suspension lead becomes unnecessary, and the broken surface of the suspension lead is not exposed, so insulation resistance is significantly improved and high reliability can be obtained.
第１図は本発明の一実施例を説明するための断面図、第
２図は従来の樹脂絶縁型半導体装置における半導体素子
を搭載したリードフレームの上面図、第３図は従来の樹
脂絶縁型半導体装置の一例の断面図である。
１・・・半導体素子、２・・アイランド、３・・外部リ
ード、４・・・ワイヤー、５・・・吊りリード、６・・
・取付は穴、７・・・樹脂、８．９・・ピン、１．０．
１１・・絶縁物柱、１２．１３・・・成形金型。FIG. 1 is a cross-sectional view for explaining one embodiment of the present invention, FIG. 2 is a top view of a lead frame on which a semiconductor element is mounted in a conventional resin-insulated semiconductor device, and FIG. 3 is a conventional resin-insulated semiconductor device. 1 is a cross-sectional view of an example of a semiconductor device. DESCRIPTION OF SYMBOLS 1...Semiconductor element, 2...Island, 3...External lead, 4...Wire, 5...Hanging lead, 6...
・Installation is through hole, 7...resin, 8.9...pin, 1.0.
11... Insulator column, 12.13... Molding mold.
Claims (1)
型の前記リードフレームの外部リードとは反対側のリー
ドフレーム端部側に前記金型を垂直に貫通する孔を設け
、前記孔を通るピンを設け、前記リードフレームを前記
金型にセットする時前記ピンと同一サイズの水平断面積
を持つ絶縁物柱を前記ピンによって前記リードフレーム
の位置まで突上げ、前記リードフレームの端部を前記絶
縁物柱と共に支持してから樹脂封止を行うことを特徴と
する半導体装置の製造方法。A hole is provided perpendicularly through the mold at the end of the lead frame opposite to the external lead of the mold for resin-sealing a lead frame on which a semiconductor element is mounted, and a pin passing through the hole is provided. and when setting the lead frame in the mold, an insulator column having a horizontal cross-sectional area of the same size as the pin is pushed up to the position of the lead frame, and the end of the lead frame is pushed up to the position of the insulator column. 1. A method of manufacturing a semiconductor device, which comprises supporting the same and then resin-sealing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31527588A JPH02159750A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31527588A JPH02159750A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02159750A true JPH02159750A (en) | 1990-06-19 |
Family
ID=18063452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31527588A Pending JPH02159750A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02159750A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996036074A1 (en) * | 1995-05-11 | 1996-11-14 | Rohm Co., Ltd. | Semiconductor device |
-
1988
- 1988-12-13 JP JP31527588A patent/JPH02159750A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996036074A1 (en) * | 1995-05-11 | 1996-11-14 | Rohm Co., Ltd. | Semiconductor device |
| US6242801B1 (en) | 1995-05-11 | 2001-06-05 | Rohm Co., Ltd. | Semiconductor device |
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