JPH02157958A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02157958A
JPH02157958A JP31232588A JP31232588A JPH02157958A JP H02157958 A JPH02157958 A JP H02157958A JP 31232588 A JP31232588 A JP 31232588A JP 31232588 A JP31232588 A JP 31232588A JP H02157958 A JPH02157958 A JP H02157958A
Authority
JP
Japan
Prior art keywords
external
data
register
synchronous
asynchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31232588A
Other languages
Japanese (ja)
Inventor
Hideyuki Odawara
秀幸 小田原
Mikio Sakakibara
幹夫 榊原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP31232588A priority Critical patent/JPH02157958A/en
Publication of JPH02157958A publication Critical patent/JPH02157958A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain general usefulness in a semiconductor device with the small number of terminals by providing a register and a circuit to switch synchronously or asynchronously the input / output of data to an external part in the internal part of the semi-conductor device equipped with an I/O port. CONSTITUTION:When a switching register 4 shows an asynchronous system, the data is outputted with external asynchronization since the data of a data register 1 is passed through a multiplexer 5 as it is and outputted to the external part. Next, when the switching register 4 shows a synchronous system, the data of the data register 1 goes into a latch 2 for external synchronization. The data goes up to the multiplexer 5 by a signal from an external synchronous signal input line 3 and since the switching register 4 selects the synchronous system, the value of the data register is matched with the signal of the external synchronous signal input line 3 and outputted. In the case of an input, operation is samely executed as the above mentioned case of the output as well. Thus, even one I/O port can be used as the external synchronous system and external asynchronous system.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、１つのＩ／Ｏポートが、外部同期式としても
、外部非同期式としても使用することのできる半導体装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which one I/O port can be used either as an external synchronous type or as an external asynchronous type.

従来の技術 近年、半導体装置の集積化が進み、１つの装置で様々な
制御を行うようになってきた。2. Description of the Related Art In recent years, the integration of semiconductor devices has progressed, and a variety of controls have come to be performed with one device.

以下従来の入出力回路について説明する。A conventional input/output circuit will be explained below.

第２図は、従来の外部同期式入出力回路である。データ
レジスタ１と外部端子の間には、外部との同期を合わせ
るための回路２が存在している。FIG. 2 shows a conventional externally synchronized input/output circuit. A circuit 2 for synchronizing with the outside exists between the data register 1 and the external terminal.

第３図は、従来の外部非同期式入出力回路である。デー
タレジスタ１と外部端子は直接結ばれているため、出力
の場合レジスタにデータを書（とそのデータはすぐに外
部に出力され、また、入力の場合、外部のデータはいつ
もレジスタと同じ値を持っている構造になっている。FIG. 3 shows a conventional external asynchronous input/output circuit. Data register 1 and the external terminal are directly connected, so in the case of output, data is written to the register (and that data is immediately output to the outside), and in the case of input, the external data always has the same value as the register. It has a structure.

従来このような、外部同期式の入出力回路と非同期式の
入出力回路は、別々の端子に分かれていた。Conventionally, such externally synchronous input/output circuits and asynchronous input/output circuits have been separated into separate terminals.

発明が解決しようとする課題 しかしながら上記従来の構成では、半導体装置に汎用性
を持たせたい′場合、外部同期式と外部非同期式の両方
を備えると端子数が増えてしまう。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, if the semiconductor device is desired to have versatility, the number of terminals increases if both externally synchronous and externally asynchronous types are provided.

またセットによっては、どちらかを使用しない場合があ
る時、余分な端子ができることになる。Also, depending on the set, if one of the terminals is not used, an extra terminal is created.

本発明は上記従来の課題を解決するもので、汎用性を持
たせた上に少ない端子数で、外部同期式か外部非同期式
かを選んで使用することができることを目的とする。The present invention is intended to solve the above-mentioned conventional problems, and aims to provide versatility, reduce the number of terminals, and enable use of either an external synchronous type or an external asynchronous type.

課題を解決するための手段 この目的を達成するために本発明の入出力回路は、内部
に、外部同期式か外部非同期式かを設定する専用レジス
タを設け、上記レジスタの値により、外部同期式か外部
非同期式かを切り換える構成を有している。Means for Solving the Problems In order to achieve this object, the input/output circuit of the present invention is provided with an internal dedicated register for setting external synchronous type or external asynchronous type. It has a configuration that allows switching between the external asynchronous type and external asynchronous type.

作用 この構成により、１つのＩ１０ポートを外部同期式とし
ても外部非同期式としても使用することができる。Operation This configuration allows one I10 port to be used both as an external synchronous type and as an external asynchronous type.

実施例 以下、本発明の一実施例について図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例における、入出力回路を示す
ものである。第１図において、１はデータレジスタ、２
は外部同期用のラッチ、３は外部同期信号入力線、４は
外部同期、非同期を切り換えるレジスタ、５は外部同期
、非同期を切り換えるためのマルチプレクサである。FIG. 1 shows an input/output circuit in one embodiment of the present invention. In Figure 1, 1 is a data register, 2
3 is a latch for external synchronization, 3 is an external synchronous signal input line, 4 is a register for switching between external synchronous and asynchronous, and 5 is a multiplexer for switching between external synchronous and asynchronous.

このように構成された本実施例の入力回路にっいてその
動作を説明する。The operation of the input circuit of this embodiment configured as described above will be explained.

まず、Ｉｌｏのうち出力の場合を説明する。First, the case of output of Ilo will be explained.

データレジスタ１に入っているデータはラッチ２とマル
チプレクサ５につながっている。今、切換レジスタ４が
非同期式を示しているとすると、データレジスタ１のデ
ータはそのままマルチプレクサ５を通り外部に出力され
るため、外部非同期でデータが出力される。次に、切換
レジスタ４が同期式を示しているとすると、データレジ
スタ１のデータは２の外部同期用のラッチに入る。そし
て外部同期信号入力線３からの信号により、データはマ
ルチプレクサ５まで行き、切換えレジスタ４が同期式を
選んでいることにより、データレジスタ１の値は、外部
同期信号入力線３の信号に合わせて出力される。The data contained in data register 1 is connected to latch 2 and multiplexer 5. Now, assuming that the switching register 4 indicates an asynchronous type, the data in the data register 1 is outputted to the outside through the multiplexer 5 as it is, so that the data is outputted externally asynchronously. Next, assuming that the switching register 4 indicates the synchronous type, the data in the data register 1 enters the latch 2 for external synchronization. Then, the data is sent to the multiplexer 5 by the signal from the external synchronization signal input line 3, and since the switching register 4 has selected the synchronous type, the value of the data register 1 is changed according to the signal from the external synchronization signal input line 3. Output.

Ｉｌｏのうちの入力の場合も上記の出力の場合と同様に
動作し、外部のデータが、外部同期又は非同期によって
データレジスタ１に入る。The input of Ilo operates in the same way as the output described above, and external data enters the data register 1 by external synchronization or asynchronous.

発明の効果 本発明によれば、専用の外部同期、非同期切換レジスタ
を用いて、Ｉ／Ｏポートを、外部同期式と外部非同期式
を切換えて使用できる構成をしているものであるから、
少ない端子数で、半導体装置に汎用性を持たせることが
できる。Effects of the Invention According to the present invention, an I/O port can be used by switching between an external synchronous type and an external asynchronous type using a dedicated external synchronous/asynchronous switching register.
With a small number of terminals, the semiconductor device can be made more versatile.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例における入出力回路の回路図
、第２図は従来の外部同期式入出力回路の回路図、第３
図は従来の外部非同期式入出力回路の回路図である。 １・・・・・・データレジスタ、２・・・・・・外部同
期用ラッチ、３・・・・・・外部同期信号入力線、４・
・・・・・同期、非同期切換レジスタ、５・・・・・・
マルチプレクサ。 代理人の氏名　弁理士　粟野重孝　ほか１名第１図 多−タレジズタ 外雷同躬用ラッチ 外部同１’Ｍ　ｂ、子 同期・詐ｌｉｌ副回復しジズタ 同期・非同ｗ４切換用マル士プレク丈 タトＷ３１１１１モトFIG. 1 is a circuit diagram of an input/output circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional externally synchronized input/output circuit, and FIG.
The figure is a circuit diagram of a conventional external asynchronous input/output circuit. 1... Data register, 2... External synchronization latch, 3... External synchronization signal input line, 4...
...Synchronous, asynchronous switching register, 5...
multiplexer. Name of agent: Patent attorney Shigetaka Awano and 1 other person Figure 1 Multi-tare register for external lightning same 1'Mb, child synchronization/fraud sub-recovery, jizuta synchronization/non-same w4 switching for multi-layer plec length tato W31111moto

Claims (1)

【特許請求の範囲】[Claims] Ｉ／Ｏポートを有する半導体装置の内部にレジスタおよ
びデータの入出力を外部との同期非同期を切換える回路
を備えたことを特徴とする半導体装置。1. A semiconductor device comprising an I/O port and a register and a circuit for switching data input/output between synchronous and asynchronous with the outside.
JP31232588A 1988-12-09 1988-12-09 Semiconductor device Pending JPH02157958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31232588A JPH02157958A (en) 1988-12-09 1988-12-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31232588A JPH02157958A (en) 1988-12-09 1988-12-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02157958A true JPH02157958A (en) 1990-06-18

Family

ID=18027878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31232588A Pending JPH02157958A (en) 1988-12-09 1988-12-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02157958A (en)

Similar Documents

Publication Publication Date Title
AU2002361761A1 (en) Multi-mode synchronous memory device and method of operating and testing same
JPS56137584A (en) Semiconductor storage device
JPH02157958A (en) Semiconductor device
JPS5515559A (en) Test input circuit of microcomputer
JPS5444480A (en) Package for integrated circuit
KR910014785A (en) Integrated circuit device
JPS6371671A (en) Large sale integrated circuit
JPH02109414A (en) Semiconductor integrated circuit filter and its manufacture
JP2881788B2 (en) Video signal switching device
JPS6072318A (en) Logical lsi
JPS59167157A (en) Time division exchange
JPS5983234A (en) Large scale integrated circuit
JPS617974A (en) Chip mode selection circuit
JPH03125206A (en) Logic integrated circuit
JPH02181950A (en) System of setting operation mode of semiconductor integrated circuit
JPH01296326A (en) Clock drive circuit
JPH0425913A (en) Clock output circuit
JPS59149724U (en) DA converter
JPS61284110A (en) Integrated circuit
JPH04155481A (en) Microprocessor
JPS59151254A (en) Interrupt synchronizing system between minicomputer and microcomputer
JPS61198914A (en) Power-on reset circuit
JPS6136947A (en) Semiconductor device
JPH02235124A (en) Signal processing circuit
JPH03263921A (en) Counter with preset