JPH0215710A - Metastable detection circuit - Google Patents

Abstract

PURPOSE:To detect the metastable state of a signal to be tested by deciding outputting states of the multi-input gate circuit of a CMOS NAND gate element and the multi-input gate circuit of a CMOS OR gate element from outputs of the both gate circuits. CONSTITUTION:At a NOR 21, potential of logic '0' is previously inputted to #2-#m of the input terminal 23 except #1 after adjusting the value (m). At a NAND 22, potential of logic '1' is previously inputted to #2-#n of the input terminal 24 except #1 after adjusting the value (n). When the potential of the output OUT of an FF1 gets into the range between the lower and higher thresholds, the output OUT is fetched to each FF 4 and 5 by means of a clock CLK #2 which rises at the timing t3 lagging in phase from the rising timing of a clock t1 by prescribed time DELTAt. Therefore, the output of an EOR 6 rises from logic '0' to logic '1' after the timing t3 and the metastable state of the output OUT of the FF 1 can be detected.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a metastable detection circuit that detects the metastable state of the output of a flip-flop when its setup time and hold time are not satisfied. Realize the operation,
In order to facilitate integration into CMO3-LSI etc., one input terminal is connected to the signal under test and the number of other input terminals is changed to make the potential of the signal under test meta-stable. first and second multi-input gate circuits configured such that each output logic changes with boundaries near the upper and lower thresholds when the state is reached; and the first and second multi-input gate circuits. and a determination circuit that determines each output logic of the gate circuit to detect the metastable state.

[Industrial application field]

The present invention relates to a metastable detection circuit that detects the metastable state of the output of a flip-flop when its setup time and hold time are not satisfied.

[Conventional technology]

For example, in a D-type flip-flop 1 (FFI, the same applies hereinafter) as shown in FIG. As shown in FIG. 5 fbl, when the input timing of the input signal DATA does not satisfy the cent-up time tsu and hold time thoLd of the FFI, the FFI
The output OUT from the output terminal Q of the is in a logically uncertain state (for example, 0 volts in potential), neither logic "O" (for example, 0 volts in potential) nor logic "1" (for example, 3 volts in potential). 8 volts or more and 2 volts or less).

The above state is called a metastable state, and FF
Since the maximum value of the propagation delay time of I is exceeded, there is a possibility that the subsequent circuit will malfunction. Therefore, a circuit to detect such a metastable state is prepared,
It is necessary to operate so that input DATA is not input at a timing when a metastable state is detected.

Figure 6 shows the configuration of a conventional metastable detection circuit,
Further, FIG. 7 shows the operation timing chart.

In FIG. 6, first, a flip-flop whose metastable state is to be detected is assumed to be FFI.

The input DATA inputted to the input terminal of the FFI via the buffer 9 is synchronized with the rising timing t1 of the clock CLK#1 inputted to the clock terminal GK via the buffer 10 as shown in FIG. and imported into FFI. The above timing tl corresponds to the setup time tsu and hold time of the FFI.

If Ld is not satisfied (see FIG. 5(b)), the output OUT from the positive logic output terminal Q of the FFI is in a metastable state between t2 and t4 as shown in FIG.

The output OUT is input to comparators 2 and 3. In addition to the power supply voltage Vcc, the comparator 2 also has a reference voltage Vl.
is inputting. Here, if the potential of the logic "1" of the entire system is 3 volts and the potential of the logic "0" is O volts, then in the comparator 2, for example, the threshold voltage determined by the power supply voltage Vcc is 1.4 volts and the reference voltage V I = 0.6
volts are added to set a threshold voltage of 2.0 volts. On the other hand, in the comparator 3, for example, the power supply voltage Vcc
Threshold voltage 1.4 volts determined by and reference voltage V 2
=-0.6 volts is added, and a threshold voltage of 0.8 volts is set.

As a result, the output OUT shown in FIG. 7 becomes, for example, t2
When the logic "1" is determined as before (potentially 3 volts), the output OUT of comparators 2 and 3 exceeds the respective threshold voltages of 2.0 volts and 0.8 volts. , their respective outputs C#1 and C#2 have the same logic rlJ.

Similarly, the output OUT becomes logic rO, for example after t4.
When J is determined (O volts in terms of potential), the outputs OUT of comparators 2 and 3 are both below the respective threshold voltages of 2.0 volts and 0.8 volts, so each of these outputs C# 1 and C#2 have the same logic "0".

However, if a metastaple state occurs between 2 and t4 in FIG. 7, and the potential of the output OUT is 0.8 volts or more and 2.0 volts or less, the output 0LJT of the comparator 21 becomes the threshold voltage 2. .0pol1-, the output C#1 becomes logic "0", and in comparator 3, the output OUT exceeds the threshold voltage 0°8 volts, so the output C#1 becomes logic "0".
#2 becomes logic "0", and the logic of each output C#1 and C#2 is reversed as shown in FIG.

C#1 and C#2 in the above metastable state are 2
Rise timing of clock H (F of input DATA
Clock CLK# that rises at timing L3, which is out of phase by a predetermined time Δt from the set timing to FI
2 (manually inputted via the buffer 13) to each clock terminal CK of FF4 and 5, the clock signal from each input terminal to each FF4 and 5 is input at the above timing L3.
be taken in.

As a result, exclusive OR circuit 6 (EOR
6, the same applies hereafter), the output becomes logic ``0'' as shown in Figure 7.
” rises to logic “1”.

Subsequently, the output of EOR6 is inputted to the input terminal of FF7. FF7 is initially cleared by the clear signal CL input to the reset terminal R, and the output between the negative logic output terminals is logic "1", so the buffer 1
1, the detection output DET becomes logic "1", and at the same time, the AND circuit 8 (AND8. hereinafter the same) is turned on via the buffer 12, and the clock CLK#3 input via the hesoplex 14 becomes the logic "1". It can be input to the clock terminal CK.

Therefore, EOR6, which became logic "1" at t3,
The output of is taken into FF7 at timing t5 when clock CLK#3 rises, and as a result, as shown in FIG. 7, the output between the negative logic output terminals changes to logic "0",
The detection output DET via the buffer 11 becomes logic "0".

With the above operation, the metastable state of the output OUT of the FFI can be detected as the detection output DET of logic "0". This detection output DET is used to indicate that the metastable state has been detected by a display circuit (LED), etc., which is not particularly shown.

Note that when the output between the negative logic output terminals of FF7 becomes logic "0", AND8 is turned off via the buffer 12, so that the clock CLK#3 is no longer input. Therefore,
After that, the metastable state of the output OUT is resolved,
Even if the output of EOR6 becomes logic "1", the state of FF7 does not change, and the detection output maintains logic "0" until the user inputs the clear signal CL.

[Problem to be solved by the invention]

Flip-flop circuits that attempt to detect metastable states as shown above have been widely used in integrated circuits such as LSIs in recent years, and because they are used in deep logical parts, their outputs are not connected to output pins. In many cases, it cannot be taken out directly.

Therefore, it is conceivable to configure the metastable detection circuit shown in FIG. 6 inside an integrated circuit.

However, in the configuration shown in Fig. 6, in order to operate the comparators 2 and 3, two reference voltages Vl and 2 are required in addition to the power supply voltage Vcc. CMO that operates from a single power supply
The problem is that it is difficult to configure it in a 3-LSI.

An object of the present invention is to realize the operation of a metastable detection circuit with a single power supply and to facilitate its incorporation into a CMO3-LSI or the like.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention.

The signal under test 15 is the output of, for example, a flip-flop circuit (not shown) which can generate a metastable state.

The first multi-input gate circuit 18 has one input terminal 1
The signal under test 15 is input to 6#1, and the other input terminal 16#
By changing the number from 2 to 16#m, the output logic is set to change with the upper threshold value at which the signal under test 15 is in a metastable state as the boundary. The circuit 18 has, for example, one input terminal connected to the signal under test 15, the other input terminals set to a potential equal to or higher than the upper threshold, and when the potential of the signal under test 15 is equal to or higher than the upper threshold, the logic is "0". ”, if it is less than or equal to the upper threshold, the logic “
It is composed of a CMOS NAND gate element that outputs "1".

The second multi-input gate circuit 19 has one input terminal 1
The signal under test 15 is input manually to 7#1, and the other input terminal 17
By changing the numbers #2 to 17#n, settings are made such that the output logic changes with the lower threshold value at which the signal under test 15 enters the metastable state as the boundary. For example, the circuit 19 has one input terminal connected to the signal under test 15, the other input terminals are set to a potential below the lower threshold, and when the potential of the signal under test 15 is above the lower threshold, It is constituted by a CMOS OR gate element which outputs a logic "O" and a logic "1" when the lower threshold value is below.

Next, the determination circuit 20 determines each output logic of the first and second large-scale gate circuits 18 and 19 to detect the metastable state. The circuit 20 is composed of, for example, an exclusive OR element inputting each output of the first and second multi-input gate circuits 18 and 19, and a flip-flop circuit latching the output of the element.

[For production]

In the above configuration 1. When the signal under test 15 is in a metastable state, the signal 15 has a potential higher than the lower threshold and lower than the upper threshold.

Therefore, when the signal under test 15 is in a metastable state, if the first multi-input gate circuit 18 is, for example, the CMOS NAND gate device, and the second multi-input gate circuit 19 is, for example, the CMOS OR gate device, these are as follows. Each outputs a different logic rlJ and logic "0".

Subsequently, the output state is detected by the determination circuit 20, thereby making it possible to detect the metastable state of the signal under test 15.

In this case, multiple threshold values for detecting a metastable state can be set by changing the number of inputs of the multi-input gate circuits 18 and 19, and the circuit in FIG. 1 can be operated with a single power supply. becomes possible.

Therefore, even if the flip-flop circuit that outputs the signal under test 15 is configured in a CMO3-LSI that operates on a single power supply, the circuit shown in FIG. 1 can be easily incorporated into the LSI. becomes.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

FIG. 2 is a configuration diagram of an embodiment of the present invention. In addition, the 6th
It is assumed that circuits with the same numbers as in the figure have the same function.

In FIG. 1, first, a flip-flop whose metastable state is to be detected is assumed to be FFI.

The input DATA input to the input terminal of the FFI via the buffer 9 is input to the FFI input terminal according to the clock CLK#1 input to the clock terminal CK via the buffer 10.
be taken in.

The output OUT from the positive logic output terminal Q of FF1 is 0MO
NAND circuit 21 of CMO3 (NOR circuit 21 <N0R21, the same applies hereafter) input terminal 23#1 and NAND circuit 22 of CMO3
It is input to the input terminal 24#1 of the ND22 (hereinafter the same).

In N0R21, input terminals 23 #2 to # other than #1
The potential of the logic rOJ is applied to m. Also, NAND2
2, a potential of logic "1" is input to input terminals 24 #2 to #n other than #1.

The outputs C#3 and C#4 of the N0R21 and NAND22 are taken into the FFs 4 and 5 from each input terminal in accordance with the clock CLK#2 inputted to each clock terminal CK via the buffer 13, respectively.

Each output from each positive logic output terminal Q of each FF4 and 5 is
Both are input to an exclusive OR circuit 6 (EOR6, the same applies hereinafter), and the output thereof is input to the input terminal of FF7. F F
, 7, the clock CL is connected to the clock terminal CK of the clock terminals CK through the hasher 14 and the AND circuit 8 (AND8, the same applies hereinafter).
K#3 is manually operated 1. AND8 is controlled by the output from the negative logic output terminal Q of FF7 which is manually input via the buffer 12.

Further, the output from between the negative logic output terminals of the FF7 is outputted as a detection output DET via the buffer 11, and the detection of the metastable state is displayed by a display circuit (LED), etc. not shown.

The operation of the embodiment of the present invention having the above configuration will be explained using the operation timing chart of FIG. 3 and the operation characteristic diagram of FIG. 4.

First, the input DATA is clocked C as shown in FIG.
FFI by the same amount at the rising timing LL of LK#1
be taken in. Then, the above timing t1 is FFI
If the set-up time tsu and hold time t1°, , are not satisfied (see Fig. 5 (bl)), the output O
As shown in FIG. 3, the UT is in a metastable state between L2 and t4.

The above output OUT is 0MO3 N0R21 and NAND2
2, but N0R21 of 0MO3 and NAND2
2, the number m, n of each input terminal 23.24 and each output C
There is a relationship as shown in FIG. 4 between the input potential threshold at which the logic of #3 and C#4 changes. From now on, N0R
21, by inputting a logic "0" potential to the input terminals 23#2 to #m other than #l after adjusting the value of m, the output C#3 is changed from the input terminal 23#l. If the potential of the input output OUT is higher than the lower threshold of the potential for metastable state, the logic "
If it is low, it can be set to logic "1". In addition, in the NAND 22, after adjusting the value of n, logic "1" is applied to the input terminals 24#2 to #n other than #l.
By inputting the potential of the output C#4, if the potential of the output OUT input from the input terminal 24#1 is higher than the upper threshold of the potential at which the metastable state occurs, the logic "0" is set. ”, and if it is low, it can be set to logic “1”.

When the output OUT shown in FIG. 3 is determined to be logic "1" by the N0R21 and NAND22, for example before t2, the output OUT is below the potential of the metastable state in the N0R21 and NAND22. Since both the threshold and the upper threshold are exceeded, their respective outputs C#l and C#2 will be the same logic "0". Similarly, when the output OUT is determined to be logic "0", for example after t4, the output OUT of N0R21 and NAND22 is below both the lower threshold and the upper threshold, so their Each output C#1 and C#2 becomes the same logic "1".

However, if a metastable state occurs between t2 and t4 in FIG. 3, and the potential of the output OUT is greater than or equal to the lower threshold and less than or equal to the upper threshold, in N0R21, the output O
Since UT exceeds the lower threshold, output C#3 is logic “0”
In the NAND27, the output OUT is below the upper threshold, so the output C#4 becomes logic "1" and the third
As shown in the figure, the logic of each output C#3 and C#4 is reversed.

C#1 and C#2 in the above metastable state are based on the rise timing of clock t1 (F of input DATA).
Clock CLK# that rises at timing t3, which is out of phase by a predetermined time Δt from the set timing to FI
2, it is taken into each FF4 and 5.

As a result, after t3, the output of EOR6 rises from logic "0" to logic rlJ as shown in FIG.

Subsequently, the output of EOR6 is inputted to the input terminal of FF7. FF'7 is initially cleared by the clear signal CL input to the reset terminal R, and the output of the negative logic output terminal Q is the logic rlJ, so the detection output DET via the buffer 11 becomes the logic rlJ. At the same time, the AND circuit 8 (AND8, hereinafter the same) is turned on via the buffer 12, and the clock CLK#3 input via the buffer 14 can be input to the clock terminal CK of the FF7.

Therefore, EOR6, which became logical rlJ at t3,
The output of is taken into FF7 at timing t5 when clock CLK#3 rises, and as a result, as shown in FIG. 3, the output of negative logic output terminal 100 changes to logic "0".
The detection output DET via the buffer 11 becomes logic "0".

With the above operation, the metastable state of the output OUT of the FFI can be detected as the detection output DET of logic "0". This detection output DET is used to indicate that the metastable state has been detected by a display circuit (LED), etc., which is not particularly shown.

Note that when the output at the negative logic output terminal of FF7 becomes logic "0", AND8 is turned off via the buffer 12, so that the clock CLK #3 is no longer input. Therefore, after that, even if the metastable state of the output 0tJT is resolved and the output of EOR6 becomes logic "1", FF7
The state of DET remains unchanged and the detection output DET remains at logic "0" until the user inputs the clear signal CL.

As shown above, in the embodiment of the present invention shown in FIG.
R21 is comparator 3 and NAND2 of the conventional example in FIG.
Similarly, comparator 2 performs the same operation as comparator 2 (however, the output logic is reversed). Therefore, the plurality of reference voltages 1 and V2 in the conventional example shown in FIG. 6 are completely unnecessary. This makes it possible to operate the entire circuit shown in Figure 2 with a single power supply, and allows the FFI to operate on a single power supply in CMO3-LS.
Even if it is configured within the CMO3-LSI, circuits other than the FFI shown in FIG. 2 can also be incorporated into the CMO3-LSI.

Note that the multi-input gate circuit is not limited to the NOR circuit or NAND circuit of the CMO5, but can also be realized by an OR circuit, an AND circuit, or the like. Further, any gate circuit may be used as long as the logic threshold value changes depending on the number of input terminals.

〔Effect of the invention〕

According to the present invention, by changing the number of input terminals of the multi-input gate circuit, it is possible to set the upper and lower threshold potentials of the metastable state.

This makes it possible to operate the entire metastable detection circuit with a single power supply, and the signal under test is
Even if it is inside an LSI, the entire detection circuit is CMO3
- It becomes possible to easily incorporate it into LSI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. 3 is an operation timing chart of the embodiment of the present invention; FIG. 4 is an embodiment of the present invention. Figure 5 (at
, (bl is an explanatory diagram of metastable, FIG. 6 is a configuration diagram of a conventional example, and FIG. 7 is an operation timing chart of a conventional example. 15...signal under test, 16.17... Input terminal, 18... First multi-input gate circuit, 19... Second multi-input gate circuit, 20... Judgment circuit. This is the start!! The size of the month is 4 and 1. Timing Chart Diagram 3 Figure 7'] Murder m, n Honba September's 'JJ &I1's Shigetsuki Ishita T Temple 1 Life Chart Diagram FF Furiraffe 070, Tsubu (FF) Operation Timing Timer Chart (b ) Metastial escape station ``Fig.

Claims (1)

[Claims] 1) Each one input terminal (16#1, 17#1) is connected to the signal under test (15) and each other input terminal (16#2
~#m, 17#2~#m), each output is set to the vicinity of the upper threshold and the lower threshold when the potential of the signal under test (15) is in a metastable state. The first and second multi-input gate circuits (18, 19) are set so that the logic changes, and each output logic of the first and second multi-input gate circuits (18, 19) is determined. and a determination circuit (20) for detecting the metastable state. 2) In the first multi-input gate circuit, one input terminal is connected to the signal under test, other input terminals are set at a potential higher than the upper threshold, and the potential of the signal under test is higher than the upper threshold. The second multi-input gate circuit is configured with a CMOS NAND gate element that outputs a logic "0" when the signal is below the upper threshold, and a logic "1" when the signal is below the upper threshold, and one input terminal is connected to the signal under test. and the other input terminals are set to a potential below the lower threshold, and a logic "0" is set when the potential of the signal under test is above the lower threshold, and a logic "1" is set when the potential of the signal under test is below the lower threshold. 2. The metastable device according to claim 1, wherein the metastable device is constituted by a CMOS OR gate device that outputs, and wherein the determination circuit detects the metastable state when the respective output logics of the CMOS NAND gate device and the CMOS OR gate device are different. detection circuit.