JPH0215653A - Manufacture of semiconductor chip - Google Patents
Manufacture of semiconductor chipInfo
- Publication number
- JPH0215653A JPH0215653A JP63165462A JP16546288A JPH0215653A JP H0215653 A JPH0215653 A JP H0215653A JP 63165462 A JP63165462 A JP 63165462A JP 16546288 A JP16546288 A JP 16546288A JP H0215653 A JPH0215653 A JP H0215653A
- Authority
- JP
- Japan
- Prior art keywords
- film
- fets
- semiconductor chip
- semiconductor
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title description 9
- 238000005520 cutting process Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 abstract description 19
- 229910052751 metal Inorganic materials 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 17
- 230000001681 protective effect Effects 0.000 abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 230000000717 retained effect Effects 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 15
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 239000004188 Virginiamycin Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229920006302 stretch film Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ウェハプロセスにより、半導体ウェハ基板上
に多数の半導体素子が構築された半導体ウェハを、各半
導体素子に分割して半導体チップを製造する方法に関す
る。さらに詳述すれば、得られた半導体チップの所定電
極と、パッケージやリードフレーム等の所定部分とを、
ポンディングワイヤを用いることなく、直接電気的に接
続し得る半導体チップの製造方法に関する。Detailed Description of the Invention (Industrial Application Field) The present invention is a method for manufacturing semiconductor chips by dividing a semiconductor wafer, in which a large number of semiconductor elements are constructed on a semiconductor wafer substrate, into individual semiconductor elements through a wafer process. Regarding how to. More specifically, predetermined electrodes of the obtained semiconductor chip and predetermined parts of the package, lead frame, etc.
The present invention relates to a method for manufacturing a semiconductor chip that can be directly electrically connected without using bonding wires.
（従来の技術）
ウェハプロセスにより、半導体ウニ八基板上に多数の同
一の半導体素子が構築された半導体ウェハが得られると
、該半導体ウェハは、それぞれの半導体素子毎に半導体
チップとなるようにそれぞれ分割される。分割された各
半導体チップはパッケージやリードフレームに組み込ま
れる。パッケージやリードフレームに組み込まれた半導
体チップは、ペースト等によりパッケージやリードフレ
ームに固着される。そして、各半導体チップの電極とパ
ッケージやリードフレーム等の導体パターンやグランド
部とが電気的に接続される。(Prior Art) When a semiconductor wafer in which a large number of identical semiconductor elements are constructed on a semiconductor substrate is obtained through a wafer process, the semiconductor wafer is individually processed so that each semiconductor element becomes a semiconductor chip. be divided. Each divided semiconductor chip is assembled into a package or lead frame. A semiconductor chip incorporated into a package or lead frame is fixed to the package or lead frame using paste or the like. Then, the electrodes of each semiconductor chip are electrically connected to a conductive pattern such as a package or a lead frame or a ground portion.
第６図は、パッケージやリードフレーム等の基板に固着
された従来の半導体チップの断面図である。半導体チッ
プ６０はパッケージやリードフレーム等の基板７１にマ
ウントされて、ペースト７２により固着されている。該
半導体チップ６０の各接地電極６１は該基板７１におけ
るグランド部７１ａ等の所定部分に、ボンディングワイ
ヤ７３にてそれぞれ電気的に接続されている。FIG. 6 is a cross-sectional view of a conventional semiconductor chip fixed to a substrate such as a package or a lead frame. The semiconductor chip 60 is mounted on a substrate 71 such as a package or a lead frame, and is fixed with a paste 72. Each ground electrode 61 of the semiconductor chip 60 is electrically connected to a predetermined portion of the substrate 71, such as a ground portion 71a, by a bonding wire 73.
（発明が解決しようとする課題）
このように、パッケージ等の基板７１の所定部分と半導
体チップ６０の接地電極６１とをボンディングワイヤ７
３で接続する場合には、該基板７１上には。(Problem to be Solved by the Invention) In this way, the bonding wire 7 connects a predetermined portion of the substrate 71 such as a package and the ground electrode 61 of the semiconductor chip 60.
3, on the board 71.
該半導体チップ６０を固定するためのペースト７２等が
占める領域のほかに、半導体チップ６０の接地電極６１
と電気的に接続すべきボンディングワイヤ７３が占める
領域が必要になる。このため、基板７１が大型化し、製
造される半導体装置全体が大型になるという欠点がある
。In addition to the area occupied by the paste 72 and the like for fixing the semiconductor chip 60, the ground electrode 61 of the semiconductor chip 60
An area occupied by the bonding wire 73 to be electrically connected is required. Therefore, there is a drawback that the substrate 71 becomes larger and the entire semiconductor device to be manufactured becomes larger.
また、近時、高周波化および高速動作化を目的として、
電子の移動度の大きいＧａＡｓ材料を用いた電界効果ト
ランジスタ（ＧａＡｓＦＥＴ）やモノリシックマイクロ
波ＩＣ（ＧａＡｓＭＩＣ）等が開発されている。このよ
うな、半導体チップの接地電極と、パッケージ等のグラ
ンド部との接続にボンディングワイヤを用いると、該ボ
ンディングワイヤのインダクタンスが、半導体チップに
おける素子の接地インダクタンスに加わり、半導体素子
の性能が著しく低下するおそれがある。In addition, recently, with the aim of achieving higher frequencies and faster operation,
Field effect transistors (GaAsFETs) and monolithic microwave ICs (GaAsMICs) using GaAs materials with high electron mobility have been developed. When a bonding wire is used to connect the ground electrode of a semiconductor chip and the ground part of a package, etc., the inductance of the bonding wire is added to the ground inductance of the element in the semiconductor chip, and the performance of the semiconductor element is significantly reduced. There is a risk of
本発明は上記従来の問題を解決するものであり。The present invention solves the above-mentioned conventional problems.
その目的は、半導体チップの電極部をボンディングワイ
ヤを用いることなくパッケージ等の導体パターンやグラ
ンド部に電気的に接続し得る半導体チップの製造方法を
提供することにある。The purpose is to provide a method for manufacturing a semiconductor chip that can electrically connect the electrode portion of the semiconductor chip to a conductive pattern such as a package or a ground portion without using bonding wires.
（課題を解決するための手段）
本発明の半導体チップの製造方法は、多数の半導体素子
が形成された半導体ウェハ表面を、各半導体素子の表面
に設けられた接地電極の少なくとも一部が露出するよう
に、レジスト膜にて被覆する工程と、その半導体ウェハ
を、切断面が所定の傾斜面となるように切断して各半導
体素子に分割する工程と２分割された各半導体素子の切
断面と各半導体素子の表面全面とを、導電膜にて被覆す
る工程と、該切断面を被覆する導電膜が各半導体素子に
おける表面の接地電極に接続した状態で残るように、各
半導体素子表面の所定位置を被覆するレジスト膜を、該
レジスト膜を被覆する導電膜と共に各半導体素子から除
去する工程と、を包含してなり、そのことにより上記目
的が達成される。(Means for Solving the Problems) A method for manufacturing a semiconductor chip of the present invention includes exposing a surface of a semiconductor wafer on which a large number of semiconductor elements are formed, at least a part of a ground electrode provided on the surface of each semiconductor element. As shown in FIG. A step of covering the entire surface of each semiconductor element with a conductive film, and a step of covering the entire surface of each semiconductor element with a conductive film, and applying a conductive film to a predetermined area on the surface of each semiconductor element so that the conductive film covering the cut surface remains connected to the ground electrode on the surface of each semiconductor element. The method includes the step of removing the resist film covering the position from each semiconductor element together with the conductive film covering the resist film, thereby achieving the above object.
（実施例） 以下に本発明を実施例について説明する。(Example) The present invention will be described below with reference to Examples.
本発明の半導体チップの製造方法は２例えば高周波用Ｇ
ａＡｓ ＦＥＴを製造する際に実施される。本発明方法
では、第１図（イ）および（ロ）に示すように、ウェハ
プロセスにより、半導体ウェハ基板１５上に、半導体素
子として平面視正方形状の多数の高周波用ＧａＡｓ Ｆ
ＥＴ ＩＬ １１．・・・が構築された半導体ウェハ１
０が使用される。各ＦＥＴ １１は、その表面側に、
Ａｕを用いた接地電極１１ａが配設されている。The method for manufacturing a semiconductor chip of the present invention is as follows:
It is implemented when manufacturing aAs FETs. In the method of the present invention, as shown in FIGS. 1(a) and 1(b), a large number of high-frequency GaAs Fs having a square shape in plan view are formed as semiconductor elements on a semiconductor wafer substrate 15 by a wafer process.
ET IL 11. Semiconductor wafer 1 constructed with...
0 is used. Each FET 11 has a
A ground electrode 11a made of Au is provided.
該ＰＥＴ １１０表面側には他の電極も配設されている
。Other electrodes are also arranged on the surface side of the PET 110.
本発明方法は、まず、各ＦＥＴ １１を例えば窒化シリ
コン膜でなる保護膜１２により、各接地電極１１ａの一
部を除いて被覆する。該保護膜１２はＦＥ、Ｔ １１を
保護する。該保護膜１２には、各接地電極１１ａの一部
を露出させるための一対の開口部１２ａが設けられてい
る。各開口部１２ａは、 ＰＥＴ１１の対をなす一対の
辺に沿って開設されている。半導体ウェハ基板１５の各
ＦＥＴ １１が構築されていない部分は、切り代１５ａ
となっており、この切り代１５ａ部分には保護膜１２は
設けられていない。In the method of the present invention, each FET 11 is first covered with a protective film 12 made of, for example, a silicon nitride film, except for a part of each ground electrode 11a. The protective film 12 protects the FE, T11. The protective film 12 is provided with a pair of openings 12a for exposing a portion of each ground electrode 11a. Each opening 12a is opened along a pair of opposing sides of the PET 11. The portion of the semiconductor wafer substrate 15 where each FET 11 is not constructed is a cutting margin 15a.
The protective film 12 is not provided in this cutting margin 15a portion.
次いで、このような半導体ウェハ１０表面全面にフォト
レジス１−を塗布し、その後に、フォトマスクを用いて
、第２図（イ）および（ロ）に示すように、各ＦＥＴ
１１の保護膜１２を、該保護膜１２の一部を除いて被覆
するレジスト膜２０を形成する。該レジスト膜２０は、
各ＦＩＥＴ １１の接地電極１１ａを外部に露出させる
保護膜１２の開口部１２ａを被覆しないように、該開口
部１２ａ上には設けられておらず、しかも、該開口部１
２ａの周縁部を形成する各ＰＥＴ １１の外周側（ｊＩ
１１縁部の保護膜１２上にもレジスト膜２０は設けられ
ていない。その結果、各ＦＥＴ １１の接地電極１１ａ
は、レジスト膜２０にて覆われることなく。Next, a photoresist 1- is applied to the entire surface of the semiconductor wafer 10, and then each FET is coated using a photomask as shown in FIGS. 2(a) and 2(b).
A resist film 20 is formed to cover the protective film 12 of No. 11 except for a part of the protective film 12. The resist film 20 is
In order not to cover the opening 12a of the protective film 12 that exposes the ground electrode 11a of each FIET 11 to the outside, the opening 12a is not provided above the opening 12a, and the opening 1
The outer peripheral side (jI
The resist film 20 is not provided on the protective film 12 at the edge of the resist film 11 either. As a result, the ground electrode 11a of each FET 11
is not covered with the resist film 20.
保護膜１２の開口部１２ａより外部へ露出している。It is exposed to the outside through the opening 12a of the protective film 12.
次いで、半導体ウェハ基板１５の背面全面にエキスバン
ドフィルム３０を貼着する。該エキスバンドフィルム３
０は１次の切断工程により半導体ウェハ１０を各ＦＥＴ
１１毎に分割する際に、得られる各ＦＥＴ１１が四方
へ飛散することを防止する。Next, an extended film 30 is attached to the entire back surface of the semiconductor wafer substrate 15. The extract band film 3
0, the semiconductor wafer 10 is cut into each FET by the primary cutting process.
When dividing into 11 units, each FET 11 obtained is prevented from scattering in all directions.
このような状態で、半導体ウェハ１０を切り代１５ａに
沿って各１？ＥＴ １１毎に切断する。このとき９半導
体ウヱハ基板１５の切り代１５ａは、第２図（イ）およ
び（ロ）に二点１￥線で示すように、背面側になるに連
れてその開口幅が徐々に小さくなるように１表面側から
順次切削され、断面Ｖ字状の溝部により、各ＦＥＴ １
１に分割する。これにより得られる各ＦＥＴ １１の切
断面１１ｂは所定の傾斜面になる。In this state, the semiconductor wafer 10 is cut along the cutting margin 15a by 1 ? Cut every ET 11. At this time, the cutting width 15a of the 9 semiconductor wafer substrate 15 is such that the opening width gradually becomes smaller toward the back side, as shown by two dots and lines in FIGS. 2(a) and 2(b). Each FET 1 is cut sequentially from the surface side of the
Divide into 1. The resulting cut surface 11b of each FET 11 becomes a predetermined inclined surface.
このような切削には２例えば、刃先にテーバ角を有する
グイシングツ−が用いられる。For such cutting, for example, a guissing tool having a Taber angle at the cutting edge is used.
このとき、前述のように、半導体ウェハ１０の背面には
エキスバンドフィルム３０が貼着されているため、半導
体ウェハｌＯが各ＦＥＴ １１に分割されても。At this time, as described above, since the extended film 30 is attached to the back surface of the semiconductor wafer 10, even if the semiconductor wafer IO is divided into each FET 11.
各ＰＥＴ １１は周囲に飛散するおそれがない。There is no risk that each PET 11 will be scattered around.
次に、エキスバンドフィルム３０上に貼着された状態の
各ＰＵＴ １１は９例えばエキスバンドフィルム３０と
共に、真空蒸着器内に装着されて蒸着され。Next, each PUT 11 attached to the expanded film 30 is placed in a vacuum evaporator together with, for example, the expanded film 30, and vapor deposited.
第３図に示すように、各ＦＥＴ １１の表面全面が、導
電膜として例えばＴｉとＡｕの２層構造でなる金属膜４
０により被膜される。該金属膜４０は、各ＦＥＴ １１
を保護する保護膜１２の開口部１２ａを通って、該ＦＥ
７１１の接地電極１１ａに強く接着されている。そして
。As shown in FIG. 3, the entire surface of each FET 11 is covered with a metal film 4 having a two-layer structure of, for example, Ti and Au as a conductive film.
covered by 0. The metal film 40 connects each FET 11
The FE passes through the opening 12a of the protective film 12 that protects the FE.
It is strongly adhered to the ground electrode 11a of 711. and.
該金属膜４０は、各ＦＥＴ １１の周側面である傾斜面
１１ｂ上にも積層されている。このとき、 ＦＥＴ １
１表面のレジスト膜２０上に積層された金属膜と、保護
膜１２の開口部１２ａ内に積層された金属膜とは段差が
生じ１両金属膜は不連続状態となる。The metal film 40 is also laminated on the inclined surface 11b, which is the peripheral side surface of each FET 11. At this time, FET 1
There is a level difference between the metal film stacked on the resist film 20 on one surface and the metal film stacked inside the opening 12a of the protective film 12, and the two metal films become discontinuous.
このようにして、エキスバンドフィルム３０上の各ＦＥ
Ｔ １１表面全面が金属膜４０にて被覆されると。In this way, each FE on the extract band film 30
When the entire surface of T 11 is covered with the metal film 40.
各ＦＥＴ １１は、エキスバンドフィルム３０と共に、
有ｉ溶剤を用いた剥離液中に浸漬され、各ＦＥＴ １１
上に積層されたレジスト膜２０は、金属膜４０の不連続
部分から浸入する剥離液により除去される。これにより
、該レジスト膜２０上に積層された金属膜４０が該レジ
スト膜２０と共に、 ＰＥＴ １１から除去され。Each FET 11, together with the extract band film 30,
Each FET 11 is immersed in a stripping solution using a solvent.
The resist film 20 laminated thereon is removed by a stripping solution that enters from the discontinuous portion of the metal film 40. As a result, the metal film 40 laminated on the resist film 20 is removed from the PET 11 together with the resist film 20.
第４図（イ）および（ロ）に示すように、それぞれの周
側面の傾斜面である切断面１１ｂ上に金属膜４０が積層
されたＦＥＴ １１を有する各半導体チップ１６がエキ
スバンドフィルム３０に貼着された状態で形成される。As shown in FIGS. 4(a) and 4(b), each semiconductor chip 16 having an FET 11 on which a metal film 40 is laminated on a cut surface 11b, which is an inclined surface of each peripheral side, is attached to an expanded film 30. Formed in a pasted state.
そして、各半導体チップ１６の金属膜４０はＦＥＴ １
１の接地電極１１ａと直接接着された状態で残り、該接
地電極１１ａと金属膜４０とは電気的に接続されている
。The metal film 40 of each semiconductor chip 16 is connected to the FET 1
The metal film 40 remains directly bonded to the ground electrode 11a of No. 1, and the ground electrode 11a and the metal film 40 are electrically connected.
このようにして製造された各半導体チップ１６は。Each semiconductor chip 16 manufactured in this way.
エキスバンドフィルム３０を引き延ばすことにより。By stretching the stretch film 30.
それぞれに分離され、その後に、エキスバンドフィルム
３０より離脱され、第５図に示すように、パンケージの
基板５１におけるグランド部５１ａ上にグイボンディン
グされる。このとき、半導体チップ１６は基板５１上の
グランド部５１ａに２例えば、 Ａｕ −Ｓｎの合金を
主成分とする導電性ペースト５３により固着される。該
導電性ペースト５３は、半導体チップ１６における各Ｆ
Ｅ７１１周側面の切断面１１ａ上に積層された金属膜４
０にも接着され、該導電性ペースト５３を介して金属膜
４０とグランド部５１ａとが電気的に接続される。従っ
て、 ＦＥＴ １１の接地電極１１ａが、ボンディング
ワイヤを用いることなく、該金属膜４０および導電性ペ
ースト５３を介して、基板５１のグランド部５１ａと電
気的に接続される。After that, they are separated from each other and then separated from the extended film 30, and as shown in FIG. 5, they are bonded onto the ground portion 51a of the substrate 51 of the pan cage. At this time, the semiconductor chip 16 is fixed to the ground portion 51a on the substrate 51 with, for example, a conductive paste 53 whose main component is an alloy of Au-Sn. The conductive paste 53 connects each F in the semiconductor chip 16.
Metal film 4 laminated on the cut surface 11a of the circumferential side of E711
0, and the metal film 40 and the ground portion 51a are electrically connected via the conductive paste 53. Therefore, the ground electrode 11a of the FET 11 is electrically connected to the ground portion 51a of the substrate 51 via the metal film 40 and the conductive paste 53 without using a bonding wire.
（発明の効果）
本発明の半導体チップの製造方法は、このように、パッ
ケージやリードフレーム等の導体部分あるいはグランド
部分と、ワイヤボンディングを用いることなく電気的に
接続し得る半導体チップを容易に製造し得る。(Effects of the Invention) As described above, the semiconductor chip manufacturing method of the present invention can easily manufacture a semiconductor chip that can be electrically connected to a conductor portion or a ground portion of a package or lead frame without using wire bonding. It is possible.
４、 パ の なＬ
第１図（イ）は本発明方法に使用される半導体ウェハの
平面図、第１図（ロ）は第１図（イ）のＡ−Ａ線におけ
る断面図、第２図（イ）は本発明方法の一工程における
半導体ウェハの平面図、第２図（ロ）は第２図（イ）の
Ａ−Ａ線における断面図、第３図は本発明方法のさらに
他の工程における半導体チップの断面図、第４図（イ）
は本発明方法のさらに他の工程における半導体ウェハの
平面図、第４図（ロ）は第４図（イ）のＡ−Ａ線におけ
る断面図、第５図は本発明方法により得られた半導体チ
ップをパッケージに装着した状態の断面図、第６図は従
来の半導体チップをパッケージに装着した状態の断面図
である。4. Figure 1 (A) is a plan view of a semiconductor wafer used in the method of the present invention, Figure 1 (B) is a cross-sectional view taken along line A-A in Figure 1 (A), Figure (A) is a plan view of a semiconductor wafer in one step of the method of the present invention, Figure 2 (B) is a sectional view taken along line A-A in Figure 2 (A), and Figure 3 is a further step of the method of the present invention. Cross-sectional view of the semiconductor chip in the process of FIG. 4 (A)
4 is a plan view of a semiconductor wafer in yet another step of the method of the present invention, FIG. FIG. 6 is a sectional view of a conventional semiconductor chip mounted in a package.
１０・・・半導体ウェハ、 １１・・・ＦＥＴ、 ｌｌ
ａ・・・接地電極。10... Semiconductor wafer, 11... FET, ll
a... Ground electrode.
１１ｂ・・・切断面、１２・・・保護膜、１２ａ・・・
開口部、１５・・・半導体ウェハ基板、１６・・・半導
体チップ、 ２０・・・レジスト膜、３０・・・エキス
バンドフィルム、４０・・・金属膜。11b...Cut surface, 12...Protective film, 12a...
Opening, 15... Semiconductor wafer substrate, 16... Semiconductor chip, 20... Resist film, 30... Extended film, 40... Metal film.
以上that's all
Claims (1)
、各半導体素子の表面に設けられた接地電極の少なくと
も一部が露出するように、レジスト膜にて被覆する工程
と、 その半導体ウェハを、切断面が所定の傾斜面となるよう
に切断して各半導体素子に分割する工程と、 分割された各半導体素子の切断面と各半導体素子の表面
全面とを、導電膜にて被覆する工程と、該切断面を被覆
する導電膜が各半導体素子における表面の接地電極に接
続した状態で残るように、各半導体素子表面の所定位置
を被覆するレジスト膜を、該レジスト膜を被覆する導電
膜と共に各半導体素子から除去する工程と、 を包含する半導体チップの製造方法。[Claims] 1. A step of covering the surface of a semiconductor wafer on which a large number of semiconductor elements are formed with a resist film so that at least a part of a ground electrode provided on the surface of each semiconductor element is exposed. , the step of cutting the semiconductor wafer into individual semiconductor elements so that the cut surface has a predetermined slope; A resist film covering a predetermined position on the surface of each semiconductor element is coated with the resist film so that the conductive film covering the cut surface remains connected to the ground electrode on the surface of each semiconductor element. a step of removing the conductive film from each semiconductor element together with a conductive film covering the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16546288A JPH0666389B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor chip manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16546288A JPH0666389B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor chip manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0215653A true JPH0215653A (en) | 1990-01-19 |
| JPH0666389B2 JPH0666389B2 (en) | 1994-08-24 |
Family
ID=15812876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16546288A Expired - Fee Related JPH0666389B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor chip manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666389B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002170788A (en) * | 2000-11-29 | 2002-06-14 | Murata Mfg Co Ltd | Method of manufacturing electronic component |
-
1988
- 1988-07-01 JP JP16546288A patent/JPH0666389B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002170788A (en) * | 2000-11-29 | 2002-06-14 | Murata Mfg Co Ltd | Method of manufacturing electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0666389B2 (en) | 1994-08-24 |
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