JP2000332049A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable electroplating with one plating equipment, irrespective of kinds of silicon substrates in the state of a wafer, and make the height of columnar electrodes more uniform, in a semiconductor device having the columnar electrodes formed by electroplating. SOLUTION: A tray 11 for plating is used, in which a recessed part for silicon substrate arrangement is formed in the almost central part of the upper surface of a rectangular insulating substrate 12, and a metal layer 14 is formed in a region except the recessed part for silicon substrate arrangement and specified three edge parts, on the upper surface of the insulating substrate 12. A silicon substrate 21 in a wafer state is arranged in the recessed part for silicon substrate arrangement, a plating resist pattern 34 is formed, electroplating is performed by using the metal layer 14 or the like as a plating current path of one side, and columnar electrodes are formed on the silicon substrate 21. In this case, dummy columnar electrodes are formed on the metal layer 14 in the peripheral part of the silicon substrate 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art For example, when manufacturing a semiconductor device such as an LSI chip provided with a columnar electrode, as an example, as shown in FIGS. 20A and 20B, first, as shown in FIGS. The connection pads 4 formed on the silicon substrate 1 are exposed through the openings 3 formed in the insulating film 2 formed on the substrate 1, and a base metal layer 5 is formed on the entire upper surface thereof. On the upper surface of the metal layer 5, a plating resist pattern 6 is prepared at a portion other than a portion corresponding to three predetermined locations 5 a on the outer peripheral portion and the connection pad 4. In this case, three predetermined locations 5a on the outer peripheral portion of the upper surface of the underlying metal layer 5 are exposed without being covered with the plating resist pattern 6. This exposed portion 5a is used as one plating electrode and the upper surface of the underlying metal layer 5 is exposed. This is to ensure the sealing performance when plating the outer peripheral portion. Note that FIG.
In (A), a chain line indicates a dicing street.

When electrolytic plating of copper or the like is performed using the plating resist pattern 6 as a mask and the underlying metal layer 5 as one plating current path, the plating resist pattern 6
Column electrode 7 on base metal layer 5 in opening 6a of
(See FIG. 21) is formed. Next, the plating resist pattern 6 is peeled off, and unnecessary portions of the base metal layer 5 are removed by etching using the columnar electrodes 7 as a mask. Then, silicon is formed along the dicing street indicated by a dashed line in FIG. When the substrate 1 is diced, a plurality of semiconductor chips (semiconductor devices) as shown in FIG. 21 are obtained.

[0004] The amount of plating deposited by electrolytic plating depends on the density of lines of electric force during plating.
It is uniform at the center of the silicon substrate 1 but gradually increases toward the outer periphery. Therefore, when no countermeasures are taken, the height of the columnar electrode 7 formed on the outer peripheral portion of the silicon substrate 1 becomes higher than that formed on the central portion, and the height of the columnar electrode 7 varies. Will happen.
Therefore, as shown in FIG. 20A, a dummy opening 6b is formed in the plating resist pattern 6 outside the effective area of the silicon substrate 1 (the area where a semiconductor chip as shown in FIG. 21 is obtained). By forming a dummy columnar electrode on the base metal layer 5 in the portion 6b, the height of the columnar electrode 7 formed in the effective area of the silicon substrate 1 is made uniform.

[0005]

However, in such a conventional method of manufacturing a semiconductor device, the silicon substrate 1
Has a limit on the size outside the effective area, and the underlying metal layer 5
In order to form the exposed portion 5a and secure the sealing performance during plating of the outer peripheral portion of the upper surface of the base metal layer 5, an area having a width of about 4 to 5 mm is required on the outer peripheral portion of the silicon substrate 1. Therefore, the area where the dummy columnar electrodes are formed outside the effective area of the silicon substrate 1 is considerably reduced, and there is a problem that it is difficult to make the height of the columnar electrodes 7 formed within the effective area of the silicon substrate 1 uniform. In addition, there are several types of silicon substrates 1 in a wafer state depending on differences in size (generally, three types of diameters of 5, 6, and 8 inches) and shapes (orientation flat, notch, etc.). There was a problem that a dedicated one had to be used. An object of the present invention is to make it possible to perform electrolytic plating with one plating apparatus regardless of the type of a semiconductor substrate such as a silicon substrate in a wafer state. Another object of the present invention is to make the height of columnar electrodes formed in an effective area of a semiconductor substrate such as a silicon substrate in a wafer state more uniform.

[0006]

According to the present invention, a semiconductor substrate having a base metal layer is disposed on one surface of a tray on which a metal layer is formed, and a metal layer formed on the tray and a base metal of the semiconductor substrate are provided. The layers are connected by a conductive member, and the semiconductor substrate is subjected to electrolytic plating. According to the present invention, the tray on which the metal layer is formed is used, and the metal layer formed on the tray and the base metal layer of the semiconductor substrate are connected by the conductive member to perform the electrolytic plating. By changing the size and shape of the semiconductor substrate arrangement region, electrolytic plating can be performed by one plating apparatus regardless of the type of the semiconductor substrate. in this case,
When a columnar electrode is formed on a base metal layer of a semiconductor substrate placed in a semiconductor substrate placement region of a tray and a dummy plating layer (dummy columnar electrode) is formed on a metal layer around the semiconductor substrate, The area where the dummy plating layer is formed on the metal layer around the substrate can be made sufficiently large, so that the height of the columnar electrode formed in the effective area of the semiconductor substrate can be made more uniform.

[0007]

FIG. 1 is a plan view of a plating tray initially prepared for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2A is a sectional view taken along line AA of FIG. FIG. This plating tray 1
1 has a silicon substrate disposing recess 13 provided substantially at the center of the upper surface of a rectangular insulating substrate 12.
2 has a structure in which a metal layer 14 is provided via an adhesive 15 in a region other than the silicon substrate disposing recess 13 and predetermined three sides (left side, right side, and lower side in FIG. 1). I have.

In the case of forming the plating tray 11, as an example, first, as shown in FIG.
Three predetermined sides (width d ₁ = 10 m) of the upper surface of the insulating substrate 12 made of a rectangular glass epoxy plate or the like of about 4 mm
m) is prepared by pasting a metal layer 14 made of a copper foil or the like having a thickness of about 18 μm via an adhesive 15 made of an epoxy resin or the like in a region excluding about m). Next, in a substantially central portion of the upper surface of the prepared product, using a face mill or the like, according to the size and shape of the target silicon substrate in a wafer state, a silicon substrate having a diameter of about 0.4 mm larger than that is arranged. The recess 13 is formed. As will be described later, the depth h of the silicon substrate disposing concave portion 13 is set to 1/2 to 1 of the thickness of the silicon substrate in a state where the underlying metal layer is provided.
About twice. In the case shown in FIG. 2A, the depth h is
The thickness is substantially the same as the thickness of the silicon substrate provided with the base metal layer.

After preparing such a plating tray 11, a silicon substrate (semiconductor substrate) 21 in a wafer state is placed in the silicon substrate placement recess 13 as shown in FIGS. 3 and 4 (A). I do. In this case, the silicon substrate 21 arranged in the silicon substrate arrangement concave portion 13 corresponds to FIG.
This is as shown in FIG. That is, the opening 2 formed in the insulating film 22 formed on the silicon substrate 21
The connection pad 24 formed on the silicon substrate 21 is exposed via the third metal layer 3, and a base metal layer 25 is formed on the entire upper surface thereof.

Next, as shown in FIGS. 3 and 4A,
The conductive member 26 connects the predetermined three locations on the outer peripheral portion of the upper surface of the base metal layer 25 to the upper surface of the metal layer 14 outside thereof. When the conductive member 26 is formed, for example, the conductive member 26 is formed by applying a conductive paste to three predetermined places (the entire circumference is also possible) by a screen printing method, a dispenser method, a transfer method, or the like. Note that a metal foil, a metal wire, or the like may be used instead of the conductive paste. Conductive member 2
6 is fixed to a predetermined location regardless of its material, and is then maintained by laminating a dry photoresist described later.

Next, as shown in FIGS. 5A and 5B,
The dry photoresist 31 is superimposed on the upper surface of the plating tray 11 including the upper surface of the base metal layer 25, and this superimposed material is passed between a pair of pressure heating rollers 32 and 33 in FIG.
By moving from right to left in (A),
A dry photoresist 31 is laminated on the upper surface of the plating tray 11 including the upper surface of the base metal layer 25. In this case, as an example, a negative type dry photoresist 31 having a thickness of about 120 μm is used, and after preheating at a temperature of about 80 ° C. for about 3 minutes, a pair of pressure heating rollers 3
The transfer speed is about 1m / min.
g / cm ² and a heating temperature of about 110 ° C.
Then, by laminating the dry photoresist 31, the silicon substrate 21 is turned into the silicon substrate placement recess 13.
The conductive member 26 is fixed to a predetermined position as described above.

However, in this case, as shown in FIG. 6, the dry photoresist 31 is not laminated only on the upper side (the remaining one side) of the upper surface of the plating tray 11. Therefore, the metal layer 14 on the upper side of the plating tray 11 is exposed without being covered by the dry photoresist 31. The width d of the exposed portion of the metal layer 14
₂ is about 10 to 20 mm. As a result, not only the outer peripheral portion of the base metal layer 25 but also the portion excluding the upper side portion of the metal layer 14 is sealed by the dry photoresist 31.

Next, by performing predetermined exposure and development, a plating resist pattern 34 is formed as shown in FIGS. 7 and 8A and 8B. In this state, FIG.
8A and 8B, the connection pad 24
An opening 35 is formed in the plating resist pattern 34 in a portion corresponding to the above. 7 and 8
As shown in (A), an effective area of the silicon substrate 21 (an area where a semiconductor chip as shown in FIG. 10 is obtained).
Dummy openings 36 are formed at predetermined positions of the plating resist pattern 34 on the outer base metal layer 25 and at predetermined positions of the plating resist pattern 34 on the metal layer 14 around the silicon substrate 21.

Here, a specific example of exposure and development when forming the plating resist pattern 34 will be described. Exposure is performed by alignment using an alignment mark formed on the silicon substrate 21 and using a stepper exposure method or an exposure method using a glass mask. The exposure wavelength is about 390-450 nm. The exposure amount is about 2800 to 3000 mJ when the exposure wavelength is 420 nm. The development is performed by O ₂ plasma etching or using a developing solution of a 1% NaCO ₃ solution. By the way, if the pattern of the dummy openings 36 formed in the plating resist pattern 34 outside the effective area of the silicon substrate 21 is the same as the pattern of the original openings 35, that is, the areas of the openings 35, 36 are substantially the same. Then, in the case of the stepper exposure method, the actual pattern can be used as a pattern for forming the dummy opening 36,
In the case of the exposure method using a glass mask, it is not necessary to form a special pattern mask.

Next, as pretreatments for electrolytic plating, the openings 35 of the plating resist pattern 34 and the dummy openings 3 are formed.
By applying steam such as pure water or a plating solution to the portion 6, the steam is adhered to at least the opening 35 and the dummy opening 36. This is because the inside of the opening 35 and the dummy opening 36 is wetted with steam, thereby reducing the entrapment of bubbles during electrolytic plating.

Next, electrolytic plating of copper or the like is performed using the plating resist pattern 34 as a mask and the metal layer 14, the conductive member 26, and the base metal layer 25 as one plating current path. As shown in FIG. 3B, columnar electrodes 37 are formed on the underlying metal layer 25 and the metal layer 14 in the openings 35 and the dummy openings 36 of the plating resist pattern 34.
In addition, a dummy columnar electrode (dummy plating layer) 38 is formed. In this case, the electrolytic plating method may be any of a dipping method, a face-down method, and a face-up method. In the case of the dipping method, electrolytic plating is performed by immersing a portion of the plating tray 21 except for the upper side (the remaining side, that is, the exposed portion of the metal layer 14) in a plating solution. That is, the exposed portion of the metal layer 14 is used as an external plating electrode without being immersed in the plating solution.

As described above, the plating tray 11 in which the metal layer 14 is provided around the silicon substrate placement recess 13 on one surface of the insulating substrate 12 is used, and the metal layer 14 is used as one plating current path. Since the plating is performed, the recess 13 for arranging the silicon substrate of the plating tray 11 is formed.
By changing the size and shape of the silicon substrate 21
Regardless of the type, electrolytic plating can be performed by one plating apparatus. In addition, a columnar electrode 37 is formed on the surface side of the silicon substrate 21 arranged in the silicon substrate disposing recess 13 of the plating tray 11, and the silicon substrate 2
1 is formed on the metal layer 14 around the metal layer 1, the metal layer 1 around the silicon substrate 21 is formed.
4, the area for forming the dummy columnar electrode can be made sufficiently large, so that the height of the columnar electrode 37 formed in the effective area of the silicon substrate 21 can be made more uniform. In particular, since the dummy columnar electrode formation area is formed on the metal layer 14 around the silicon substrate 21, the dummy columnar electrode formation area can be provided immediately near the effective area, and a sufficient effect can be obtained.

Next, the plating resist pattern 34 is stripped by applying a predetermined temperature using a stripping agent. Next, the silicon substrate 21 is taken out from the silicon substrate disposing recess 13 of the plating tray 11. Next, unnecessary portions of the base metal layer 25 are removed by dry etching or wet etching using the columnar electrodes 37 and the dummy columnar electrodes 38 as masks. Next, when the silicon substrate 21 is diced along a dicing street indicated by a chain line in FIG. 7A, a plurality of semiconductor chips (semiconductor devices) as shown in FIG. 10 are obtained.

In this method of manufacturing a semiconductor device, the silicon substrate 21 in a wafer state is placed on the plating tray 1.
1 can be handled in a state of being attached to the silicon substrate 21, so that the handling of the silicon substrate 21 in a wafer state can be easily performed and the handling of a wafer state can be easily performed as compared with the case of only the silicon substrate 21 in a wafer state. Damage to the silicon substrate 21 can be reduced. Further, since a dummy columnar electrode forming area can be provided outside the silicon substrate 21 in a wafer state, it is possible to increase the number of chips taken from the wafer.

Incidentally, in the case of the first embodiment,
As shown in FIG. 9A, the plating resist pattern 34
Since the dummy columnar electrode 38 is formed on the metal layer 14 in the dummy opening 36, if the metal layer 14 and the dummy columnar electrode 38 are both formed of, for example, copper, the plating tray 11 cannot be reused. . That is, when the plating resist pattern 34 is peeled off, the silicon substrate 21 is taken out from the silicon substrate disposing recess 13 of the plating tray 11, and then the dummy columnar electrode 38 is removed by etching, and the metal layer 14 is also removed at the same time. . Therefore, the plating tray 11 cannot be reused.

Next, a second embodiment of the present invention in which the plating tray can be reused will be described. First, as shown in FIGS.
A substrate formed by laminating a first metal layer 14 made of a copper foil having a thickness of about 18 μm in a region excluding predetermined three sides of an upper surface of an insulating substrate 12 made of a rectangular glass epoxy plate or the like of about 4 mm. prepare. Next, FIG.
As shown in (B), a second metal layer 16 made of a metal that is not etched by a copper etchant such as gold or platinum is formed on the upper surface of the first metal layer 14 by electrolytic plating to a thickness of 2.
３3 μm.

Next, as shown in FIGS. 21A and 21B, chemical resistance and heat resistance are applied to a region except the upper side and the lower side of the upper surface of the insulating substrate 12 including the second metal layer 16. An insulating film (non-photosensitive resin sheet) 17 made of a polyimide film or the like having the above is laminated. The thickness of the insulating film 17 is appropriately larger than the height of the columnar electrode to be formed. Next, as shown in FIGS. 14A and 14B, a recess 13 for silicon substrate placement is formed in a substantially central portion of the upper surface of the insulating substrate 12 including the insulating film 17 or the like by using a face mill or the like. Form. The depth of the concave portion 13 for arranging the silicon substrate is as follows when the insulating film 17 is excluded.
It is the same as the case shown in FIG. Further, mounting holes 18 are formed at four corners of the insulating substrate 12.

Next, as shown in FIGS. 15A and 15B, the insulating film 17 around the concave portion 13 for arranging the silicon substrate has a width of 2 mm by irradiation with a CO ₂ laser.
A ring-shaped groove (opening) 19 of about
9, the second metal layer 16 is exposed. Thus, the plating tray 11 in this embodiment is formed.

Next, another method of forming the plating tray 11 in this embodiment will be described. First, FIG.
In the state shown in FIG. 2, the concave portion 13 for arranging the silicon substrate and the mounting hole 18 are formed, and then the insulating film 17 is laminated. You may make it. Secondly, in the state shown in FIG. 12, the silicon substrate disposing recess 13 and the mounting hole 18 are formed,
Next, the insulating film 17 may be laminated, and then the portion of the insulating film 17 corresponding to the silicon substrate disposing recess 13 and the portion corresponding to the groove 19 may be removed by photolithography. Third, in the state shown in FIG. 12, the silicon substrate disposing recess 13 and the mounting hole 18 are formed, and then, with reference to FIG. 15, the insulating layer having the opening 13 and the groove 19 by a screen printing method. 17 may be formed.

Next, a case of manufacturing a semiconductor device using the plating tray 11 shown in FIG. 15 will be described. First, as shown in FIGS. 16A and 16B, a silicon substrate 21 in a wafer state is arranged in the silicon substrate arrangement recess 13. Also in this case, a base metal layer 25 is formed on the upper surface of the silicon substrate 21. Next, predetermined three locations on the upper surface of the second metal layer 16 exposed via the groove 19 and the upper surface of the underlying metal layer 25 inside the two locations are connected by a conductive member 26 made of copper.

Next, as shown in FIGS. 17A and 17B, a plating resist pattern 34 is formed only on the upper surface of the base metal layer 25. In this state, an opening 35 and a dummy opening 36 are formed in the plating resist pattern 34. Next, as a pretreatment for electrolytic plating, vapor is adhered to at least the opening 35, the dummy opening 36, and the groove 19. Next, using the plating resist pattern 34 and the insulating film 17 as a mask,
6. When copper electroplating is performed using the conductive member 26 and the underlying metal layer 25 as one plating current path, the underlying metal layer 25 in the openings 35 and the dummy openings 36 of the plating resist pattern 34 is formed, although not shown. A columnar electrode and a dummy columnar electrode (dummy plating layer) are formed thereon, and the second metal layer 16 in the groove 19 of the insulating film 17 is formed.
A dummy plating layer is formed thereon.

In this case, a columnar electrode is formed on the surface side of the silicon substrate 21 arranged in the silicon substrate disposing recess 13 of the plating tray 11 and a dummy plating is formed on the second metal layer 16 around the silicon substrate 21. The second metal layer 1 around the silicon substrate 21
6, the area for forming the dummy plating layer can be made sufficiently large, so that the height of the columnar electrodes formed in the effective area of the silicon substrate 21 can be made more uniform. Since the thickness of the insulating film 17 is appropriately larger than the height of the columnar electrode to be formed, the dummy plating layer formed in the groove 19 is
9 can be prevented from being formed so as to be raised outside.

Next, the plating resist pattern 34 is peeled off. Next, the silicon substrate 21 is taken out from the silicon substrate disposing recess 13 of the plating tray 11. Next, using the columnar electrode and the dummy columnar electrode as a mask, the underlying metal layer 25 is formed.
Unnecessary portions are removed by dry etching or wet etching. Next, along the dicing street indicated by the one-dot chain line in FIG.
When 1 is diced, a plurality of semiconductor chips (semiconductor devices) similar to those shown in FIG. 10 are obtained.

On the other hand, the plating tray 11 in a state where the silicon substrate 21 is taken out from the silicon substrate disposing recess 13 of the plating tray 11 is as shown in FIG. That is, the plating tray 11 in this state
Unlike the initial state shown in FIG. 15B, a dummy plating layer 20 is formed on the second metal layer 16 in the groove 19 of the insulating film 17. In this case, the dummy plating layer 20 is made of copper, and the second metal layer 16 is made of a metal that is not etched by a copper etchant such as gold or platinum. Therefore, even if the dummy plating layer 20 (including the conductive member 26 made of copper in some cases) is removed by wet etching, the second metal layer 16 and the first metal layer 14 made of copper thereunder are not etched. Remains as it is. As a result, the plating tray 11 can be reused.

In the first embodiment, FIG.
Referring to (A), when a metal layer made of gold, platinum, or the like is provided on the upper surface of the metal layer 14 made of copper, the plating tray 11 is moved in the same manner as in the second embodiment. Can be reused.

In each of the above embodiments, the case where the columnar electrode 37 is formed on the connection pad 24 of the silicon substrate 21 using the plating tray 11 has been described, but the present invention is not limited to this. For example, as in the third embodiment of the present invention shown in FIG.
When manufacturing a semiconductor device called “kage”, the rewiring 46 and the columnar electrode 47 may be formed on the silicon substrate 41 using the plating tray 11.

Next, a method of manufacturing the semiconductor device shown in FIG. 19 will be briefly described. First, the connection pads 44 formed on the silicon substrate 41 are exposed through the openings 43 formed in the insulating film 42 formed on the silicon substrate 41 in a wafer state.
Prepare the one on which is formed. And FIG. 1 or FIG.
5, a plating resist pattern for forming a rewiring is formed, and a rewiring 46 made of copper or the like is formed on the base metal layer 45 by electrolytic plating. At this time, when the plating tray 11 shown in FIG. 1 is used, an opening for forming a dummy wiring is formed in the plating resist pattern for forming a rewiring in addition to the opening for forming the rewiring. You may do so. Next, the plating resist pattern for forming the rewiring is peeled off, then a plating resist pattern for forming the columnar electrode is formed, and then the columnar electrode 47 made of copper or the like is formed on the rewiring 46 by electrolytic plating. At this time, when the plating tray 11 shown in FIG. 1 is used, an opening for forming a dummy columnar electrode is formed in the plating resist pattern for forming a columnar electrode in addition to the original opening for forming the columnar electrode. Then, a columnar electrode 47 (including a dummy columnar electrode) is formed in each opening by electrolytic plating using the base metal layer 45 as a cathode electrode side. Next, unnecessary portions of the underlying metal layer 45 are removed by etching using the columnar electrodes 47 and the rewirings 46 as masks, and then a resin sealing film 48 is formed on the entire upper surface excluding the columnar electrodes 47. Dice along the dicing street. Thus, the semiconductor device shown in FIG. 19 is obtained.

[0033]

As described above, according to the present invention, a tray on which a metal layer is formed is used, and the metal layer formed on the tray and the base metal layer of the semiconductor substrate are connected by a conductive member. Since the electroplating is performed, the electroplating can be performed by one plating apparatus regardless of the type of the semiconductor substrate by changing the size and shape of the semiconductor substrate arrangement region of the tray. In this case, a columnar electrode is formed on a base metal layer of the semiconductor substrate arranged in the semiconductor substrate arrangement region of the tray, and a dummy plating layer (dummy columnar electrode) is formed on the metal layer around the semiconductor substrate. Then, the dummy plating layer formation area on the metal layer around the semiconductor substrate can be made sufficiently large, and therefore, the height of the columnar electrode formed in the effective area of the semiconductor substrate can be made more uniform. it can.

[Brief description of the drawings]

FIG. 1 is a plan view of a plating tray initially prepared for manufacturing a semiconductor device according to a first embodiment of the present invention.

2A is a sectional view taken along line AA of FIG. 1, FIG.
FIG. 4 is a cross-sectional view for explaining an example of a method for forming a plating tray.

FIG. 3 is a plan view of an initial manufacturing process.

4A is a cross-sectional view of a predetermined portion in FIG. 3, and FIG. 4B is an enlarged cross-sectional view of a part of the silicon substrate.

FIG. 5A is a cross-sectional view of a manufacturing step following FIG. 4A;
(B) is an enlarged sectional view of a part of the silicon substrate.

FIG. 6 is a plan view of the state shown in FIG.

FIG. 7 is a plan view of the manufacturing process following FIG. 6;

8A is a cross-sectional view of a predetermined portion of FIG. 7, and FIG. 8B is an enlarged cross-sectional view of a part of the silicon substrate.

FIG. 9A is a cross-sectional view of a manufacturing step following FIG. 8A;
(B) is an enlarged sectional view of a part of the silicon substrate.

FIG. 10 is a sectional view of a semiconductor device manufactured by the manufacturing method of the first embodiment.

FIG. 11A is a plan view of an initially prepared plating tray for forming a plating tray according to a second embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along the line BB.

FIG. 12A is a plan view of a forming step following FIG. 11;
(B) is a sectional view along the line BB.

FIG. 13A is a plan view of a forming step following FIG. 12;
(B) is a sectional view along the line BB.

FIG. 14A is a plan view of a forming step following FIG. 13;
(B) is a sectional view along the line BB.

FIG. 15A is a plan view of a forming step following FIG. 14;
(B) is a sectional view along the line BB.

16A is a plan view of an initial manufacturing process when a semiconductor device is manufactured using the plating tray shown in FIG. 15, and FIG. 16B is a cross-sectional view of a predetermined portion thereof.

FIG. 17A is a plan view of a manufacturing step following FIG. 16;
(B) is a sectional view of a predetermined portion thereof.

FIG. 18A is a plan view of a manufacturing step following FIG. 17;
(B) is a sectional view of a predetermined portion thereof.

FIG. 19 is a sectional view of a semiconductor device manufactured by a manufacturing method according to a third embodiment of the present invention;

20A is a plan view for explaining an example of a conventional method for manufacturing a semiconductor device, and FIG. 20B is an enlarged cross-sectional view of a part thereof along line BB.

FIG. 21 is a sectional view of a semiconductor device manufactured by the conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Plating tray 12 Insulating substrate 13 Silicon substrate arrangement concave part 14 Metal layer 21 Silicon substrate 22 Insulating film 24 Connection pad 25 Base metal layer 34 Plating resist pattern 35 Opening 36 Dummy opening 37 Columnar electrode 38 Dummy columnar electrode

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[Procedure amendment]

[Submission date] August 22, 2000 (2008.2.
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

According to the present invention, there is provided an underlayer metal layer.
A semiconductor substrate having disposed on one side of the tray, the tray
A metal layer is formed on one side around the semiconductor substrate.
Is, the underlying metal layer of the semiconductor substrate and a metal layer formed on the tray are connected by the conductive member, below the semiconductor substrate
Forming a mask covering the ground metal layer and the metal layer of the tray;
Forming a part of the base metal layer and the metal layer on the mask.
Is formed, and electrolytic plating is performed on the semiconductor substrate and the metal layer using the mask .

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masami Hiramoto 3-10-6 Imai, Ome-shi, Tokyo Casio Computer Co., Ltd. Ome Office F-term (reference) 4M104 AA01 DD52

Claims (11)

[Claims] 1. A semiconductor substrate having a base metal layer is arranged on one surface of a tray on which a metal layer is formed, and the metal layer formed on the tray and the base metal layer of the semiconductor substrate are connected by a conductive member. And subjecting the semiconductor substrate to electrolytic plating. 2. The method according to claim 1, wherein the tray has a recess, and the semiconductor substrate is housed in the recess. 3. The method according to claim 1, wherein
The method of manufacturing a semiconductor device, wherein the metal layer is formed on an entire periphery of the semiconductor substrate. 4. The semiconductor device according to claim 1, wherein the electroplating on the semiconductor substrate covers the semiconductor substrate and the metal layer, and forms one of the semiconductor substrate and the metal layer. A method for manufacturing a semiconductor device, wherein the method is performed using a mask having an opening exposing a portion. 5. The method according to claim 4, wherein all the openings formed in the mask have substantially the same area. 6. The method according to claim 4, wherein the opening formed in the mask covering the metal layer has a ring shape. 7. The method according to claim 4, wherein the mask is a photoresist. 8. The semiconductor device according to claim 4, wherein the mask covering the semiconductor substrate is a photoresist, and the mask covering the metal layer is a non-photosensitive resin sheet. Method. 9. The semiconductor device according to claim 4, wherein steam is applied to at least an opening of the mask after the mask is formed and before electrolytic plating is performed. Manufacturing method. 10. The invention according to claim 1, wherein at least an upper layer of said metal layer is made of a metal which is not etched by an etching solution of a plating metal formed by electrolytic plating. A method for manufacturing a semiconductor device. 11. The method according to claim 1, wherein a columnar electrode is formed on the base metal layer of the semiconductor substrate by electrolytic plating.