JPH02156363A - State change detecting method for cache memory - Google Patents

Abstract

PURPOSE:To supervise a continuous state change by supervising the contents of a data are area necessary for the processing of a cache memory itself, and successively storing the changed data into a prescribed buffer area possessed by the memory itself whenever the contents change. CONSTITUTION:In the internal program of an information processor DT, a table concerning the supervisory objective address of a cache memory CM designated by an application program is prepared, and the state change is supervised. When the data are exchanged at the section of the other DT, and the state change is generated in the address concerned, a result is notified to the application program. The changed data are successively stored into a buffer BF at the time when the state change has been generated. When the notification request of the change data is received from the application program again, whether the address of the request is the same as the last one is checked, and when they corresponds, the state changed data of the address held in the state buffer BF is notified to the application program, and the newest data can be notified.

Description

[Detailed description of the invention] [Industrial application field]

The present invention is a system comprising a plurality of information processing devices each having a common memory, wherein each of the common memories is coupled to the memory via a common transmission bus, and is given exclusive rights to the transmission bus. The present invention relates to a method for detecting a change in the state of the common memory in a data transmission system that can be rewritten by the information processing device.

[Conventional technology]

FIG. 1 is a system configuration diagram as an embodiment of the present invention, and the conventional technology will be explained below using this diagram. In addition, in the conventional system, the state change buffer BP (
BFI to BFn) are not provided. This example shows C in the data transposition of the so-called token bus method.
PU, M (Ml to Mn) are the same (specific memory, and this specific memory is exclusive to each corresponding CPLI. CM (CMI to CMn) is also common memory, and IB (IBI to IBn) is also internal memory. It is a bus.C
B is a common transmission bus that connects the common memories CMI to CMn, and 2 is a transmission CPU. B (Bl to Bn) are blocks (areas) provided in each common memory CM, and in this example, block B1 is an area that can be rewritten by the CPU II, and blocks B2 . . . Bn are areas that can be rewritten by the CPUs 12, . . . 1n, respectively. However, each CPUI uses the corresponding common memory CM as necessary.
The contents can be read anywhere, but when writing (or rewriting) to the common memory side, the CPU in question receives a token (that is, the right to exclusively use the transmission bus CB, also called line exclusive right). Only then can the corresponding block B of the corresponding common memory CM be rewritten. When writing (or rewriting) to any of the common memories CM is performed in this way, the transmission CPU
2 sends the write (rewrite) data to all other common memories so that the contents of each block B1=Bn in each common memory CMI to CMn become the same. In this way, data transmission is performed between each information processing device DT. FIG. 3 is a time chart for explaining the operation of the main parts of this conventional system. The solid line curve in the figure shows the flow of the application program in the information processing device DT, and (1) in the figure shows the timing of processing other than common memory monitoring of the application program.
(2) indicates the timing at which the CPUI monitors the state change (change in data content) of the common memory CM.
3) indicates the timing at which another information processing device DT rewrites the contents of the corresponding common memory (via the transmission CPU 2). Conventionally, in this type of data transmission method, as in periods TI and T2 in FIG. 3, only when there is a request from an application program, the corresponding CPU sends the corresponding common memory C? I was monitored for changes in the state, and if there was a - degree change in state, the state change monitoring was not performed until there was a request from the application program again. That is, in FIG. 3, the CPU in question monitors changes in the state of the common memory as in period T1 in FIG. 3 (2) at the request of the application program. Then, in this state, when the common memory CM is rewritten by another information processing device DT and a state change a occurs, the CPU in question uses this change data to perform processing in period T2 in FIG. 1 (1). Similarly, the common memory is monitored during period T3 in (2) in the same figure according to the next program request, and the change data of the state change C is captured and shown in (1) in the same figure.
The process is performed during period T4.

[Problem to be solved by the invention]

However, in the above method, when continuously monitoring a specific address of the common memory CM, the application program issues a monitoring request to the relevant CPUI, and then, when a state change occurs, the result is notified to the application program. After that, there is a gap between the periods T1 and T3 in FIG. 3 until a request from the application program is accepted again, and during this period, in other words, something like b that occurred during period T2 in FIG. There was a problem that state changes could not be taken into account. In order to solve the above-mentioned problem, the present invention allows an information processing device to sequentially accumulate and store in a buffer the contents of data changes of status change target addresses accepted from application programs in a common memory, so that data changes can be transferred to application programs. An object of the present invention is to continue to monitor state changes in a common memory within the information processing device 2 even after notification of a state change, thereby reducing the burden on an application program.

[Means to solve the problem]

In order to solve the above problems, the method of the present invention provides a system consisting of a plurality of information processing devices (DT, etc.), each of which is provided with a common memory (CM, etc.), and each of the common memories is connected to the memory. In a system that is connected via a common transmission bus (such as CB) and can be rewritten by the information processing devices that are given exclusive rights to this transmission bus, each of the information processing devices always uses its own information. monitors the contents of the data area necessary for its own processing in the common memory corresponding to the data area, and each time the contents change, it sequentially stores the changed data in a predetermined buffer (such as BP) area that it owns, and , each time it becomes necessary for its own processing, at least refers to the corresponding data in this buffer area and performs the processing.

[For use]

The change data of the state change monitoring target address in the common memory received from the application program is continuously stored in the buffer and monitored even after the state change occurs.
When called again from the application program,
Information on state changes that have occurred up to that point is notified to the application program.

【Example】

Next, the present invention will be explained in detail based on FIGS. 1 and 2. In FIG. 1, each information processing device DTI to DTn
The above-mentioned state change buffer BF is stored in the unique memories M1 to Mn of
(BPI to BFn) are provided, and state changes (data changes) in predetermined areas (designated by the relevant application program) of the common memories Cold to CMn (designated by the relevant application program) are sequentially stored in the buffers BF. Figure 2 is a time chart showing the main operations of Figure 1.
This corresponds to the figure. In Figure 2, (1), (
The solid broken line curve in 2) shows the processing of the application program, and the broken line part in 2) shows the internal program (
In other words, it shows the processing by the operating system). In the present invention, the common memory monitoring process is performed by an application program as shown in FIG. 2 (2), and also by an internal program in parallel with other processes of the application program. That is, in FIG. 2, the application program requests the CPU to monitor the status change of the common memory. In the internal program (operating system) of the information processing device DT, a table is created for the monitored address of the common memory CM specified by the application program, and state change monitoring for the address is performed based on this table. . When a state change occurs at the address in data exchange with another information processing device DT in (2), the result is notified to the application program. Thereafter, the internal program (operating system) of the information processing device DT continues to monitor status changes based on the previously created table of monitoring target addresses, and at the point in time when a status change occurs, The change data is stored in the relevant state buffer BF. When a notification request for change data is received from the application program again in step (3), it is checked whether the address for the request is the same as the previously specified address, and if it is, the corresponding address stored in the state buffer BP is checked. Notify the application program of address state change data. Note that the buffer that stores state change data is a ring buffer (i.e., a buffer in which the addresses of the buffer area where state change data is stored sequentially over time are connected in a circular chain). The latest data can be notified without a re-request from the information processing device. [Effects of the Invention] According to the present invention, the contents of the state change of the common memory are sequentially accumulated and stored in the buffer inside the information processing device. Therefore, even if no state change data request is issued from the application program, state changes can be monitored, and state change monitoring can be performed continuously under the same conditions.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram as an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the main parts of Fig. 1, and Fig. 3 is a conventional time chart corresponding to Fig. 2. be.

Claims (1)

[Scope of Claims] 1) A system consisting of a plurality of information processing devices each having a common memory, wherein each of the common memories is coupled to the memory via a common transmission bus, and the transmission bus is In a system that can be rewritten by the information processing device to which exclusive rights have been given, each of the information processing devices constantly monitors the contents of the data area necessary for its own processing in the common memory corresponding to itself. Each time this content changes, it sequentially stores this changed data in a predetermined buffer area that it owns, and whenever it needs it for its own processing, it at least refers to the corresponding data in this buffer area and performs the processing. A common memory state change detection method characterized by: