JPH02156362A - Control circuit for personal computer - Google Patents

Abstract

PURPOSE:To execute an access at a high speed and to secure the recovery time of elements by controlling an output by the control circuit of an element block, which goes to be an access subject, and generating an access signal in the above mentioned element block with optimum timing. CONSTITUTION:Element controllers 7, 8 and 9 recognizes it by a CPU status signal 14 that a CPU 1 goes to start the access. Then, when it is known by address information 18 and 20 that the access is an access request to the controller itself, an element select signal 23 is made active. It is informed that an access signal generating circuit 2 is controlled. Then, the active start and end of the access signal 25 is controlled by an access signal generating circuit control signal 24. When the activation is finished, the cycle of the CPU 1 is also finished by a ready signal 13. During such a period, access signal 28 and 16 are not made active.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a personal computer or the like.

[Prior art] The CPU of a personal computer has memory and I/O
In order to perform access, an access signal generation circuit is provided, and the output of the circuit is connected to each memory/I/O element or the control circuit of the memory/I/O element, and access is performed based on this access signal. It was being done. FIG. 3 is a simplified diagram for explaining the control circuit of a conventional personal computer. An element or element block connected to a personal computer system (/O
7 to 112) are connected to an access signal (116) generated by decoding the status signal (114) of the CPU (/O1) by an access signal generation circuit (/O2). Therefore, the pulse width of the access signal must be such that it can be permitted in all elements and element blocks connected to the system.

/O3, /O5 are data bus buffers, /O4゜/O
6 is an address bus buffer, 113 is a ready signal to the CPU, 115 is a wait request signal from an element or element block, 117, 119°, 121 is a data bus, 1
18, 120, and 122 indicate address buses, respectively.

[Problems to be Solved by the Invention] First, memory/I/O devices often require a recovery period after the previous access before allowing the next access; Conventionally, due to the difference in setup time of access signals, memory/I/O
It was necessary to process the access signal to be supplied to the element by the control circuit of the element and then supply it to the element.

Second, for accessing elements with very short access times, the access 1 word is possible with a short active pulse width, but for other elements or control circuits of other elements, Inputting short access signals is often restricted, even though the duration of the access is limited, and the access single word pulse width must be the shortest pulse width that can be permitted by all elements or control circuits of the elements connected to the system. must,
Not optimal for devices with very short access times;
This was an obstacle to increasing the efficiency of personal computers.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate such drawbacks and to provide a circuit that increases the efficiency of personal computers.

[Means for Solving the Problems] The present invention provides a personal computer having a CPU, a data bus, an address bus, and a memory/I/O access signal circuit. Access signals (memory read strobe signal, memory write strobe signal, Ilo
・The control circuit of the element block (memory block, etc.) that is being accessed by the CPU at that time controls the output of the read strobe signal, Ilo write strobe signal, etc. By controlling the transmission range to the personal computer system, the access signal is generated at the optimal timing for the element block to be accessed, without considering the influence on other element blocks. It is found in the control circuit of a personal computer.

[Embodiment] FIG. 1 is a diagram showing an embodiment illustrating the operation of a control circuit of the present invention. In this embodiment, two access signals (2
5, 28), which can be increased as necessary. Here, the access signals are a memory read strobe I word, a memory write strobe signal, an I/O
Refers to a read strobe signal or an I/O write strobe signal.

The element or element control (7, 8, 9) is (25
), the shortest pulse widths are close to each other, and on the contrary, the element control (/O, 11, 12) is connected to the other access signal (28).
is considerably different from the shortest pulse width of the access signal that can be granted. The signal indicating which access signal system is connected is (23, 26), and the access signal (25) is output by this signal.
The access signal (28) is controlled not to be output.

When both (23, 26) are not active, that is, when accessing (29, 30), the access signal is output to (16, 25, 28), and the shortest pulse width is the access signal for (2). One shift is predetermined by the signal generation circuit, and this is the same as the method of determining the shortest pulse width of the access signal in the conventional access signal generation circuit.

When the select signal in (23) or (26) becomes active, generation of access signals such as the conventional /O2 is prohibited in (2), and the access signal generation circuit control in (24) or (27) is disabled. The start and end of output of the access signal is controlled by the signal. Inside (2),
There is nothing to set the start and end. 1 antiζko, (24
), the access signal (25) is controlled and becomes active. (2
The access signal 8) is not activated. (29
) is accessed, the access signal becomes (1) as predetermined by the access signal generation circuit (2).
The output starts from B, 25.28) and ends with a pulse width that satisfies both the wait signal of (15) and the internally set shortest access signal pulse width of (2).

That is, (23).

When the select signal (26) becomes active, the circuit controls the output start, period, and transmission range of the access signal on the element control side.

FIG. 2 is a timing chart for explaining the operation of FIG. 1. (14) CPU status signal CP
The element controller recognizes that U is about to initiate an access (18).

When it learns that it is an access request to itself based on the address information in (20), it activates the element select signal in (23) to notify that it will control the access signal generation circuit in (2), and the access signal in (24) The generating circuit control signal (25) controls the activation start and end of the access signal. When finished, (
13) The CPU cycle is also terminated by the ready signal. The access signals during these periods (28) and (16) are not active.

[Effects of the Invention] According to the present invention, generation of an access signal for performing memory/I/O access from the CPU is performed by the CPU at that time.
The control circuit of the element block (memory block, etc.) that is the access target controls the output and further controls the transmission range of the access signal to the personal computer system.

As a result, memory access including RAMDISK of a personal computer can be performed by generating an access signal at the optimal timing and accessing the element block to be accessed without considering the influence on other element blocks. This makes it possible to increase the speed of I/O access, or to secure a recovery period for elements used in personal computers.

[Brief explanation of the drawing]

FIG. 1 is a simple explanatory diagram of an embodiment of the present invention, and FIG. 2 is a timing chart explaining the operation of the control circuit of the present invention. Each word is shown with its active level set to low. FIG. 3 is a diagram briefly explaining the control circuit of a conventional personal computer. 1: CPU 2: Access signal generation circuit 3.5: Data bus buffer 4.6: Address bus buffer ~ 12: Element or element control 13:
Ready signal to CPU 14: Status 1 word from CPU 15: Wait request signal 25: 26: 28: 29° Access signal 21: Data bus 22 Near address bus select signal 27: Control signal access to access signal generation circuit Signal select signal access signal 30: Element control or element 16: 17.19° 18.20° 23: 24° or more Applicant Seiko Epson Corporation Representative Patent attorney Kizobe Suzuki Ike-na, /”---- -111111 Figure 2

Claims (1)

[Claims] CPU, data bus, address bus, memory I/
In a personal computer having an O access signal circuit, generation of an access signal for memory I/O access from the CPU is performed by the CPU at that time.
The control circuit of the element block that was accessed by U controls the output and further controls the transmission range of the access signal to the personal computer system, without considering the influence on other element blocks. . A control circuit for a personal computer, wherein the access signal is generated at an optimal timing for the element block to be accessed.