JPH02154579A - Image sensor for television, movie or photographic recording including solid-state image sensor - Google Patents

Abstract

PURPOSE: To remove the generation of stripes at the time of displaying a picture signal by allowing a clock pulse signal for controlling a solid state sensor to have changes of at least three levels. CONSTITUTION: The shown figure indicates a change (solid line) of a clock pulse Q, a change (broken line) of voltage Vm and a change (alternate long and short dash line) of output voltage Vo when Vi=-V1, i.e., a logic value '0' exists, and Vi=+V1, i.e., a logic value '1' exists, at time t20 when time (t) is a function. In the case of Vi=-Vi, a transistor(TR) N1 is conducted, TRs P1, N2 are interrupted and Vm=V1 and Vo=-V1 are formed in an initial state. When the voltage of the clock pulse Q arrives at threshold voltage VTN2 at time ta, the TR N2 starts to be conducted and the voltage Vm is dropped. In this case, the TR P1 is conducted, the TR N1 is interrupted and then Vo=+V1 and Vm=-V1 are formed by the completely conductive TR P1 and the completely interrupted TR N1. Consequently stripes are not generated on a picture.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates to an imaging device for television, cinema or photographic recording comprising a solid state image sensor for generating an image signal.

More particularly, the invention relates to an imaging device in which the sensor is controlled by a clock pulse signal and operates on the accordion principle in which the information in the sensor is shifted with an open phase, a transfer phase and a closed phase. . In this case, the open phase includes the expansion of the image information element and the transfer of image information, the transfer phase includes the transfer of image information, and the close phase includes the transfer of image information and the transfer of image information at the designated position. This includes reduction of the element. The sensor also has a driving shift register comprising a series of resistor elements whose outputs are coupled to the electrodes of the sensor, while a tarok pulse input is coupled to the series of resistor elements; and,
These register elements have a series switch controlled by a clock pulse followed by an inversion circuit.

The above-mentioned imaging device having a frame transfer sensor is
Magazine "Philibus Technica" published in December 1986
LiL/BuJ Vol, 43. It is known from the article "Determined body image sensor, accordion imager" published on pages 1 to 8 of No. 1/2. The driving shift register of the sensor comprises, for each register element, an NMO3l- transistor as a series switch and an inverting circuit (inverter circuit) having a PMO3, # and NMO3) transistor between the power supply terminals,
The interconnected drains of the latter two transistors form the resistor output and are connected to the input of the following resistor element. The drive shift register shifts information on an accordion principle from the image area of the sensor to a storage area, from which it is transferred via parallel manual serial output shift registers to the sensor output terminals for supplying image signals. , image information is available in row and field sequence.

[Summary of the invention]

However, when displaying an image signal in the above-mentioned device, it seems that a stripe-like problem actually occurs. Thus, horizontal stripes appear in the displayed image in the row scanning direction. Therefore, an object of the present invention is to realize an imaging apparatus that can eliminate the problem of fringes even if they occur when displaying a generated image signal. To this end, the imaging device according to the invention is characterized in that the clock pulse signal has a variation with at least three levels.

This invention is based on the knowledge that the above-mentioned stripe problem is caused by an incorrect transfer step when shifting information based on the accordion principle. That is, this incorrect transfer step is related to the structure of the clock pulse signal, if the clock pulse signal has a known transition with two levels. Additionally, incorrect transfer steps such as those described above occur during positive-to-negative inversions (logic 1 to logic 0, which occurs immediately), and during negative-to-positive inversions (logic 1 to logic 0, which occurs immediately). NMO8 and PM[ ] during the inversion from the value O to the logic value 1, this inversion is slow
The different switching speeds of the S l-transistors are also relevant. Choosing a variation with at least three levels of the clock pulse signal thereby optimizes the transfer step and thus prevents streaking problems when displaying the image signal.

A variation with at least three levels of the clock pulse can be realized by a step variation with three levels or a sawtooth variation with a large number of levels.

The adoption of step-like or sawtooth-like changes in the clock pulses to be supplied to the solid-state image sensor is described in the magazine RS published in April 1976 by Pergamon Press (UK).
solid-3tate 81 electronics J
Vol.

This is known from the article "Influence of Clock Waveform on Charge Transfer in Three-Phase CCD" published in No. 19, No. 4, pages 279 to 287. The clock pulses with the changes indicated therein act with such changes only with respect to the information transfer within the sensor itself. However, according to the invention, the information transfer within the sensor itself takes place under the control of a two-level tarlock pulse, such that the lock pulse is obtained from a drive shift register, in which the drive shift register Clock pulses having the above-mentioned at least three levels are applied to the series switches of the shift register element.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the circuit diagram of FIG. 1a, reference numeral FT indicates an image sensor, and each electrode E of this image sensor is connected to each output terminal of the drive shift register SR.

The image sensor FT is, for example, a frame transfer sensor, an interline sensor, or a combination thereof. Here, some of the electrodes E of the sensor are designated by symbols BO, Bl, B2 to B6. Although each electrode E is partially shown, it is assumed that it extends further into or across the sensor FT, insulated from the semiconductor material of the sensor. Note that for the detailed configuration of the frame transfer sensor type sensor PT, please refer to the above-mentioned article. The part of the sensor electrode E shown in FIG. 1a is, for example, in the storage area of the sensor FT. FIG. 1b also shows an example of the charge pattern generated under the electrodes E of the sensor PT depending on the voltage applied to each electrode E. Here, a positive voltage voltage v1 representing a logical value 1 is generated at the electrodes BO, IE3, and B4, while a negative voltage −vl representing a logical value 0 is generated at the electrodes B1, IE3, and B4.
Assume that it occurs at B2, B5, and B6.

FIG. 1h shows a corresponding pattern at time tlo. If the electron charge packets contain image information, these charge packets are connected to the positive electrode BO1B3.
and B4, these packets are shown in shading in the figure, and a barrier occurs between them. Now, if a certain known pattern "r 01010101" is related to image recording in the image area (illustrated path) of the sensor in question, then in this case the known pattern r 0OI100IIJ is the transfer phase of the information shift based on the accordion principle. It's all about things. Therefore, after the next transfer step, "olloollo
'', the five values to the left of this pattern are shown at time t111 in FIG. 1b. This time t111 corresponds to an ideal transfer step. Note that FIG. 1a shows two clock pulse signals o1 and 2 as a function of time t.
These times tlO and tll are shown in FIG. These signals 01 and 02 shown are the driving shift register S
This occurs in the case of the known two-phase clock pulse control of R. However, according to one aspect of the invention,
What occurs under the control of the rectangularly varying clock pulses 01 and 02 shown in FIG.
This is not the charge pattern shown at li, but the pattern shown at time top, and this time tllp corresponds to the actual transfer step. And, Fig. 1b shows this time tll
The charge pattern at p is shown, and such a pattern occurs because most of the barrier at locations indicated by Y has already been formed while the barrier at locations indicated by X has not yet been removed. This shaded charge packet spreads out, so to speak, and mixes with its neighboring packets. This undesirable mixing results in stripes in the row scanning direction, that is, in the horizontal direction when the final image signal is displayed. The problem with this stripe is due to the combination of an information groove below electrode B3, which is not wide enough and not deep enough, through which the charge spreads, and the slow removal of the barrier (X) and the barrier Due to the fast formation (Y) and the period difference, this period difference is caused by the driving shift register using square wave clock pulses 01 and 02 as shown in FIG. 1a.

For the sake of completeness of the description and in anticipation of FIGS. 2b and 3b, a known drive shift register SR will be briefly described. FIG. 1a shows the shift register elements SRI to SR6 of the column (SRI to 5R6) of the register SR.
It is shown. Here, each series switch controlled by a tarok pulse is connected to a transistor N22
to N26. In addition, each inverter circuit is connected to PMO3) transistor pH to B15 and N
MO8) is formed by transistors Nil to N15. In this case, the transistor pH to B15,
The drain electrodes N11 to N15 constitute respective resistor output terminals, and each output voltage vo1, Vo2, Vo3, V to be supplied to the electrodes B1 to R5 is applied to these output terminals.
o4 and vO5 forces are generated. Further, the source electrodes of the transistors pH to PI5 and transistors N11 to N15 are connected to power supply terminals carrying voltages +v1 and vl, respectively.

It goes without saying that one of these two power supply terminals may be connected to ground. transistor p
H, Nil to PI5. Each interconnected gate of N15 is connected to the drain or source electrode of the preceding series switch transistor, respectively;
The interconnected gate electrodes of transistors N23 and N25 input the clock pulse signal Q1, and the interconnected gate electrodes of transistors N22 and N2
The interconnected gate electrodes of 4 and N26 input the clock pulse signal 02.

Furthermore, in the transistors N22 to N26, the electrode with the highest voltage operates as a drain electrode, and the electrode with the lowest voltage operates as a source electrode.

According to the measures of the invention, the clock pulse signals 01 and 02 vary in a sawtooth manner as shown in FIG. 2a as a function of time t.
is used to control the drive shift register Sfl of FIG. 1a. Here, the symbols t20, t21 and t
22 represents three times. In this case, time t20
corresponds to time t10 shown in FIG. 1a, and this relationship also holds true for the corresponding voltage patterns in FIGS. 1b and 2d. Further, FIG. 2h shows the shift register element in a general representation. Transistors P1 and N1 in this diagram
and N2 correspond to the transistor shown in a similar configuration in FIG. 1a. Further, the output voltage is indicated by Vo, and the output voltage is applied to the electrode E, which is indicated as a capacitance. Further, the input voltage is indicated by vl, and the input terminal is the voltage V of the preceding resistor element.

It is. Further, the symbol Vm is the inverter circuit (PI, N1
) represents the voltage at the input terminal of the A clock pulse Q is then applied to the gate electrode of transistor N2. Note that the gate-source threshold voltages of transistors N1 and N2 are represented by VT old and VTN2, respectively. When voltage v1 is smaller than voltage Vm, the electrode carrying voltage Vi operates as a source electrode, while when voltage v1 is larger than voltage Vm, the electrode carrying voltage Vm operates as a source electrode.

Next, FIG. 2C shows the time t when the time t is a function.
Changes in clock pulse Q (solid line), changes in voltage Vm (dashed line) and output voltage vO when vl−−v1, or logic value 0, exists at 20 and when Vi−+ Vl, or logic value 1, exists. (-dotted chain line). Also, threshold hole 1”K pressure VTN1=
VTN2 is plotted as a voltage level located between power supply voltages +v1 and -v1.

In the case of Vi--Vl in FIG. 2C, as an initial state, the transistor Nl in FIG. 2b is conductive, the transistors P1 and N2 are cut off, and Vm=+V1 and vO
vl is established. When the voltage of the clock pulse Q reaches the threshold voltage VTN2 at time ta, the transistor N2 starts conducting and the voltage Vm decreases.

In this case, transistor P1 is conductive, transistor N1 is cut off, and then transistor P1 is fully conductive.
With transistor N1 completely cut off, Vo-+
Vl and Vm=-Vl. Therefore, a charge transfer under the electrode E accompanies the above-mentioned transition of the output voltage vO from −v1 to +v1. Therefore, it is considered that the pattern shown in FIG. 2d exists at the illustrated time t21. Here, the barrier that is about to be removed at X is Vi=
-Vl (Vl is logical value 0), -Vl<Vo<
+ Vl.

v1-+v1 (vic logical value 1) in FIG. 2C corresponds to the barrier that is about to form at Y in FIG. 2d.

In this case, as an initial state, the transistor P1 in FIG. 2b is conductive, the transistors N1 and N2 are cut off, and Vm--Vl and Vo-+Vl are established.

At time ta, when the voltage of clock pulse Q reaches the keto-source threshold voltage VTN2, transistor N2 becomes conductive and voltage Vm increases as the clock pulse voltage increases. Next, at time tb, the voltage V
When m reaches the threshold voltage VTNI, transistor N1 conducts while transistor P1 shuts off. Then with transistor N1 completely conducting and transistor P1 completely blocking Vo=-Vl and Vm
=+V1. Therefore, a charge transfer under the electrode E accompanies the above-mentioned transition of the output voltage Vo from −vl to −v1. Thus, it is believed that the pattern shown in FIG. 2d exists at the time t22 shown with the barrier formed at Y.

And Figures 2C and 2d show that the removal of the barrier at X begins earlier than the formation of the barrier at Y. That is, along with the above-mentioned continuous removal, there is subsequent formation. Thus, an optimal transfer step results, as can be seen by comparing the pattern at time t22 in FIG. 2d with the bang at time top in FIG. 1b.

According to another measure of the invention, the clock pulse signal 0 varies stepwise as shown in FIG. 3a as a function of time t.
1 and 02 are used. Symbols t31 and N in Figure 3a
32 indicates a time corresponding to time t21 and N22 in FIG. 2a, while time t30 indicates a time later than time t20. FIG. 3a also shows a clock pulse signal having a stepwise variation with three levels. What is common with the sawtooth variation shown in FIG. 2a is that both signal variations have at least three levels.

That is, the serrations can be formed with step-like changes having multiple levels. Also, as an alternative to the sequence of clock pulse changes such as lowest level, middle level, highest level, and lowest level as shown in Figure 3a, There will also be variations in the order, such as the highest level and then the lowest level. In this case, it becomes a step-like change with discontinuous steps.

Figure 3b shows the gate-to-lass threshold voltage, denoted by VTN2+ΔV, which has been changed from that shown in Figure 2b. This change was made in the 3rd c.
This will be referred to when explaining the voltage level L1 in the figure.

As described with reference to FIG. 2c, FIG. 3c shows the clock pulse Q and the voltage changes Vm and Vo.

In the case of Vi--Vl, Vm=+V1 and Vo--Vl
There is an initial state in which transistor N1 is conducting, while transistors P1 and N2 are off. Time t30
In , the lock pulse Q has a voltage step up to level L1 that is greater than the gate threshold voltage VTN2, so transistors N2 and Pl conduct;
Transistor N1 is cut off. The transition of the output voltage Vo from -v1 to +v1 causes the charge under the electrode E to be transferred. Since it is considered that the charge transfer is completely realized at time t31, the pattern shown in FIG. 3d corresponds to this. Note that the symbol X in the pattern at time t30 in FIG. 3d indicates that barrier removal begins at this point.

Next, if Vi=+Vl, Vm knee v1 and Vo=
There is an initial state of 1v1, with transistor P1 conducting while transistors N1 and N2 are off. At time t30, lock pulse Q has a voltage step up to level L1. Therefore, the transistor N2 has a voltage of Vi-+V1 at its drain electrode, a clock pulse voltage of Q=L] at its gate electrode, and a voltage of Vmvl at its source electrode. In this case, since the voltage level L1 is larger than the gate-source threshold voltage VTN2,
Transistor N2 is biased to conduct, and voltage Vm changes as shown. On the other hand, by selecting the voltage level 1.1, transistor N1 is maintained in a cut-off state, and transistor P1 is maintained in a conductive state. This condition continues until the next voltage step to a higher level occurs with clock pulse Q at time tc. At this stage, transistors N2 and Nl are conductive, while transistor P1 is turned off. And the output voltage V.

The transition from +v1 to -v1 causes the charge under electrode E to be transferred. Therefore, since it is considered that the transfer of the second charge is completely realized at time t32, the pattern shown in FIG. 3d corresponds to this. Furthermore, at time t32 in Fig. 3d
The symbol Y in the pattern indicates that the formation of the barrier has been completed at this point.

Regarding the voltage level I,1, this level must be greater than the gate-source threshold voltage of transistor N2, but smaller than the sum of the threshold voltages of transistors N1 and N2. A high voltage Vi-Vm with a value slightly smaller than 2Vi is applied to the transistor N.
2 is accompanied by an increase in its threshold voltage by ΔV. in this case,
Assume that a voltage -vl is applied to the substrate of transistor N2. According to the above, the following relationship must be satisfied.

VTN2< LL < (VTNI+VTN2+ △
V) Figures 2a and 3a with at least three levels
Optimizing the charge transfer under electrode E of FIG. 1a using the clock pulses shown introduces an intermediate stop in the charge transfer. That is, starting from logic pattern 0011.0011 on electrode E, intermediate pattern 01110111 is formed first, and then final pattern 0 is formed.
1100110 follows. On the other hand, if the known square wave clock pulse of FIG. 1a were used, the undesirable transient pattern 00100010 would automatically occur;
This causes the charge packets to intermingle with each other, resulting in horizontal stripes in the displayed image, as described above.

In addition, although the transfer phase in the information shift based on the accordion principle was illustrated above, the tarokku pulse Q having at least three levels can be applied to the accordion principle without causing any other problems and with the same effect as above. It can also operate in the open and closed phases of the information shift based on . Furthermore,
It can also be used for 3-phase, 4-phase or polyphase control.

[Brief explanation of the drawing]

Figure 1a shows a circuit diagram of a part of the image sensor, and Figure 1b shows the charge pattern under the sensor electrode obtained when the drive shift 1 register of the image sensor is driven with a known two-phase clock pulse. 2a is a waveform diagram showing an example of a two-phase clock pulse according to the present invention; FIG. 2b is a general circuit diagram of a register element of a drive shift register; FIG. 2c is a clock pulse diagram of FIG. 2a. and a waveform diagram showing the waveform of the signal obtained as a result, FIG. 2d is an explanatory diagram showing the charge pattern under the sensor electrode obtained as a result of the same tarlock pulse, and FIG. 3a is another example of the two-phase clock pulse according to the present invention. FIG. 3h is a general circuit diagram of the register element of the drive shift register; FIG. 3C is a waveform diagram showing the clock pulse of FIG. 3a and the waveform of the resulting signal; FIG. 3d is a waveform diagram showing the waveform of the clock pulse of FIG. is an explanatory diagram showing a charge pattern under the sensor electrode obtained as a result of the same tarok pulse. register, port 1.02...clock pulse signal, SR
... Drive shift register, vl... Input voltage of register element, Vm... Voltage at input end of inversion circuit,
Vo...output voltage of resistor element, VTNI, VTN2
...Gate-source threshold voltage. Applicant: N.B. Philips Fluirampenfabriken

Claims (1)

[Scope of Claims] 1. An imaging device for television, film, or photographic recording comprising a solid-state image sensor that generates an image signal, the sensor being controlled by a clock pulse signal to operates on the accordion principle of shifting information with an open phase, a transfer phase and a close phase, the open phase comprising an expansion of the image information element and the transfer of the image information, and the transfer phase including the transfer of the image information. and the closing phase includes transferring image information and shrinking the image information element at the specified location;
The sensor has a driving shift register having a series of register elements, the outputs of which are coupled to the sensor electrode, while the clock pulse inputs are coupled to the series of register elements, and the outputs of the register elements are coupled to the sensor electrodes. An imaging device comprising a series switch controlled by a clock pulse and an inversion circuit following it, characterized in that the clock pulse signal has a variation having at least three levels. 2. The imaging device according to claim 1, wherein the clock pulse signal has a step-like change. 3. The imaging device according to claim 1, wherein the clock pulse signal has a sawtooth variation.