JPH02154398A - Test circuit for memory - Google Patents

Abstract

PURPOSE:To simplify the circuit configuration of the test circuit for memory and eliminate the necessity of control signals from the circuit by providing a constant-current source which supplies electric currents to plural transistors, the gates of which are respectively connected with plural nodes, and giving weights to the current driving abilities of the plural transistors in a fixed way. CONSTITUTION:This test circuit is constituted of a memory circuit 1, MOS field effect transistors 2-5, resistance 6, DC power source 7, and output terminals 8-11 of the circuit 1. When, for example, the transistors 2-5 are of N channel type and logic levels of outputs of the output terminals 8, 9, 10, and 11 of the memory circuit 1 are respectively '1', '0', '1', and '0', the electric current flowing to the resistance 6 becomes 5I. Therefore, the logic levels of the outputs at the four output terminals 8-11 of the memory circuit 1 can be observed when the electric current flowing to the resistance 6 is measured. Therefore, the circuit configuration of the test circuit can be simplified and the necessity of control signals can be eliminated from the circuit.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to a memory test circuit.

[Prior Art] Conventionally, in this type of memory testing method, it was necessary to observe all output signals appearing at the output terminals of the memory in order to discover defective memories. However, large-scale integrated circuits (
In the case of a memory circuit in an LSI (LSI), since the number of output terminals of the LSI is limited, the output of the memory circuit is often outputted to the outside as is. Therefore, we adopted a scan canvas test circuit that takes the output of the memory circuit into a register in parallel, converts it from parallel to serial, and outputs it serially.Based on the serial output that appears at one output terminal, we use a scan canvas test circuit that outputs the memory contents to the memory circuit. will test the functionality of.

[Problems to be Solved by the Invention] In the conventional memory test circuits described above, all or some of the memory output terminals are observed, but redundant circuits such as scan test circuits and scan tests are required. There is a problem in that a control signal for controlling the circuit (for example, a signal for taking the memory output into the scan test circuit in parallel, a clock signal for serially reading out from the scan test circuit, etc.) is required.

[Differences between the present invention and the prior art] The present invention differs from the conventional memory test circuit described above in that the circuit configuration is simple and no control signal is required.

[Means for Solving the Problems] The gist of the present invention is to provide a test circuit for testing the functions of a memory circuit having a plurality of output nodes, including a plurality of transistors whose gates are respectively connected to the plurality of nodes; A constant current source that supplies current to the plurality of transistors is provided, and the current driving ability of the plurality of transistors is given a certain weight.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. 1 is a memory circuit, 2 to 5 are MO9 field effect transistors,
6 is a resistor, 7 is a DC power supply, and 8 to 11 are outputs of the memory circuit. Is the current drive capacity of MOS field effect transistors 2 to 5 unit type? The transistor size is determined so that mI is raised to the power of 2. That is, Mo, sz
If the current drive capacity of the field effect transistor 2 is ■, then M
The current driving capacity of the OS field effect transistor 3 is 2■, M
The current driving capacity of the OS field effect transistor 4 is 4■, M
The current driving capability of the OS field effect transistor 5 is 8■. Therefore, if the output logic of the memory circuit 1 differs, the value of the current flowing from the DC power supply 7 to the resistor 6 will appear different.

For example, all MOS field effect transistors 2 to 5 are n
If it is a channel type, the output 8 of the memory circuit 1 is at the logic "1" level, the output 9 is at the logic "0" level, and the output 1
If 0 is a logic "1" level and the output 11 is a logic "0" level, the current flowing through the resistor 6 will be five. In this way, the logic of the four-tree logic of outputs 8 to 11 of memory circuit 1 is
It can be observed by measuring the current flowing through one resistor 6.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. 1st
Compared to the embodiment, p-channel type MOS field effect transistors are used for the MOS field effect transistors 12 to 15. The operation is similar to that described in the first embodiment if the logic of outputs 8 to 11 of the memory circuit is replaced with "0" level and "1" level.

Effects of the Invention As explained above, the present invention makes it possible to observe the logic level alignment of multiple outputs of a memory circuit by measuring the current of a single resistor, and is particularly useful for semiconductor integrated circuits. When applied to memory circuit testing, it is effective in eliminating the need for extra terminals.

1... Memory circuit, ...n-channel type MO5 electric field effect transistor, DC power supply, memory output terminal, resistance, p-channel MO5 electric field effect transistor.

2～5 ・ ・ ・ ・ 7 ・ ・ ・ ・ ・ ・ ・ ・ ・ 8～11 ・
・ ・ ・ ・ ・ 6 ・ ・ ・ ・ ・ ・ ・ ・ ・12～15
・ ・ ・ ・ ・

Claims (1)

[Claims] A test circuit for testing the function of a memory circuit having a plurality of output nodes, comprising a plurality of transistors whose gates are respectively connected to the plurality of nodes, and a constant current source that supplies current to the plurality of transistors, A memory test circuit characterized in that the current drive capabilities of the plurality of transistors are given a certain weight.