JPH02153543A - Flexible printed board - Google Patents
Flexible printed boardInfo
- Publication number
- JPH02153543A JPH02153543A JP63308205A JP30820588A JPH02153543A JP H02153543 A JPH02153543 A JP H02153543A JP 63308205 A JP63308205 A JP 63308205A JP 30820588 A JP30820588 A JP 30820588A JP H02153543 A JPH02153543 A JP H02153543A
- Authority
- JP
- Japan
- Prior art keywords
- film
- flexible printed
- element chip
- integrated circuit
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920001721 polyimide Polymers 0.000 claims abstract description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000005452 bending Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 239000012778 molding material Substances 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フレキシブルプリント基板に関し、特に折り
曲げ性に富むポリイミドフィルムをベースにしたフレキ
シブルプリント基板の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flexible printed circuit board, and particularly to the structure of a flexible printed circuit board based on a polyimide film having excellent bendability.
従来、この種のフレキシブルプリント基板は、ベース基
板としてポリイミドフィルム、ガラエポ板が使用されて
おり、これらのベース基板と銅箔は接着材で貼り合わさ
れ、所定の回路パターンに銅箔を加工し使用される。Conventionally, this type of flexible printed circuit board uses a polyimide film or glass epoxy board as the base board, and these base boards and copper foil are bonded together with an adhesive, and the copper foil is processed into a predetermined circuit pattern. Ru.
上述したポリイミドフィルムをベース基板として用いた
フレキシブルプリント基板は、ポリイミドフィルム自体
に吸水性があるので、集積回路素子チップ搭載には、信
顆性上の問題がある。In the flexible printed circuit board using the above-mentioned polyimide film as a base substrate, since the polyimide film itself has water absorbency, there is a problem in reliability when mounting an integrated circuit element chip thereon.
方、ガラエポ板をベース基板として用いた場合は、集積
回路素子チップ搭載する上での信頼性は確保されるが、
ガラエポ板が折り曲げ性に乏しいという別の欠点がある
。On the other hand, when a glass epoxy board is used as a base substrate, reliability is ensured when mounting an integrated circuit element chip, but
Another disadvantage of glass epoxy boards is that they have poor bendability.
本発明のフレキシブルプリント基板は、ベース基板とし
てのポリイミドフィルムと、折り曲げ部分を除き少なく
とも部品実装部分に成膜された無機膜と、所定のパター
ンに加工された導体膜とを有している。無機膜及び導体
膜は、接着材を用いずポリイミドフィルム上に、真空蒸
着、スパッタあるいはＣＶＤにより直接成膜される。The flexible printed circuit board of the present invention includes a polyimide film as a base substrate, an inorganic film formed on at least the component mounting part except for the bent part, and a conductive film processed into a predetermined pattern. The inorganic film and the conductive film are directly formed on the polyimide film by vacuum evaporation, sputtering, or CVD without using an adhesive.
上記した本発明のフレキシブルプリント基板の無機膜は
、ポリイミドフィルムに吸着した水が実装される部品（
例えば、集積回路素子チップ）に影響を与えないように
阻止層の作用を有ししかも、この無機膜は折り曲げ部分
を避けて形成されているので折り曲げ性も確保される。The above-mentioned inorganic film of the flexible printed circuit board of the present invention is a component (
For example, the inorganic film has the function of a blocking layer so as not to affect the integrated circuit element chip), and since the inorganic film is formed avoiding the bending portion, bendability is also ensured.
又、上述したように、本発明のフレキシブルプリント基
板は、接着材を用いず薄膜形成技術を用いて無機膜及び
導体膜を形成しているので、部品実装性に富む効果も合
わせて持っている。Furthermore, as mentioned above, the flexible printed circuit board of the present invention has an inorganic film and a conductive film formed using a thin film formation technique without using an adhesive, so it also has the effect of improving component mounting performance. .
次に、本発明について、実施例を用い説明する。第１図
は、本発明の第１の実施例のフレキシブルプリント基板
に集積回路素子チップを実装した模式断面図である。厚
さ３５μｍのポリイミドフィルム１上に選択的に５ｉ０
２膜２（厚さ１μｍ）をスパッタ法で成膜する。本実施
例では、図中Ａ−Ａを折り曲げるため、ＳｉＯ２が幅１
ｍｍ取り除かれている。次に、銅膜３を真空蒸着法で
１μｍ厚に形成し、フォトリソグラフィ法で所定のパタ
ーンに加工する。パターン形成後、ニッケル・金を銅膜
上に電解メツキする。集積回路素子チップ４をダイボン
ディングし、この集積回路素子チップ４とフレキシブル
プリント基板の各々の端子パッドを金ワイヤ−５でワイ
ヤーボンディングし、最後にモールド材としてエポキシ
樹脂６を用いモールドする。Next, the present invention will be explained using examples. FIG. 1 is a schematic cross-sectional view of an integrated circuit element chip mounted on a flexible printed circuit board according to a first embodiment of the present invention. 5i0 selectively on polyimide film 1 with a thickness of 35 μm
2. A film 2 (thickness: 1 μm) is formed by sputtering. In this example, in order to bend A-A in the figure, SiO2 has a width of 1
mm has been removed. Next, a copper film 3 is formed to a thickness of 1 μm by vacuum evaporation, and processed into a predetermined pattern by photolithography. After pattern formation, nickel and gold are electrolytically plated on the copper film. The integrated circuit element chip 4 is die-bonded, the integrated circuit element chip 4 and each terminal pad of the flexible printed circuit board are wire-bonded with gold wires 5, and finally molded using an epoxy resin 6 as a molding material.
第２図は、本発明の第２の実施例の模式断面図である。FIG. 2 is a schematic sectional view of a second embodiment of the invention.
この実施例は、両面配線パターンの例で、スルーホール
７の部分は、両面の接続を確実に行なうため、５ｉ０２
膜２がスルーホール径に対し−廻り大きな径で除かれて
いる。この実施例では、折り曲げ部Ａ−Ａを除き、ベー
ス基板の両面にＳｉＯ２が成膜されており、より高い信
頼性が得られる利点がある。This example is an example of a double-sided wiring pattern, and the through hole 7 is made of 5i02 to ensure connection on both sides.
The membrane 2 is removed with a diameter approximately larger than the diameter of the through hole. In this embodiment, SiO2 is deposited on both sides of the base substrate except for the bent portion A-A, which has the advantage of providing higher reliability.
上記実施例で用いた５ｉ０２膜は、−例にすぎず、例え
ばプラズマＣＶＤ法で形成される５ｉＮＸを用いてもよ
いことは、言うまでもない又、導体膜として銅膜を実施
例では用いたが、他の金属例えば金を用いてもよいこと
は言うまでもない。又、実施例で用いた数値（ポリイミ
ドフィルム膜厚ＳｉＯ□膜厚等）は、−例でありこの値
に限るものではない。The 5i02 film used in the above example is just an example, and it goes without saying that 5iNX formed by plasma CVD, for example, may also be used.Also, although a copper film was used as the conductor film in the example, It goes without saying that other metals such as gold may also be used. Further, the numerical values (polyimide film thickness, SiO□ film thickness, etc.) used in the examples are examples and are not limited to these values.
以上、説明したように本発明によれば、ベース基板に折
り曲げ性のよいポリイミドフィルムを用い、部品実装部
に無機膜を設けることにより耐湿性にも優れ、高信頼性
が要求される集積回路素子チップ実装にも適するフレキ
シブルプリント基板が得られる。As explained above, according to the present invention, a polyimide film with good bendability is used for the base substrate, and an inorganic film is provided on the component mounting area, so that the integrated circuit element has excellent moisture resistance and is required to have high reliability. A flexible printed circuit board suitable for chip mounting can be obtained.
・・・スルーホール。...Through hole.
Claims (1)
も部品実装部分に無機膜を設け、さらに所定のパターン
に加工された導体膜を設けたことを特徴とするフレキシ
ブルプリント基板。1. A flexible printed circuit board, characterized in that an inorganic film is provided on a polyimide film at least at a part where components are mounted, excluding the bent part, and a conductive film processed into a predetermined pattern is further provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308205A JPH06101489B2 (en) | 1988-12-05 | 1988-12-05 | Flexible printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308205A JPH06101489B2 (en) | 1988-12-05 | 1988-12-05 | Flexible printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02153543A true JPH02153543A (en) | 1990-06-13 |
| JPH06101489B2 JPH06101489B2 (en) | 1994-12-12 |
Family
ID=17978181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63308205A Expired - Lifetime JPH06101489B2 (en) | 1988-12-05 | 1988-12-05 | Flexible printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101489B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952741A (en) * | 2014-03-27 | 2015-09-30 | 英特尔公司 | Electric circuit on flexible substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3195590B2 (en) | 1999-04-27 | 2001-08-06 | 日東電工株式会社 | Flexible wiring board |
-
1988
- 1988-12-05 JP JP63308205A patent/JPH06101489B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952741A (en) * | 2014-03-27 | 2015-09-30 | 英特尔公司 | Electric circuit on flexible substrate |
| JP2015192144A (en) * | 2014-03-27 | 2015-11-02 | インテル・コーポレーション | Electric circuit on flexible substrate |
| US9930793B2 (en) | 2014-03-27 | 2018-03-27 | Intel Corporation | Electric circuit on flexible substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06101489B2 (en) | 1994-12-12 |
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