JPH02152067A - Recording or reproducing device - Google Patents

Abstract

PURPOSE:To omit mechanical detecting mechanisms and to reduce the power consumption by interruptedly detecting the state of a disk loading completion detecting switch and performing initialization only at the time of replacing a disk. CONSTITUTION:A pulse signal which goes to the low level with the period of a frequency divider 17n is supplied to a disk loading completion detecting switch SW3 through a transistor Tr 22. When the switch 3 is switched from the turning-on or turning-off state to the turning-off or turning-on state because of loading or unloading of a disk, the output of an OR gate 35 goes to the high level for a prescribed time through an amplifier 25 and FFs 29a and 29b. Then, a Tr 124 is turned on, and a main power source 12 is turned on, and power is supplied to all circuits including a system control circuit 10. Next, an idle track of the disk D is detected. Meanwhile, when a main battery 121 is replaced, the state of an RS-FF 42 is checked, and an idle track is detected when its output terminal is in the high level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a recording or reproducing device, and more particularly to a record carrier exchange detection device for detecting that a record carrier has been exchanged.

(Prior Art) Various proposals have been made for devices that record information such as video and audio on a record carrier, but in recent years, for example, a record carrier called a video floppy has been used to BACKGROUND ART Electronic cameras that can sequentially record signals on a plurality of tracks and can be played back, printed out, transmitted, etc. immediately after recording, that is, photographing, are rapidly becoming popular.

In electronic cameras that sequentially record multiple pieces of information on multiple tracks on a record carrier, it is extremely important to use the recording tracks effectively, such as by preventing double recording on the same track on the record carrier. This is the condition.

That is, it is always necessary to accurately position the recording head in an unrecorded area on the record carrier prior to recording.

This type of double recording prevention mechanism detects the presence or absence of recording at the recording position on the record carrier before recording, and if the recording information already exists and has been recorded, the recording head is moved to the next recording area. There is a method in which the recording head is repeatedly moved to an unrecorded area and the recording head is finally positioned in an unrecorded area (for example, Japanese Patent Laid-Open No. 140515/1983).

In a recording or reproducing apparatus configured in this way, for example, by adopting a control sequence in which the recording head is moved to the next recording position at the end of recording in one recording area or at the time of the next recording operation, the current The position of the head on the record carrier itself is equivalent to memorizing the next recording position with respect to the record carrier. Therefore, the power must be turned off, or if the device is battery-powered, the battery must be removed for replacement or charging, or even the power supply voltage may drop below a predetermined threshold and become unusable. Even if the power is turned on or restored, recording will start from the current head position on the record carrier used for the previous recording, unless the recording head has been moved in the meantime. No double recording is performed, and no unrecorded portions, ie, empty tracks, are created unnecessarily.

However, according to this configuration, if the record carrier is replaced while the power is cut off in some way, the current position of the recording head becomes completely meaningless, and if recording continues, This causes problems such as double recording and empty tracks.

In order to deal with this situation, as described above, it is necessary to position the recording head with respect to the unrecorded portion on the recording medium every time the power is turned on. This means that every time the power is turned on, the unrecorded area is detected and the recording head is positioned, even though the record carrier has not been replaced.
This will greatly impair the performance of the device, and in battery-powered devices, it will accelerate the consumption of the power source battery.

Further, problems similar to those described above occur in devices that are configured to set various conditions for recording, such as switching the recording head to be used depending on the characteristics and type of the recording carrier.

In order to solve these problems, the present applicant has proposed a method of providing a mechanism for mechanically storing the replacement of the record carrier and repositioning the recording head according to the state of the storage mechanism. (Gan No. 60-22633).

In addition, we focused on detecting the insertion and removal of a record carrier by the opening and closing operation of the lid of the record carrier storage section of the device, and provided a switch that is closed during the opening operation of the lid, thereby detecting the replacement of the record carrier. A method to do this has also been proposed by the present applicant (Japanese Patent Application No. 61-288070).

(Problems to be Solved by the Invention) However, as described above, the record carrier exchange detection device that mechanically stores the exchange of record carriers requires a large number of parts, which is disadvantageous in terms of manufacturing costs. Furthermore, since a mechanism for mechanically resetting the memory is also required, the mechanical configuration becomes complicated, and the resetting operation requires a relatively long time.

In addition, the record carrier exchange detection device using a switch includes not only a switch for detecting opening of the lid, but also a switch for detecting insertion of a record carrier, a switch for detecting that the lid is closed, and a switch for detecting that the lid is closed. Many switches are required, including a switch to detect the write protection notch.
This method is disadvantageous in terms of space, and since the switch for detecting the opening of the lid has a complicated mechanism as described above, it has many problems, such as increasing costs.

(Means for Solving the Problems) The present invention has been made for the purpose of solving the above-mentioned problems, and is characterized in that in a recording or reproducing apparatus in which the record carrier is replaceable, a switch means operated in connection with the loading or unloading of the switch means, a detection means for intermittently detecting the state of the switch means, a storage means for storing the detection result of the detection means, and an initial state for the record carrier. A recording or reproducing apparatus comprising an initial setting means for making settings, and a control means for controlling the operation of the initial setting means based on the stored contents of the storage means when power is supplied to the apparatus, As a result, the initial setting operation is performed only when the record carrier is replaced, regardless of whether the power is turned on or off, providing a device that consumes low power, has excellent quick shooting performance, and does not require a complicated mechanical detection mechanism. It is something to do.

(Embodiments) Hereinafter, embodiments of the recording or reproducing apparatus according to the present invention will be described in detail with reference to the respective figures.

FIG. 1 is a block diagram showing a case where the recording or reproducing apparatus according to the present invention is applied to an electronic camera.

In the same figure, ■ is the optical system including the photographic lens, and C is the optical system including the photographic lens.
It consists of an image sensor such as an OD, an aperture, a shutter, etc.
A camera section 2 converts the photographed image information into an electrical signal and outputs it, converts the electrical signal output from the camera section into a video signal, performs FM modulation, etc., and records it on a magnetic disk D as a recording record carrier. 3 is a disk rotation motor that rotates the magnetic disk D at a predetermined speed; 4 is a motor servo circuit for controlling the rotation of the motor 3; 5 is a magnetic disk. D
a recording/reproducing head 6 for recording the output signal of the recording signal processing circuit 2 or reproducing the recorded information signal on the magnetic disk D;
7 is a head feeding mechanism that drives a head feeding motor to move the head 5 in the radial direction of the magnetic disk D and controls the head position to select a track; 7 is an RF multiplied signal reproduced from the magnetic disk D by the magnetic head 5; An envelope detection circuit performs envelope detection and supplies the level to a system control circuit to be described later, and 8 is an A/R converting the output signal of the envelope detection circuit 7 into a digital signal.
D converter; 9 is a switch for switching and connecting the above-mentioned recording signal processing circuit 2 and envelope detection circuit 7 to the magnetic head 5; 10 is a system control circuit for controlling each of the above-mentioned circuits and switches according to the mode; 11 12 is a main power supply circuit, which includes a battery 121, a voltage control transistor 122, a regulator 123, an Nch-transistor 124 for controlling the transistor 122, It is composed of a transistor 125 that maintains the ON state of the transistor 124 based on a control signal from the system control circuit 11.

Reference numeral 13 denotes a disk attachment/detachment detection circuit for detecting attachment/detachment of the recording carrier, that is, the magnetic disk D, which constitutes the main part of the present invention, and the detailed internal configuration will be described later.

14 is an auxiliary battery that supplies power to the disk attachment/removal detection circuit 13 and other necessary parts;
4, the range to which power can be supplied is shown by a dashed line in the figure.

SW3 is turned on when a disc is inserted into a disc loading disc holder (not shown), closed to the device, and loaded at a predetermined recording or playback position.
The loading completion detection switch SW4, designated as N, is a mode selection switch of the electronic camera system in this embodiment, and when turned on, supplies power to the system and puts it in a recordable state. This allows the user to recognize whether the display section 11, such as a liquid crystal display, is turned ON, released from the LOCK state, or the like.

SWI and SW2 are switches that are sequentially closed by pressing the first and second stages of a two-stage suppression type release button (not shown), and the power supply to the system is turned on by opening these switches. . Reference numeral 15 corrects the difference in operating voltage levels between the disk attachment/removal detection circuit 13 and the system control circuit 10 to ensure accurate data exchange.

This is a level shift circuit to enable exchange.

Therefore, in order to record with this electronic camera, first the disk D is loaded into the device by means not shown, the power is turned on, and an initialization operation is performed.

That is, the head feeding mechanism is controlled by the system control circuit 10, and the head 5 is sequentially moved to all tracks on the disk. At the same time, the head 5 is connected to the RF envelope detection circuit 7 by the switch 9, and the reproduction RF
The presence or absence of recording on each track is checked based on the magnitude of the envelope level of the signal, and the recording head 5 is moved and positioned to an unrecorded area.

Next, by setting the recording mode while power is being supplied to each circuit, the switch 9 is connected to the recording signal processing circuit 2, and a release button (not shown) is operated to turn on the switches SWI and SW2. As a result, the image captured by the camera unit 1 is converted into an electric signal, which is subjected to predetermined processing by the signal processing circuit 2, and then supplied to the recording head 5 and recorded on the disk D rotated by the motor 3. Ru.

The operation algorithm for initializing the disk is shown in the flowchart of FIG. In addition, the disks used in this example are concentrically arranged from the outer circumference to the inner circumference by 50 mm.
Use something that can be recorded over the entire track.

In the figure, when the disk is replaced (step
l), the head 5 is moved to the innermost track of the disk (step 2), and the track table that is formed on the memory in the system control circuit 10 and stores information such as whether or not each track is recorded is cleared from all unrecorded tracks. It is cleared to "0" as shown (step 3). Then, the RF signal envelope level reproduced from the recording track where the head 5 is located is compared with a predetermined value to determine whether or not the track has been recorded (step 4). If the recording has not been completed, the process moves to 5tepH and it is determined whether the current track is the first track or not. If it is not the first track, proceed to 5teplO, move the head 5 one track to the outer circumferential side, return to 5tep4, move the head sequentially until the first track or a recorded track is reached, and determine whether recording has been completed. Repeat. If it becomes the first track at 5 tepH, this means that all the tracks have not been recorded, and the process advances to 5 tep 9 to display the current track position and complete the initialization.

If it is determined in step 5 that the track has been recorded, the process advances to step 5 and indicates that the track has been recorded at the address corresponding to the current track on the track table.
" is stored. Next, in 5tep6, it is determined whether the current track is the 50th track or not. If it is not the 50th track, the process moves to 5tep8, the head 5 is sent one track toward the inner circumference, and the current track is stored in 5tep9. Displays the head position and finishes initialization.

If it is the 50th track at 5tep6, all the tracks have been recorded, so the process proceeds to 5tep7, where it is displayed that all the tracks have been recorded and the initialization ends.

As described above, at the time when initialization is completed, the head 5 is located at the unrecorded track to be recorded next, except when all tracks have been recorded.

Next, the disk attachment/detachment detection circuit 13 which is the most characteristic feature of the present invention
The specific configuration and operation of will be explained.

In FIG. 1, 16 is a reference clock oscillator that oscillates a predetermined clock frequency; 17. ．． 17□,...
, 17. consists of n D-flip-flops connected in series with a frequency divider that divides the clock frequency of the clock oscillator 16 to a predetermined frequency, for example, several Hz.

The D-flip-flops 18a and 18b use the reference clock output from the reference clock oscillator 16 to divide the D-flip-flop frequency divider 17. The input value is latched until the next reference clock is applied. Then, the output of the D-flip-flop 18b is the Q output of the D-flip-flop 18a, which is further converted to 1 of the reference clock.
With a period delay, the NAND gate 19 outputs the Q output of the D-flip-flop 18a and the Q output of the D-flip-flop 18b.
and the D-flip-flop 17. Detects the rising edge of . The output signal of the NAND gate 19 is then delayed by a delay element 20 for a predetermined period of time, and then sent to an OR gate 21.
is applied to the Nch-transistor 22 through the Nch-transistor 22 to turn it on. The output of the transistor 22 is connected to the loading completion detection switch SW3. Mode selection switch SW
4 are connected to one end side of each switch SW3. S
The other end of W4 is connected to the power supply by the auxiliary battery 14 through pull-up resistors 23 and 24, respectively, and pulled up to the H level, and has hysteresis in the input/output characteristics to prevent chattering etc. when switching the switch. It is connected to buffer amplifiers 25 and 26. The outputs of the buffer amplifiers 25 and 26 are output to the level shift circuit 15 via buffers 27 and 28, which serve as output ports, and are supplied to the system control circuit 10 after being converted to a predetermined level. Further, the buffers 27 and 28 as output ports have their control terminals 27a,
When the control terminals 28a and 28a are at the L level, the input signals are passed through as they are, and when the control terminals are at the H level, the output is cut off and the output is in a high-dance state. The operation is controlled by the control signal provided.

On the other hand, the output of the amplifier 25 is supplied to D-flip-flops 29a and 29b connected in series, and is latched at the timing of the output of the NAND gate 19. The Q outputs of the D-flip-flops 29a and 29b are then supplied to the EX-OR gate 31. The output of the amplifier 26 is also supplied to D-flip-flops 30a and 30b connected in series, and is latched at the timing of the output of the NAND gate 19. and D-flip-flop 30a, 3
The Q output of 0b is provided to EX-OR gate 32. The output of EX-OR gate 1-31.32 is OR gate 3
The output of the OR gate 33 is supplied directly to the input gate of the OR gate 35 after being delayed for a predetermined time via the D-flip-flop 34. D-flip-flop 34 latches the output of OR gate 33 at the timing of NAND gate 19. In addition, the input gate of the OR gate 35 is connected to an inverter 44a on the power line side, which is the pull-up resistor side of the switch SWI, which is turned on when the release button (not shown) is pressed in the first step, and the switch SW2, which is turned on when the release button is pressed in the second step. , 44
When each switch is OFF, an L level signal is supplied, and when each switch is ON, an H level signal is supplied.

On the other hand, these switches SWI and SW2 are ON and OFF.
The control signals corresponding to the output port buffers 36, 37, . It is supplied to the system control circuit IO via the level shift circuit 15. The system control circuit 10 is a switch SWI
, SW2 can be recognized by controlling the output boat buffers 36 and 37.

Further, the output of the OR circuit 35 is supplied to a control Nch-) transistor 124 of the main power supply circuit 12.

Further, the output signal of the EX-OR gate 31 is supplied to the input gate of the OR circuit 41 along with the output of the power-up clear circuit 40, and the output of the OR gate 41 is supplied from the system control circuit 10 via the level shift circuit 15. It is connected to the set terminal of the RS flip-flop 42 which is reset by the reset signal, and its Q output terminal is connected to the level shift circuit 15 via the output buffer 43 which is controlled simultaneously with the buffers 27, 28, 36, and 37.
and the system control circuit 10.

The operation of the disk attachment/detachment detection circuit 13 according to the ON/OFF states of the loading completion detection switch SW3 and the mode selection switch SW4 will be described below with reference to the timing chart shown in FIG.

■ When the disk D is correctly loaded at the predetermined recording or playback position and the switch SW3 is kept in the ON state: The Q output of the D-flip-flop 17n as a frequency divider receives the reference clock of the reference clock oscillator 16. (Figure 2(a)
)) is divided to a predetermined frequency, for example, several Hz, and a pulse is output. This pulse signal is latched by the D-flip-flop 18a at the timing of the reference clock (FIG. 2(b)), and is then latched by the D-flip-flop 18a.
8b at the timing of the reference clock,
The rising edge is detected by the NAND gate 19 (FIG. 2(C)). The output of the NAND gate 19 is the delay element 2
0, the transistor 22 is turned on after a predetermined time delay;
OFF control is performed, and a pulse signal with inverted polarity is output (FIG. 2(d)).

When the switch SW3 is turned on, the output of the transistor 22 is removed from chattering etc. by the amplifier 25 (FIG. 2(e)) and then supplied to the D-flip-flop 29a and the buffer 27 as an output port. Ru.

The D-flip-flop 29a latches the output of the amplifier 25 using the output of the NAND gate 19 as a clock, and its output is always at a low level. D-flip flop 29
b uses the output of the NAND gate 19 as a clock to latch the Q output of the D-flip-flop 29a. Therefore, the inputs of EX-OR gate 31 are both at low level, and the output thereof is also at low level.

Furthermore, the circuit consisting of the amplifier 26, D-flip-flops 30a, and 30b% EX-OR gate 32 following the switch SW4 operates in exactly the same way, and if the switch SW4 is turned on, the output of the EX-OR gate 32 will also be at a low level. Therefore, the output of the OR gate 33 becomes low level. As a result, the output of the D-flip-flop 34 is also at a low level, and since the pull-up sides of the switches SWI and SW are at an H level on the power supply line, the outputs of the inverters 44a and 44b are at an L level. Therefore, all the inputs of the OR gate 35 are at L level, and the output thereof is also at L level.

■ Disk D is not loaded and the disk loading detection switch SW3 is OFF: Switch SW3 is OFF.
Since it is an FF, the output of the amplifier 25 remains at a low level, and the output of the D-flip-flop 29a is also held at a low level. Therefore, the conditions are the same as in the case (2) above, and the output of the EX-OR gate 31 is at a low level. The same applies to switch SW4, switch S
If W4 is OFF, the output of EX-OR gate 32 will be at a low level. Therefore, when the main power supply is OFF, the output of the OR gate 35 is at a low level.

From the above ■ and ■, switch SW3. As long as SW4 remains stable in the ON or OFF state, the EX-OR gate 31, 32 (7) output will be at a low level and the output of the OR gate 35 will be at a low level in any combination. Become. As a result, the control transistor 24 in the main power supply 12 is turned off, and the main power supply is maintained in the OFF state.

■ The disk is installed and removed, and switch SW3 is turned on.
- When operated like $OF F: switch SW3
is turned on, the output pulse of the transistor 22 is supplied to the amplifier 25 via the switch SW3,
The threads are fed to the D-flip-flop 29a. If the switch SW3 is turned ON and OFF here, the output of the transistor 22 is no longer supplied to the amplifier 25, so the output of the amplifier 25 becomes H after the switch SW3 is turned OFF.
It becomes a level state (Fig. 2(i)).

The input pulse of the D-flip-flop 29a is NAND
It is held for one cycle of the output pulse of gate 19, and the next NA
If the input of the D-flip-flop 29a is changing when the output pulse of the ND gate 19 is input, the output of the D-flip-flop 29a will also change according to the input. Therefore, the output of the D-flip-flop 29a is as shown in FIG.
), it changes in the next cycle after switch SW3 turns ON-10F (L level - H level)
. The output of the D-flip-flop 29a is applied to the D-flip-flop 29b, and therefore the output of the D-flip-flop 29b changes to H level in the next cycle of the output pulse of the NAND gate 19 (FIG. 2(k)). E
The output pulse of the X-OR gate 31 is at the H level only during one period during which the output pulses of the flip-flops 29a and 29b' are shifted (FIG. 2(1)). EX-OR
The output pulse of gate 31 is passed through OR gate 33 to D-
The flip-flop 34 further holds the H level for one period of the output pulse of the NAND gate 19 (see Fig. 2(m)).
)) Therefore, the output of OR gate 35 is NAND goo)19
It is at H level for two cycles.

When the output of the OR gate 35 becomes H level, the Nch-transistor 124 is turned on during the period in which the output of the OR gate 35 is at the H level, that is, for two cycles.

When the transistor 124 turns on, the transistor 122
is turned on, and the transistor 122. is turned on from the main battery 121. It is supplied to all circuits starting from the system control circuit 10 via the regulator 123. Then, according to a command from the system control circuit 10, the transistor 125 is turned on, and the transistor 122 is kept in the on state. Following this, an empty track detection operation on the disk D (initialization operation shown in FIG. 3) is performed.

■ The disk is installed and removed, and switch SW3 is turned OFF.
When operated like F-+ON: switch SW3
When the transistor 22 is turned off, the output of the transistor 22 is not supplied to the amplifier 25, and the input of the amplifier 25 is pulled up to the H level via the pull-up resistor 23, so that its output is also held at the H level. Therefore D-
The Q outputs of flip-flops 29a and 29b are both H.
level, and the output of the EX-OR gate 31 becomes L level.

At this point, disk D is loaded and switch SW3 is turned OFF.
When F-+ is turned on, the output pulse signal of the transistor 22, that is, the pulse signal that becomes L level at the frequency divider 17n period is supplied to the amplifier 25, and is output from the amplifier 25 (FIG. 2(n)). This signal is latched by the D-flip-flop 29a at the timing of the NAND gate 19, and the input pulse of the D-flip-flop 29a is held for one cycle of the output pulse of the NAND gate 19, and the next output of the NAND gate 19 is If the input of the D-flip-flop 29a changes when the pulse is input, the output of the D-flip-flop 29a also changes according to the input. Therefore, the output of the D-flip-flop 29a is as shown in FIG.
It changes in the next cycle after F-$ON (H level - sL level). The output of D-flip-flop 29a is applied to D-flip-flop 29b, so the output of D-flip-flop 29b is applied to NAND gate 1.
The output pulse of EX-OR game 1-31 changes to H level in the next period of the output pulse of 9 (Fig. 2 (p)).
Both - become H level only during one shifted period of the output pulses of the flip-flops 29a and 29b (Fig. 2 (q))
). The output pulse of EXOR gate 31 is OR gate 33
The output of the OR gate 35 is held at the H level for one period of the output pulse of the NAND gate 1-19 by the D-flip-flop 34 (FIG. 2(r)).
The ND gate 19 remains at H level for two cycles.

When the output of OR gate 35 becomes H level, Nch-)
The transistor 124 is turned on for two cycles. The subsequent operations are the same as those described in ①.

Also, as is clear from Fig. 1, the mode selector switch SW4 that controls ON/LOCK of the system is as follows.
Like the loading completion detection switch SW3, ON-〇FF, 0FF-n.

N can be detected and the system can be powered on.

This allows the system control circuit 10 to turn on the display section 11, such as a liquid crystal display, to notify the operator of various information such as cancellation of the LOCK state of deafness.

Incidentally, the R3-flip-flop 42 is turned on when the disk is attached or detached, and the switch SW7 is turned on or off or 0F.
F-ONt is set simultaneously when the EX-OR gate 31 outputs an H level control signal as described above.

This R3-flip-flop 42 is configured so that when the main power is turned on by the above-described operation, if the main battery 121 is unplugged or exhausted and is inoperable, the disk is attached or detached during that time and the switch SW3 is turned on.
, is for storing that the OFF operation has been performed.

The RS flip-flop 42 is set by the output of an H level signal from the EX-OR gate 31, and when the transistor 124 is turned on to supply main power as described above, it is assumed that the main battery 121 is loaded. In addition, if sufficient power can be supplied and power is supplied to the system control circuit 10, the system control circuits 1 and 0 are reset via the level shift circuit 15 after the power is turned on.

On the other hand, if the main battery 121 is removed or exhausted and power is not supplied to the system control circuit IO, the reset signal is not supplied, so the R3-flip-flop 42 outputs the EX-OR gate 31 to a high level.
The state set via the OR gate 41 when the level is reached is maintained.

Later, when the main battery 121 is attached and the power is turned on by the mode selection switch SW4, switches SWI, SW2, etc. linked to the release button, the system control circuit 10 is connected to the output boat buffer 43.
Check the state of R5-flip-flop 42,
If the Q output terminal is set to the H level, the track information at the previous initialization is unreliable, so an initialization operation such as empty track detection is performed, and then the flip-flop 42 is reset.

This way, even if a disk is inserted or removed while the main battery is removed or the power is exhausted and the disk is inoperable, the insertion and removal will be remembered and initialized the next time the power is turned on. You can always get accurate track information.

In addition, the power-up clear circuit 40 is connected to the auxiliary battery 1.
When the auxiliary battery 14 is removed and reinserted, set the R8-flip-flop 42 and memorize it. If the auxiliary battery 14 is removed, then switch SW4゜SWI, SW2, etc. to turn on the power. When the input is performed, empty track detection, that is, initialization operation is performed.

Also, when shooting, the release button (not shown) may be pressed.
When WI and SW2 are turned on, an H level signal is supplied to the manual gate of the 0R circuit 35, so the transistor 1
24 is ONt, main power is supplied to each part, but at this time the system control circuit 10
The state of the RS flip-flop 42 is detected through the RS flip-flop 42.

If the H level indicating that the disc is attached or removed is not set, initialization will not be performed, and if it is set, the initialization will be performed as described above, so unnecessary initialization will be performed and the timing of shooting will be affected. Don't delay.

In addition, in FIG. 1, the buffer 27.
28, 36, 37, and 43 are opened and closed by control signals supplied from the system control circuit 10 to the control terminals 27a, 28a, 36a, 37, and 43a through the level shift circuit 15, respectively, and are connected to each buffer as appropriate. You can read the state of the current circuit.

Further, the OR gate 21 is connected to the system control circuit 10.
is provided to turn on the transistor 22 independently of the NAND gate 19 when it is desired to control the output ports and read the states of the switches SW3 and SW4 in real time.

As described above, according to the present invention, when the loading completion detection switch SW3 is turned 0N-OFF and 0FF-ON due to the attachment and detachment of the disk, the initialization operation of the disk is performed at the same time as the power is turned on. You can get accurate track information by doing this.

Also, even if the main battery is removed, if a disk is inserted or removed, this will be memorized, and the next time the power is restored, the specified operation (SWI, SW2, SW4, etc.) will be performed. Initialization is performed when the

In other words, do not initialize every time the power is turned on and off, but only when the disk is replaced.
Also, switch SW3. Instead of using the method of constantly supplying current to the pull-up resistors 23, 24, etc. for the detection of SW4, the D-flip-flop 17. is used as a frequency divider. Since the sampling is performed at the output cycle, the equipment can be controlled based on accurate information at all times.
Power consumption can be significantly reduced.

Here, the presence or absence of attachment and detachment of the record carrier in the present invention is determined by SW3.
To give a specific example of the power consumption of a circuit detected by sampling SW4, if the clock oscillation frequency of the reference clock oscillator 16 is set to 32.768kHz, and the frequency divider 1
7. ．． 172,......17. frequency of 8
Hz, the period when the loading completion detection switch SW3 is ON is 125 m5 eC for one cycle of 8 Hz,
The current flowing from the pull-up resistor 23 when the switch SW3 is ONL is 30.5x 10-'/125. Ox 10-”=
0.00024, which can be reduced to about 1/4 OOO of the case where the current continues to flow. This means that if the pull-up current is about 300 μ8, the average current is about 0.
．． This means that the current consumption is 0.075 μA, which means that significant power saving can be achieved.

(Other Embodiments) According to the above embodiments, the disk exchange detection device is realized by hardware, but it may also be controlled using, for example, a CPU that constitutes a system control circuit.

The control algorithm when using the CPU will be explained below using the flowchart of FIG.

In the figure, a timer interrupt is applied to the control of the system control circuit 10 at step 520, and this control flow starts. Nch- in Figure 1 at 5tep21
) Drop the drain side of the transistor 22 to L level (earth), and turn on the loading completion detection switch S at 5tep22.
The ON/OFF state of W3 is detected via the output port buffer 27 and stored in variable A. Also, dropping the drain side of the transistor 22 to the L level at step 21 is as follows:
Since the switch SW3 is connected on one side to the train of the transistor 22 and on the other side to the power supply line via the pull-up resistor 23, the state of the switch SW3 can be determined by dropping the transistor 22 side to the ground level.・This is for the purpose of

Next, in 5tep23, transistor 2 of switch SW3
Set the 2nd side to H level, compare the contents of A with the contents of variable B that stored the previous value of A in step 24, and if the contents of both variables are equal and A=B, there is no change in the state of SW3 from the previous time. Since there is no initialization etc., 5 step 29
Then, the contents of variable B are updated to the current contents of A, this routine is ended, and the original control is returned.

If the contents of A are different from B in step 5 step 24, the process proceeds to step 5 step 25, where it is determined whether or not loading is complete, that is, the disk is loaded. If loading is completed, the process proceeds to step 5 step 26, where the system is powered on. is input, an empty track is detected in ST, EP27, and initialization is performed. When the initialization is completed, the system power is turned off at step 528, and the process advances to step 529, where the contents of variable B are updated to the current contents of A, and the routine of this flow ends.

Also, if the disk is not loaded at 5tep25, the 5tep 25
29, the contents of variable B are updated to the current contents of A, and the flow ends.

By performing the interrupt operation as described above at a predetermined cycle, it is possible to perform the same operation as the disk attachment/removal detection circuit shown in FIG.

The hardware shown in FIG. 1 can be simplified by controlling the operation in software by the CPU in this way.

Although the auxiliary battery 14 is provided separately from the main battery 121 according to the embodiment shown in FIG. 1, the auxiliary battery 14 is not necessarily required (for example, as shown in FIG. It is also possible to use it as an auxiliary power source via a regulator 126 with low power consumption.The other configurations are the same as in FIG.
Explanation will be omitted.

In this case as well, R3 is cleared by the power-up clear circuit 40.
- The point that the flip-flop 42 is set and supplies information regarding whether or not a disk is attached or detached to the system control circuit 10 is as described above.

Regarding turning on the power, as shown in FIG.
It is also possible to arrange a detection switch SW5 for detecting that the detection switch SW5 is closed, and to turn on the power to the system in response to the closure of this detection switch.

This detection switch connects the battery to the battery compartment 5.
When closing the lid 51 after loading the lid 51, the locking mechanism is clicked at the end of the closing operation of the locking piece 51a of the lid 51.
It is positioned and installed so that it is N.

Therefore, as soon as the lid is closed, the system can be powered on and initialized to detect empty tracks. Note that the specific control operations are as described above.

(Effects of the Invention) As described above, according to the present invention, by intermittently detecting the state of the disk loading completion detection switch, the open detection switch for the disk loading door can be detected unlike the conventional device. This can be omitted, and the power consumption can be significantly reduced to a substantially negligible level.

In addition, even if the battery is not installed or is exhausted and becomes inoperable, it can detect that a disk has been installed or removed, and if a disk has been installed or removed, this will be memorized. The next time the power is turned on,
Initialization is performed, and unnecessary initialization is prevented when the disk is not inserted or removed.This not only reduces power consumption, but also makes the disk management information extremely reliable (and prevents unnecessary operations. Since there is no camera, it is also excellent in quick shooting performance as an electronic camera.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the recording apparatus according to the present invention, FIG. 2 is a timing chart for explaining the operation of the apparatus according to the present invention, FIG. 3 is a flowchart for explaining the initialization operation, and FIG. 5 is a flowchart showing a second embodiment of the present invention, FIG. 5 is a circuit diagram of a main part of a third embodiment of the present invention, and FIG. 6 is an example of means for detecting battery loading of the present invention. FIG. 12... Main power supply circuit 121...
・・Main battery 13 ・・・Record carrier attachment/detachment detection circuit 14 ・・・
......Auxiliary battery 171-17n...
... Frequency divider (D-flip-flop) 27.28, 36, 37.43 ... Output port SWI ... Switch SW2 closed by the first stroke of the release button ...Switch SW3, which is closed by the second stroke of the release button...Disc loading completion detection switch

Claims (1)

[Claims] In a recording or reproducing apparatus in which a record carrier is replaceable, a switch means operated in connection with loading or unloading of a record carrier, a detection means for intermittently detecting the state of the switch means, and a detection result of the detection means an initial setting means for initializing the record carrier; and an initial setting means for controlling the operation of the initial setting means based on the stored contents of the storage means when power is supplied to the apparatus. A recording or reproducing device comprising a control means for controlling.