JPH02150063A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To miniaturize a memory region by forming a groove on a semiconductor substrate, insulating the side face and the bottom of the groove except the surface side of the substrate of the groove, and burying a conductor in the groove as a bit line. CONSTITUTION:A field oxide film 14 is formed on a substrate 2, and a buffer silicon oxide film is formed between a silicon nitride film 28 and the substrate 2. a photoresist pattern 30 for forming a bit line is formed on a memory region, and the film 28, the oxide film and the substrate 2 are etched. Then, after the pattern 30 is removed, the sidewall 32 of the silicon nitride film is formed, and with it as a mask a trench groove 4 is made. The groove 4 is thermally oxidized therein to form a silicon oxide film 6. Thereafter, the sidewall 32 is removed. Then, the groove 4 is buried with a polycrystalline silicon layer 8. In this case impurity is implanted to the layer 8 to reduce its resistance.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to semiconductor memory devices such as mask ROMs and EFROMs, and in particular, bit lines are formed parallel to each other on the surface side of a semiconductor substrate. are parallel to each other on the gate oxide.

The present invention also relates to a semiconductor memory device called a so-called flat cell, in which word lines are formed in a direction crossing the bit lines, and a channel is formed between adjacent bit lines under the word lines.

(Prior Art) A bit line in a flat cell is formed on the surface side of a semiconductor substrate, and constitutes a source and a drain. These bit lines, ie, sources and drains, are formed by introducing impurities into the substrate by ion implantation or diffusion.

Furthermore, in conventional flat cells, a field oxide film formed by selective oxidation is used for element isolation in the peripheral region.

The process for forming the bit line is a new process independent of the peripheral area.

(Problem to be solved by the invention) In the bit line formed by ion implantation method or diffusion method,
Lateral diffusion of impurities causes a short channel effect, making it difficult to miniaturize memory cells.

Therefore, one method for preventing the short channel effect is to increase the substrate concentration.

However, increasing the substrate concentration increases the junction capacitance, making high-speed operation difficult.

Another method for preventing the short channel effect is to reduce the junction depth. However, reducing the junction depth increases the diffusion resistance, that is, the resistance of the bit line, which also makes high-speed operation difficult.

Although the flat cell structure is a structure for miniaturizing the memory area, if element isolation using selective oxidation is used in the peripheral area, the peripheral area will not be miniaturized, and the effect of miniaturization on the entire memory device will be reduced. becomes less.

If the process for forming the bit line is a new process independent of the peripheral area, the number of processes will increase.

An object of the present invention is to prevent short channel effects by preventing lateral diffusion of impurities in bit lines in a semiconductor memory device having a flat cell structure.

(Means for Solving the Problems) In the flat cell semiconductor memory device of the present invention, a bit line is formed by forming a groove in a semiconductor substrate, and insulating the side and bottom surfaces of the groove except for the surface side of the substrate. A conductor is embedded inside.

Furthermore, in a preferred embodiment of the present invention, the trench formed in the semiconductor substrate is insulated to achieve device isolation, and the device isolation trench and the bit line trench in the memory area are formed in the same etching process. It has become a thing of the past.

(Function) In the bit line of the flat cell of the present invention, the substrate surface portion of the bit line is connected to the substrate so that current flows between adjacent bit lines, that is, between the source and the drain. Since the side and bottom surfaces of the line are insulated, even if the conductor buried in the bit line trench is a polycrystalline silicon layer with impurities added to lower its resistance, the bit line will not pass through the substrate. There is no impurity diffusion, and therefore no short channel effect occurs.

In a preferred embodiment, the device isolation process is performed in the same process as the bit line formation in the memory area.

(Example) FIG. 1 represents one embodiment.

In the figure, the left side is the memory area, and the right side is the peripheral area.

In the memory area, grooves 4 for bit lines are formed in the substrate 2 so as to extend in parallel to each other and in a direction perpendicular to the plane of the paper in the figure. The side and bottom surfaces of the groove 4 are covered with a silicon oxide film 6 except for the substrate surface portion, and a polycrystalline silicon layer 8 is buried inside the groove 4. The resistance of polycrystalline silicon layer 8 is reduced by introducing impurities.

A gate oxide film 10 is formed on the surface of the substrate 2.

Word lines 12 are formed on the gate oxide film 10 in parallel to each other in a direction perpendicular to the bit lines 8 (in the plane of the paper). The word line 12 is also made of a polycrystalline silicon layer whose resistance has been lowered by introducing impurities.

In the peripheral region, a MoS transistor is formed in an active region surrounded by a field oxide film 14. 16 is a source, 18 is a drain, and a gate electrode 20 is formed on the gate oxide film 10 on the surface of the substrate 2.

The gate electrode 20 is also made of a polycrystalline silicon layer whose resistance has been lowered by introducing impurities.

Reference numeral 22 designates, for example, a PSG film as an interlayer insulating film, in which a contact hole is formed and a metal wiring 24 is formed. 26 is a passivation film.

The manufacturing process of this example will be explained with reference to FIG.

(A) A field oxide film 14 for element isolation in the peripheral region is formed on a silicon substrate 2 by selective oxidation using a conventional method.
628 is a silicon nitride film (S1
3N4), and a buffer silicon oxide film is formed between the silicon nitride film 28 and the substrate 2.

(B) A photoresist pattern 30 for forming bit lines in the memory area is formed by photolithography.

Using this photoresist pattern 30 as a mask, the silicon nitride film 28, the buffer silicon oxide film, and the silicon substrate 2 are etched. At this time.

The etching depth of the substrate 2 is approximately 0.3 μm.

After removing the photoresist pattern 30, a sidewall 32 of silicon nitride film is formed.

To form the side fall 32, a silicon nitride film layer may be deposited and etched back.

Next, using the side fall 32 as a mask, the substrate 2 is etched by about 2 μm to form a trench groove 34.

The inside of the trench groove 34 is thermally oxidized to 2000 to 3000
A silicon oxide film 6 about the size of a human being is formed.

After that, the sidewall 32 is removed.

(C) Next, the trench groove 4 is filled with a polycrystalline silicon layer 8. At this time, impurities are introduced into the polycrystalline silicon 8 to lower its resistance.

Thereafter, the silicon nitride film 28 and the silicon oxide film thereunder are removed.

After that, the process is the same as the conventional method, and after forming a gate oxide film 10 in the memory area and peripheral area, and depositing a polycrystalline silicon layer to reduce resistance, the word line 12 and gate electrode 20 are formed by photolithography and etching. form. A source 16 and a drain 18 in the peripheral region are formed by ion implantation, ion implantation is performed in the memory region to control the threshold value according to the information to be stored, an interlayer insulating film 22 is deposited, and a contact hole is formed. After opening, a metal wiring 24 is formed, and a passivation film 26 is formed.

FIG. 3 represents another embodiment of the invention.

In the embodiment shown in FIG. 1, the peripheral region and the memory region and between the transistors in the peripheral region are separated by a field oxide film 14, whereas in the embodiment shown in FIG. 3, trench grooves 5 for element isolation are formed. The difference is that the side and bottom surfaces of the trench 5 are insulated with a silicon oxide film 6, and the inside of the trench 5 is filled with a polycrystalline silicon layer 8.

The trenches 5 for element isolation are formed by the same etching process as the trenches 4 for bit lines in the memory area.

The structure of the memory area in FIG. 3 and the structure of the MoS transistor in the peripheral area are the same as those in FIG. 1, so their explanation will be omitted.

Next, a method of manufacturing the embodiment shown in FIG. 3 will be explained with reference to FIG. 4.

(A) A silicon oxide film 40 serving as a buffer layer is formed on a silicon substrate 2, a silicon nitride film 42 is deposited thereon, and a silicon oxide film 44 is further deposited thereon by the CVD method.

A photoresist is applied on the silicon oxide film 44, and a photoresist pattern 46 is formed using a mask including patterns of bit lines and isolation regions.

(B) Using the photoresist pattern 46 as a mask, the silicon oxide film 44, silicon nitride film 42, silicon oxide film 40, and silicon substrate 2 are etched. The etching depth of the silicon substrate 2 is approximately 0.3 μm.

(C) After removing the photoresist pattern 46 and depositing a silicon nitride film on the entire surface, etching back is performed to form a side wall 32 of the silicon nitride film.

A photoresist is applied, a photoresist pattern covering the memory area and exposing the peripheral area is formed by photolithography, and the silicon nitride film is etched to remove the sidewall 32 in the peripheral area.

Using the silicon oxide film pattern 44 and the sidewall 32 as a mask, the silicon substrate 2 is etched to a depth of about 2 μm.

Thereafter, the silicon oxide film 44 is removed, and the trench groove 4.
5 is thermally oxidized to form a silicon oxide film of 2,000 to 3,000 layers.

After that, in the same manner as in the process shown in FIG. 2, the side fall 32 of the silicon nitride film is removed, the inside of the trench 4.5 is filled with a polycrystalline silicon layer doped with impurities, a gate oxide film is formed, and the word line and surrounding areas are filled. MOS transistors are formed in the region.

(Effects of the Invention) In the flat cell type semiconductor memory device of the present invention, a groove is formed in a semiconductor substrate, the side and bottom surfaces of the groove except for the surface side of the substrate are insulated, and a conductor is buried in the groove. Since it is a line, lateral diffusion from the bit line in the memory region is blocked by the insulating film on the trench sidewall, so there is no short channel effect, and the memory region can be miniaturized.

In addition, since no junction capacitance is formed between the buried bit line and the substrate, low capacitance and high-speed operation are possible.

Furthermore, by increasing the depth of the trench in the memory area, the resistance of the bit line can be lowered.
In this respect, high-speed operation is also possible.

Furthermore, if element isolation is achieved in the present invention by insulating the grooves formed in the semiconductor substrate, the element isolation grooves and the bit line grooves in the memory area can be formed in the same etching process. There is no need for a selective oxidation process for element isolation in regions, and the number of manufacturing steps is reduced.

Further, by using the element isolation method using trench grooves, it is possible to significantly miniaturize the peripheral region as well.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment, FIGS. 2(A) to 2(C) are sectional views showing the manufacturing process of the same embodiment, and FIG. 3 is a sectional view showing another embodiment. 4(A) to 4(C) are cross-sectional views showing the manufacturing process of the same embodiment. 2...Silicon substrate, 4...Bit line trench, 5...Isolation trench,
6... Silicon oxide film, 8... Polycrystalline silicon layer, 1o... Gate oxide film, 12...
...Word line.

Claims (2)

[Claims] (1) Bit lines are formed parallel to each other on the surface side of the semiconductor substrate, and word lines are formed on the surface of the semiconductor substrate on a gate oxide film parallel to each other and in a direction crossing the bit lines. In a semiconductor memory device in which a channel is formed below a word line between adjacent bit lines, a bit line is formed by forming a groove in a semiconductor substrate, and insulating the side and bottom surfaces of the groove except for the surface side of the substrate. A semiconductor memory device characterized by having a conductor embedded therein. (2) The groove formed in the semiconductor substrate is insulated to achieve element isolation, and the element isolation groove and the bit line groove in the memory area are formed in the same etching process. The semiconductor memory device described above.