JPH02150057A - Power semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the breakdown strength of a power device by isolating a substrate from a single crystalline semiconductor layer formed with the device by a dielectric. CONSTITUTION:A stepwise recess is formed on the surface of an N<+>-type silicon substrate 24 reduced in its resistance, and the surface of the substrate 24 is covered with a silicon oxide film 26 of a dielectric film except the partial region of the bottom of the stepwise recess. A low resistance layer 28 is formed to be patterned in the buried layer of a bipolar transistor in the bottom of the recess. An N<->-type single crystalline silicon layer 30 is formed on the layers 26 and 28. The layer 30 is formed with a groove arriving at the layer 26 for isolating an element, the wall face of the groove is covered with a silicon oxide film 32 of a dielectric layer, and a polycrystalline silicon layer 34 is buried in the groove. A DMOS transistor is formed as a power device in the region including the bottom of the recess of the substrate, and a CMOS and a bipolar transistor are formed on a region except the region including the bottom of the recess.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as IC) in which a power device and other MOS devices and bipolar devices are formed on one chip.

(Prior art) When a power transistor and, for example, a bipolar transistor are formed on the same chip, the power transistor requires a high breakdown voltage and therefore needs to be thick enough to have a depletion layer. .

For bipolar transistors in peripheral circuits, it is advantageous for the thickness up to the buried layer to be thin in order to reduce the saturation voltage between the collector and emitter.

FIG. 5 shows a conventional large current power IC. A step is provided on the surface of an N-type silicon substrate 2 whose resistance has been reduced by antimony doping, and a P-type epitaxial layer 4 is formed on the surface of the substrate.
After the surface is flattened so that it fills the bottom of the step, a P-type epitaxial layer 6 is formed.

A DMOS transistor is formed as a power device in a region where the substrate 2 and the epitaxial layer 6 are in contact with each other.
Epitaxial layers 4, 6. In the area where is formed,
A bipolar transistor (Bip) and a CMOS are formed. 8 is an embedded calendar. PN junction isolation is used to isolate the bipolar transistor, CMOS and the substrate 2, and to isolate each element.

In the power IC shown in FIG. 6, a step is provided on the surface of a P-type silicon substrate 10, an N0-type buried layer 12 is epitaxially grown at the bottom of the step, and the epitaxial R
12 and an N-type epitaxial layer 14 is formed on the substrate IO. A DMO 8 is formed as a power device in a region including the bottom of the step of the substrate, and a CMOS and a bipolar transistor are formed in a region other than the bottom. In this power IC as well, the substrate and each element and between each element are separated by a PN junction.

FIG. 7 shows another conventional power IC.

A first substrate 16 and a second substrate 18 are bonded to each other, dielectrically isolated for each element region by a silicon oxide film 20, and each element region has a DM as a power device.
In addition to O8, CMOS and bipolar transistors are formed. 22 is a polycrystalline silicon layer that fills the trench for dielectric isolation.

(Problems to be Solved by the Invention) Power ICs using PN junction separation as shown in FIGS. 5 and 6 have a limit to their high breakdown voltage. Additionally, a parasitic transistor effect occurs in the PN junction isolation region.

Power IC using dielectric isolation as shown in Figure 7
In this case, since the substrate thicknesses of the power device section and the device section of the peripheral circuit are equal, it is not possible to optimize the characteristics of the power device and the characteristics of other devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power semiconductor device that can increase the withstand voltage of a power device through dielectric isolation and can maintain both the power device and other devices in an optimal state.

(Means for Solving the Problems) In the present invention, a single crystal semiconductor layer of the same conductivity type as the substrate is formed on the surface of a low resistance semiconductor substrate having a step, and in a region including the bottom of the step, the substrate and the The semiconductor layer is electrically conductive and the substrate and the semiconductor layer are separated by a dielectric layer in a region other than the region including the bottom of the step, and in the semiconductor layer, a power device is formed in the region including the bottom of the step. MOS devices and/or bipolar devices are formed in regions other than the region including the bottom of the step.

In the present invention, a single-crystal semiconductor layer is formed on the surface of the dielectric substrate having a step, and a low resistance layer is formed at the bottom of the step, and in the semiconductor layer.

A power device is formed in a region including the bottom of the step, and a MOS device and/or is formed in a region other than the region including the bottom of the step.
Or a bipolar device is formed.

(Function) Since the substrate and the single crystal semiconductor layer on which the device is formed are separated by a dielectric, it is advantageous for high durability.

Since the power device is formed in an area including the bottom of the step on the substrate, it is possible to improve the breakdown voltage characteristics of the power device, while other devices are formed in an area other than the area including the bottom of the step on the substrate. Therefore, for example, the saturation voltage of a bipolar transistor can be lowered.

(Example) FIG. 1 represents one embodiment.

A step is formed on the surface of the N1 type silicon substrate 24 whose resistance has been lowered by doping with antimony, which is an N type impurity, and the substrate 24 except for a part of the bottom region of the step is formed.
Its surface is covered with a silicon oxide film 26, which is a dielectric film. A high melting point metal layer such as tungsten, molybdenum, titanium, etc. is formed and patterned as a low resistance layer 28 at the bottom of the step, and the low resistance layer 2 is formed in areas other than the bottom to serve as a buried layer for the bipolar transistor.
8 is formed and patterned.

An N-type single crystal silicon layer 30 is formed on the dielectric layer 26 and the low resistance W28. single crystal silicon rfj
A groove reaching the dielectric 7FF 26 is formed in 30 for element isolation, the wall surface of the groove is covered with a silicon oxide film 32 which is a dielectric layer, and a polycrystalline silicon layer 34 is embedded in the groove. ing.

A DMOS transistor is formed as a power device in a region including the bottom of the step of the substrate.

36 is a P-type well, 38 is an N0-type diffusion region, and 40 is P0.
A type diffusion region, 42 a gate oxide film, and 44 a gate electrode.

CMOS and bipolar transistors are formed in regions other than the region including the bottom of the step. In 6MO5, 46 is a P-type well, 48.50 is a source and drain formed by N9-type diffusion regions, and a gate electrode 54 is formed on the channel region via a gate oxide film 52 to form an N-channel MOS transistor. ing. 56
．． Reference numerals 58 denote sources and drains formed by P0 type diffusion regions, and a gate electrode 62 is formed on the channel region via a gate oxide film 60 to form a P channel MOS transistor.

In the bipolar transistor, 64 is an emitter made of an N4 type diffusion region, 66 is a base made of a P type diffusion region,
68 is a collector contact formed by an N" type diffusion region.

Note that in FIG. 1, illustrations of the glabella insulating film, metal wiring, passivation film, etc. are omitted.

In the DMO8, the thickness of the single crystal silicon layer 30 from the surface of the element region to the low resistance layer 28 is about 30 to 40 μm, and the thickness of the single crystal silicon layer 30 in the 0MO8 and bipolar transistor is about 10 μm.

In this embodiment, in the DMOS transistor, when a gate voltage is applied to the gate electrode 44, an enhancement mode N channel is formed in the channel region on the surface of the well 36, and the monocrystalline silicon layer 30, which is the drift region, is formed.
A depletion mode N channel is formed on the surface of the substrate 24 which is the drain, and electrons pass from the source 38 through the well 36, the single crystal silicon layer 30, and the low resistance layer 28.
flows to

Next, the manufacturing method of this embodiment will be explained with reference to FIGS. 2 and 3.

Steps are provided on the surface of the low-resistance silicon substrate 24 by a method such as etching, and the surface is covered with a silicon oxide film 2.
Cover with 6. A contact hole is formed in the silicon oxide film 26 at the bottom of the step, and then a low-resistance layer is formed using a layer of a high-melting point metal such as tungsten, titanium, or molybdenum, a silicide of such a high-melting point metal, or a multilayer film whose resistance has been lowered by doping with impurities. Form a crystalline silicon layer, etc. The low resistance layer is patterned by photolithography and etching so that it remains in the four parts of the step and in the bipolar transistor formation region.

For example, a reduced pressure C is applied on the silicon oxide film 26 and the low resistance layer 28.
A polycrystalline silicon layer 70 is deposited by the VD method and leveled so that the surface is flat. For example, the surface may be polished for leveling.

A silicon nitride film 72 is deposited to a thickness of approximately 800 nm on the polycrystalline silicon layer 70 by, for example, low pressure CVD. Furthermore, a silicon oxide film 7 is formed thereon by, for example, a low pressure CVD method.
4 to a thickness of about 1000. Silicon oxide film 7
4, a polyethylene glycol layer 76 is formed as a cooling medium, and an optical glass plate 78 is placed in contact with the surface thereof.

When the polyethylene glycol 76 is formed via the silicon oxide film 74 rather than directly on the silicon nitride film 72, the wettability becomes better and more uniform. However, it is possible to form the polyethylene glycol layer 76 without providing the silicon oxide film 74. Furthermore, although the optical glass plate 78 is provided to make the film thickness of the polyethylene glycol 176 uniform, the polyethylene glycol layer 76 can be formed without providing this as well.

Thereafter, a laser beam 80 of an argon ion laser is focused by a lens from above the optical glass plate 78 and irradiated onto the polycrystalline silicon 1570, and by scanning the laser beam 80, the melted portion 82 of the polycrystalline silicon layer 70 is moved. crystal growth.

After that, the optical glass plate 78 is removed, and the upper layer of the single crystal silicon layer 30, that is, the polyethylene glycol layer 7 is removed.
6. Remove silicon oxide film 74 and silicon nitride film 72.

As a result, as shown in FIG. 3, a single crystal silicon layer 30 forming a device is formed.

Dielectric isolation between elements is applied to the single crystal silicon layer 30 by a conventional method, and DMO8, 0MO8 and bipolar transistors are formed in each element region.

FIG. 4 represents another embodiment.

Compared to the embodiment shown in FIG. 1, a contact hole is not provided at the bottom of the step on the surface of the substrate 24, and an N
A 0 type diffusion layer 84 is formed at a depth reaching the low resistance layer 28 from the surface of the single crystal silicon layer 30. In addition, in the bipolar transistor, N+ type diffusion JF is applied from the surface of the single crystal silicon layer 30 to the low resistance layer 28 which is a buried layer.
The difference is that J86 is provided so that a contact electrode can be taken out on the surface.

In the embodiment of FIG. 4 as well, the single crystal silicon layer 30 forming the device can be formed by the same method as shown in FIGS. 2 and 3. However, no contact hole is provided at the bottom of the substrate step.

In the embodiment of FIG. 1 or FIG. 4, the device isolation between the CMOS and bipolar transistors may be PN junction isolation.

In the embodiment shown in FIG. 4, instead of the structure in which the dielectric layer 26 is provided on the substrate 24, for example, a structure in which the dielectric substrate itself is provided with steps may be used.

Further, although a DMOS transistor is shown as a power device in the embodiment, a power bipolar transistor can also be used.

(Effects of the Invention) In the present invention, since the power device and other devices are dielectrically isolated, the power device
It becomes possible to apply a high voltage such as 150V and to flow a large current.

Since the power device is formed in the single crystal semiconductor layer in the area including the bottom of the step of the substrate, the substrate thickness of the power device is increased and high breakdown voltage can be achieved, while other devices are formed in the area including the bottom of the step. Since the substrate is formed in a region other than the region including the region, the substrate thickness becomes thinner, and the saturation voltage can be lowered in, for example, an NPN)-transistor.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment, FIGS. 2 and 3 are sectional views showing the process of forming a single crystal semiconductor layer in the same embodiment, and FIG. 4 is a sectional view showing another embodiment. Figures 5 and 6
7 and 7 are cross-sectional views showing conventional power ICs, respectively. 24...Substrate, 26...Silicon oxide film, 28...Low resistance layer, 30...Single crystal silicon layer, 32... Silicon oxide film, 34
...Polycrystalline silicon layer.

Claims (2)

[Claims] (1) A single crystal semiconductor layer of the same conductivity type as the substrate is formed on a surface of a low-resistance semiconductor substrate with a step, and the substrate and the semiconductor layer are electrically connected in a region including the bottom of the step;
The substrate and the semiconductor layer are separated by a dielectric layer in a region other than the region including the bottom of the step, and in the semiconductor layer, a power device is formed in the region including the bottom of the step; A power semiconductor device in which a MOS device and/or a bipolar device is formed in a region other than that of the power semiconductor device. (2) A single crystal semiconductor layer is formed on the stepped surface of the dielectric substrate, a low resistance layer is formed at the bottom of the step, and a power device is formed in the semiconductor layer in a region including the bottom of the step. A power semiconductor device in which a MOS device and/or a bipolar device is formed in a region other than the region including the bottom of the step.