JPH02146442U - - Google Patents

Info

Publication number
JPH02146442U
JPH02146442U JP5675589U JP5675589U JPH02146442U JP H02146442 U JPH02146442 U JP H02146442U JP 5675589 U JP5675589 U JP 5675589U JP 5675589 U JP5675589 U JP 5675589U JP H02146442 U JPH02146442 U JP H02146442U
Authority
JP
Japan
Prior art keywords
chip
electrodes
divided
integrated circuit
adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5675589U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5675589U priority Critical patent/JPH02146442U/ja
Publication of JPH02146442U publication Critical patent/JPH02146442U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図はこの考案の一実施例であるグルーピン
グされた１つのグループにプロービングされた状
態を示す平面図、第２図は第１図のＩＣチツプに
他方のグループの電極をプロービングした平面図
、第３図は従来のＩＣチツプにプロービングした
状態を示す平面図である。 図において、１はＩＣチツプ、２は電極、２ａ
はグルーピングされた一方の電極、２ｂはグルー
ピングされた他方の電極、３はプローブ針、３ａ
は電極２ａ用のプローブ針、３ｂは電極２ｂ用の
プローブ針を示す。なお、図中、同一符号は同一
、又は相当部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体集積回路において、入出力を機能別に複
    数のグループに分け互いに異なるグループの電極
    が隣り合うようにＩＣチツプに配置したことを特
    徴とする半導体集積回路。
JP5675589U 1989-05-17 1989-05-17 Pending JPH02146442U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5675589U JPH02146442U (ja) 1989-05-17 1989-05-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5675589U JPH02146442U (ja) 1989-05-17 1989-05-17

Publications (1)

Publication Number Publication Date
JPH02146442U true JPH02146442U (ja) 1990-12-12

Family

ID=31580864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5675589U Pending JPH02146442U (ja) 1989-05-17 1989-05-17

Country Status (1)

Country Link
JP (1) JPH02146442U (ja)

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