JPH02146174A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the break proof quantity of data against a disturbance by setting the holding charge capacity of a memory cell arranged in the peripheral part of the memory cell group larger than the holding charge capacity of the other memory cell. CONSTITUTION:The memory cell, which is selected out of a three-transistor (TR) type dynamic memory cell group 101 arrange in a grating shape, in a range of, for example, 200 to 300mum from a side making contact with a peripheral circuit, which generates the disturbance, consists of a high break proof quantity cell 105, whose holding charge capacity is doubled compared with an ordinary memory cell. Thus, the probability of the memory cell having the highest data breaking probability is reduced, and the break proof quantity of the data can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to a dynamic type M
Regarding O9 storage device.

[Prior Art] Conventionally, this type of semiconductor memory device has been designed as shown in FIG.

FIG. 3(a) is a block diagram of a conventional semiconductor memory device, and FIG. 3(b) is a circuit diagram of a three-transistor type dynamic memory cell. A large number of memory cells are arranged in a grid to form the memory cell group 301. A row decoder 302 is arranged on the left side of the memory cell group 301, and a column selector 30 is arranged on the upper side.
Only one is selected by 3. Further, a read/write circuit 304 is arranged on the upper side and controls read/write data of the memory cells. The memory cell shown in FIG. 3(b) is composed of three N-type transistors: a write transistor 305, a read transistor 306, and an amplification transistor 307, and a data storage capacitor 308. When writing data to memory cells, write word line 3
09 is set to a high potential, the transistor 305 is turned on, and the d data on the write data line 310 is transferred to the cell content, 11308.
lead to.

Further, when reading data, the read word line 311 is set to a high potential, the transistor 306 is turned on, and whether the transistor 307 is on or off is determined from the read data line 312.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, since the memory cells are of a dynamic type, there is a drawback that the data stored in the memory cells is destroyed by disturbances.

FIG. 4 shows a cross-sectional view of a part of a memory cell and the mechanism of data destruction due to disturbance. In FIG. 4, 401 is a data storage capacitor, and 402 is a write transistor. Here, the disturbance is the fractional carrier 404 flowing through the substrate 403 (
In this case, electrons), and when the minority carriers 404 jump into the depletion layer of the drain 405 of the write transistor 402 while charges are accumulated in the capacitor 401, the capacitance t4
The accumulated charges of 01 will leak to the substrate and the stored data will be destroyed. Here, the fractional carriers 404 are mainly generated by switching of MOS transistors, so if the decoder, selector, read/write circuit, etc. around the memory cell operate, the fractional carriers 404 in the substrate 403
increases. And the fractional carrier 40 in the substrate 403
The amount of 4 decreases with distance from the source due to extinction due to recombination and outflow to the substrate contact. Therefore, the probability of data corruption in a memory cell is determined by the decoder and selector.

It is higher in the peripheral areas near read/write circuits, etc.

[Differences between the invention and the prior art] Compared to the above-mentioned conventional semiconductor memory device, the present invention increases the amount of accumulated charge in the peripheral rows of memory cells arranged in a lattice pattern to increase data destruction resistance against disturbances. There is a difference.

[Means for Solving the Problems] A semiconductor memory device of the present invention is a semiconductor memory device including a memory cell group in which a plurality of memory cells that dynamically retain data are arranged in a lattice pattern. It is characterized in that the storage charge capacity of the memory cells arranged at the periphery of the group is set to be larger than the storage charge capacity of other memory cells.

A preferred embodiment of the present invention is characterized in that the memory cell is composed of three MOS transistors and a charge storage capacitor. Further, in another preferred embodiment of the present invention, the memory cell is a high resistance load (MOS)
It is characterized by being composed of transistors.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. 101 is 1
A group of 3-transistor type dynamic memory cells arranged in a grid of 28×128, 102 is a row decoder, 103
1 is a column selector, and 104 is a read/write circuit. Reference numeral 105 denotes a memory cell (hereinafter referred to as a high-withstand cell) whose holding charge capacity is twice that of the normal memory cells constituting the memory cell group 101, and which generates disturbances in the memory cell group 101. 200 to 300 from the side touching the peripheral circuit
The memory cells within μm are constituted by high-withstand cells 105.

Incidentally, with the above configuration, the operation of the semiconductor memory device itself is no different from the conventional one.

FIG. 2 shows a memory cell circuit according to another embodiment of the present invention.

201 is an N-type MOS transistor, 202 is a high resistance load (several tens to hundreds of GΩ, 203 is a holding charge capacity for high withstand capacity, 2
04 is a data line, and 205 is a word line. In this embodiment, a high resistance load type cell is used as the memory cell. In this embodiment as well, the peripheral portion of a memory cell group in contact with the peripheral circuit, which is constructed by arranging a large number of memory cells, is constructed of the above-mentioned high resistance load type high withstand capacity cells to prevent data destruction due to external disturbances.

The high-resistance load type cell performs static data retention in the circuit, but since the high-resistance load is extremely large, ranging from tens to hundreds of GΩ, this is almost the same as dynamic data retention.

[Effects of the Invention] As explained above, the present invention allows the memory cells in the peripheral part (for example, within 200 to 300 μm from the peripheral part) that are in contact with the peripheral circuit of the memory cell group arranged in a lattice shape to be high-withstand cells. Therefore, the probability of a memory cell having the highest probability of data destruction can be lowered, and the reliability of the semiconductor memory device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a semiconductor memory cell according to another embodiment of the present invention, and FIG. 3(a) is a diagram of a conventional semiconductor memory device. FIG. 3(b) is a block diagram of the memory device, FIG. 3(b) is a block diagram of its memory cells, and FIG. 4 is an explanatory diagram of the mechanism of data destruction due to disturbance. 203 ◆ ・Holding capacity for high tolerance.

Claims (1)

[Claims] In a semiconductor memory device equipped with a memory cell group consisting of a plurality of memory cells that dynamically retain data arranged in a lattice pattern, the storage charge capacity of the memory cells arranged around the memory cell group is compared to that of other memory cells. A semiconductor memory device characterized in that the storage charge capacity is set to be larger than the storage charge capacity of a cell.