JPH0214581A - Semiconductor nonvolatile memory - Google Patents
Semiconductor nonvolatile memoryInfo
- Publication number
- JPH0214581A JPH0214581A JP63164756A JP16475688A JPH0214581A JP H0214581 A JPH0214581 A JP H0214581A JP 63164756 A JP63164756 A JP 63164756A JP 16475688 A JP16475688 A JP 16475688A JP H0214581 A JPH0214581 A JP H0214581A
- Authority
- JP
- Japan
- Prior art keywords
- eprom
- light emitting
- emitting diode
- bit
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 2
- 229910021431 alpha silicon carbide Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 239000007943 implant Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000002784 hot electron Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- LFYJSSARVMHQJB-QIXNEVBVSA-N bakuchiol Chemical compound CC(C)=CCC[C@@](C)(C=C)\C=C\C1=CC=C(O)C=C1 LFYJSSARVMHQJB-QIXNEVBVSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、電子計算機、通信（幾、ファクシミノなど
の電子機器に用いる半導体不揮発性メモリに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor non-volatile memory used in electronic devices such as computers, communications (machines), and facsimino machines.
［発明の概要］
この発明は、電気的に書込みを行うＥＦＲＯＭと、バン
ドギャップの高い化合物半導体あるいはアモルファス半
導体の発光ダイオードを各ビット毎に対応して配置し、
ＥＦＲＯＭの消去を発光ダイオードの電気信号によって
行う。[Summary of the Invention] This invention has an EFROM that performs electrical writing and a light emitting diode made of a compound semiconductor or an amorphous semiconductor with a high bandgap arranged corresponding to each bit.
Erasing the EFROM is performed using an electric signal from a light emitting diode.
［従来の技術］
従来は、書き込みはトンネル電流やホットエレクトロン
等を用いてフローティングゲートに電荷を注入し、消去
は、書込みと同様にトンネル電流を用いて、Ｅ’ＰＲＯ
Ｍを構成していた。第２図は従来のトンネル電流を用い
たＥ２ＰＲＯＭの断面図である。なお、１０１１１Ｐ型
シリコン基板、１１１はコントロールゲート、１１２は
フローティングゲート、１１３はドレイン、１１４はソ
ース、１１５はセレクトゲートである。[Prior art] Conventionally, for writing, charges are injected into the floating gate using tunnel current, hot electrons, etc., and for erasing, similar to writing, tunnel current is used to inject E'PRO.
It comprised M. FIG. 2 is a cross-sectional view of a conventional E2PROM using tunnel current. In addition, 10111P type silicon substrate, 111 is a control gate, 112 is a floating gate, 113 is a drain, 114 is a source, and 115 is a select gate.
（発明が解決しようとする課題）
従来のトンネル電流を用いた消去方法では、フローティ
ングゲートの下の薄い絶縁膜（５０〜１５０人）とシリ
コン基板上の高濃度拡散領域より構成されている。この
場合、セル面積が太きい、また、消去電極をフローティ
ングゲート上に設けたものでは、セル面積は小さくなる
がフローティングゲート上のトンネル絶縁膜の膜質が悪
く書替え回数は１００〜１０００回程度であった。(Problems to be Solved by the Invention) The conventional erase method using tunnel current consists of a thin insulating film (50 to 150 layers) under a floating gate and a high concentration diffusion region on a silicon substrate. In this case, if the cell area is large and the erase electrode is provided on the floating gate, the cell area will be small, but the quality of the tunnel insulating film on the floating gate will be poor and the number of rewrites will be around 100 to 1000 times. Ta.
ＥＰＲＯＭのフローティングゲート上に発光ダイオード
を設け、発光ダイオードの出力である、光エネルギー光
を用いて、フローティングゲート中の電子を励起し、絶
縁膜／ Ｓ ｉ障壁を越えて、基板上に放出することに
より、消去する。A light emitting diode is provided on the floating gate of the EPROM, and using the optical energy light output from the light emitting diode, electrons in the floating gate are excited and emitted onto the substrate beyond the insulating film/Si barrier. will be deleted.
フローティングゲート上に発光ダイオードを設けている
ので、セル面積は小さく、ホットエレクトロンによる劣
化が小さいので、書替＾回数は伸びる。Since the light emitting diode is provided on the floating gate, the cell area is small and deterioration due to hot electrons is small, so the number of rewrites is increased.
〔実施例］
第１図に本発明の実施図を示す、シリコン基板ｌ上にセ
ル面積の小さなＥＦＲＯＭＩＯを形成する。この上に、
層間絶ｎ１ｌ１２を堆積し、平坦化する。その後、バン
ドギャップがＳ １ ／ Ｓ Ｉ Ｏ＊の障壁３．２ｅ
Ｖより大きいＧａＮ、ＺｎＯ，Ｚｎ５、ａ−ＳｉＣ半導
体層を成長させる。この場合シリコン基板からのへテロ
エピタキシャル成長を用いてもよいし、ＣＶＤによるア
モルファス層を堆積しその後レーザーアニール等により
再結晶化させても良い、半導体膜の成長中にＰ／Ｎドー
ピングするかあるいは、成長後に、イオンインプラか不
純物拡散によりＰＮ接合を形成し、基板上に配置された
ＥＰＲＯＭアレイの各ビットに対応する様に発光ダイオ
ード２０をアレイ状に形成する。[Example] An EFROMIO having a small cell area is formed on a silicon substrate 1, as shown in FIG. 1, which shows an implementation diagram of the present invention. On top of this
Deposit interlayer n1l12 and planarize. After that, the barrier 3.2e with bandgap S 1 / S IO*
Grow GaN, ZnO, Zn5, a-SiC semiconductor layers larger than V. In this case, heteroepitaxial growth from a silicon substrate may be used, an amorphous layer may be deposited by CVD and then recrystallized by laser annealing, etc., P/N doping may be performed during the growth of the semiconductor film, or After the growth, a PN junction is formed by ion implantation or impurity diffusion, and light emitting diodes 20 are formed in an array so as to correspond to each bit of the EPROM array arranged on the substrate.
書き込みは、ＥＰＲＯＭアレイのＰを選択し、所定の畜
き込みバイアスを各電極に印加し、ホットエレクトロン
注入、トンネル注入等により、フローティングゲートに
注入する。For writing, select P in the EPROM array, apply a predetermined storage bias to each electrode, and inject into the floating gate by hot electron injection, tunnel injection, or the like.
消去は、発光ダイオードのアノード２１、カソード２２
間にｊｌｉ方向バイアスを印加し、発光させる。フロー
ティングゲート中の電子は、このエネルギーの高い（３
，２ｅＶ以上）のフォト２に励起され、Ｓ ｉ ／ Ｓ
ｉ Ｏ−障壁を越えて、放出される。Erasing is performed by the anode 21 and cathode 22 of the light emitting diode.
A bias in the jli direction is applied in between to emit light. The electrons in the floating gate have this high energy (3
, 2 eV or more), and S i / S
i O-is released across the barrier.
この書込み、消去は各ビット毎に行なわれ、しかも、モ
ールド等でパッケージングした後でもＩＣ内部でできる
。This writing and erasing is performed for each bit, and can be performed inside the IC even after packaging with a mold or the like.
〔発明の効果ｌ
ＥＰＲＯＭ上に消去用発光ダイオードを形成しているの
で、セル面積が小さ（、高集積可能である。また、光学
的に励起しているので、絶縁破壊はなく、高書替え回数
が実現できる。[Effects of the invention l Since the erase light emitting diode is formed on the EPROM, the cell area is small (and high integration is possible. Also, since it is optically excited, there is no dielectric breakdown and a high number of rewrites is possible. can be realized.
第１図は、本発明のＥ２ＦＲＯＭの断面図、第２図は従
来のＥＰＲＯＭ上
１、１０
１０ ・ ・
２０ ・ ・
１２、１
シリコン基板
ＰＲＯＭ
発光ダイオード
フローティングゲート
以
上
Ｕ
弔１図
従来のＥ２Ｐ ＲＯＭの箭面図
￥２図
°旧′ｌの表示
昭和６３年 特３′「願
究明の名称
第１６４７５６号
半導体不渾発性メモリ
補正をする考
１１件との関係 特許出願人
東京都江東区亀戸６丁目３１番１号
（２３２）セイニ１−電子工″Ｊ、株式・会社代表取締
役 原 、禮之助
人
■２７０
千葉県松戸市千駄堀１４９３
別紙
特許請求の範囲
シリコン基板上に形成されたＥＦＲＯＭアレ・イ上に層
間絶縁膜を介して、ＧａＮ、ＺｎＯ，ＺｎＳ、α−Ｓｉ
Ｃ等のバンドギャップの高い半導体層を成長し、前記半
導体層を用いて、前記ＥＰＲＯＭの各ビ・７トに対応す
る発光ダイオードを形成し、前記ＥＦＲＯＭの消去を前
記発光ダイオードを点滅させる電気信号によって各ピン
トごとに行うことを特徴とする」」１俸ＺすＬ光ｊシ（
至」−以上
出願人 セイコー電子工業株式会社Figure 1 is a cross-sectional view of the E2FROM of the present invention, and Figure 2 is a conventional EPROM. 1986 Special 3' Name of application No. 164756 Relation to 11 cases of consideration for correcting memory defects in semiconductors Patent applicant: 6 Kameido, Koto-ku, Tokyo Chome 31-1 (232) Seini 1-Electronic Engineering''J Co., Ltd. Representative Director Hara, Reinosuketo 270 1493 Sendabori, Matsudo City, Chiba Prefecture Attachment Claims EFROM array memory formed on a silicon substrate GaN, ZnO, ZnS, α-Si
A semiconductor layer with a high bandgap such as C is grown, and the semiconductor layer is used to form a light emitting diode corresponding to each bit 7 of the EPROM, and an electric signal that blinks the light emitting diode is used to erase the EFROM. It is characterized by the fact that it is performed for each focus by
Applicant: Seiko Electronics Co., Ltd.
Claims (1)
絶縁膜を介して、ＧａＮ、ＺｎＯ、ＺｎＳ、α−ＳｉＣ
等のバンドギャップの高い半導体層を成長し、前記半導
体層を用いて、前記ＥＰＲＯＭの各ビットに対応する発
光ダイオードを形成し、前記ＥＰＲＯＭの消去を前記発
光ダイオードを点滅させる電気信号によって各ビットご
とに行うことを特徴とするＥＥＰＲＯＭ。GaN, ZnO, ZnS, α-SiC are deposited on an EPROM array formed on a silicon substrate via an interlayer insulating film.
A light emitting diode corresponding to each bit of the EPROM is formed using the semiconductor layer with a high bandgap, and the erasing of the EPROM is performed for each bit by an electric signal that blinks the light emitting diode. EEPROM is characterized in that it performs the following functions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63164756A JPH0214581A (en) | 1988-06-30 | 1988-06-30 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63164756A JPH0214581A (en) | 1988-06-30 | 1988-06-30 | Semiconductor nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214581A true JPH0214581A (en) | 1990-01-18 |
Family
ID=15799326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63164756A Pending JPH0214581A (en) | 1988-06-30 | 1988-06-30 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214581A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556499B2 (en) * | 1996-12-20 | 2003-04-29 | Hitachi, Ltd. | Nonvolatile semiconductor memory and read method |
| JP2010098285A (en) * | 2008-10-14 | 2010-04-30 | Samsung Electro-Mechanics Co Ltd | Surface treatment method for group iii nitride semiconductor, group iii nitride semiconductor, manufacturing method thereof, and group iii nitride semiconductor structure |
-
1988
- 1988-06-30 JP JP63164756A patent/JPH0214581A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556499B2 (en) * | 1996-12-20 | 2003-04-29 | Hitachi, Ltd. | Nonvolatile semiconductor memory and read method |
| US6765840B2 (en) | 1996-12-20 | 2004-07-20 | Renesas Technology Corp. | Nonvolatile semiconductor memory and read method |
| JP2010098285A (en) * | 2008-10-14 | 2010-04-30 | Samsung Electro-Mechanics Co Ltd | Surface treatment method for group iii nitride semiconductor, group iii nitride semiconductor, manufacturing method thereof, and group iii nitride semiconductor structure |
| US8110424B2 (en) | 2008-10-14 | 2012-02-07 | Samsung Led Co., Ltd. | Surface treatment method of group III nitride semiconductor and manufacturing method of the group III nitride semiconductor |
| US8476639B2 (en) | 2008-10-14 | 2013-07-02 | Samsung Electronics Co., Ltd. | Group III nitride semiconductor and group III nitride semiconductor structure |
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