JPH0214495A - Read only memory - Google Patents

Abstract

PURPOSE:To attain high speed of readout by providing a memory cell comprising a transistor (TR) pair whose gate is connected to a word line and a bit line pair of 2 line one pair in common, giving a ground potential to one bit line and giving a power potential to other bit line and detecting a difference voltage to the bit line pair. CONSTITUTION:Gates of 1st and 2nd TRs Q1, Q2 constituting each memory cell are connected in common to a word line WL, the bit line is constituted by it line pair of 2 line one pair, the source S of the 1st TR Q1 is connected to a ground potential VSS and the source S of the TR Q2 is connected to a power potential VDD. Then one bit line potential descends from an intermediate potential VMID to ground potential VSS and other bit line potential VMID rises from the intermediate potential to the power potential VDD, a potential difference is caused to the bit line pair and the potential difference is detected by a difference sense amplifier 5. Thus, the bit line potential is increased/decreased from the middle of the ground potential and the readout time is reduced.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a read-only memory (hereinafter referred to as ROM), and in particular to a mask ROM, and aims to shorten the change time of the bit line potential in terms of circuitry. , the purpose of this is to provide an R, OM that enables faster read operations, and includes a pair of bit lines, the gates of which are commonly connected to a word line, and a ground potential is applied to one of the bit lines. The memory cell includes a memory cell including a transistor pair of a first transistor and a second transistor that applies a power supply potential to the other bit line, and a differential sense amplifier that detects a voltage difference between the bit line pair.

[Industrial application field]

The present invention relates to a ROM, and particularly to a mask ROM.

Mask ROM is a device in which data is programmed (written) during the wafer process.6 Normally, a mask pattern is created by the manufacturer based on program data specified by the user, and programming is performed using this mask pattern. There are mainly three types of ROM programming methods.

One is “1” or “0” depending on the presence or absence of memory cells and transistors.
The diffusion layer programming method that defines the
The third method is an ion implantation programming method in which programming is performed by changing the threshold voltage of a transistor, and the other is a contact hole programming method in which "1" and "0" are defined depending on the presence or absence of a contact hole. Since such a mask ROM has a high storage density, it is suitable for use as an image memory of an image processing device that requires high-speed reading of a large amount of data.

[Conventional technology]

First, FIG. 4 shows a schematic diagram of a general mask ROM.
In FIG. 4, X address data A. When 0 to A are input, -1 is stored in the address buffer 1n. X address data A. 0''in is decoded by the X decoder 2 and selects one specific word line WL in the memory cell matrix 3.

On the other hand, when the read enable signal φ is applied to the bit line in the memory cell matrix 3 at this time, the storage contents of the memory cell at the corresponding address are detected by the sense amplifier 4, and the read data D is detected. It is output as 0 to DIIn.

Next, FIG. 5 shows 1
An example of a transistor (NMO8PET) type memory cell is shown.

In FIG. 5, word line WL and bit line ■.

At each intersection with bl, there is a transistor QH which becomes a memory cell.
1, Q142 is placed. Each transistor Q81
' Q) The gates of 42 are commonly connected to the word line WL. The drain of one transistor QH1 is connected to the bit line. connected to and programmed to logic “0”,
The source is grounded to the ground potential ■s8. The drain of the other transistor Q142 is not connected and has logic “1”.
is programmed to.

Transistors Q and QP2 are precharge transistors, and an enable signal φ is input to their gates. Each bit line S0, ■1 is connected to a sense amplifier 4, and each transistor QH1
, QH□, and read the read data D.
, D2 are read.

Next, the operation will be explained.

When the read enable signal φ goes to "H" level, the power supply potential VD is applied to each bit line S0, ■l. At this time, if word IIWL is selected, that word line WL is activated and goes to "H" level. “It becomes a level. Then,
Transistor QH1 is turned on, and the power supply voltage V is absorbed by the ground potential vs8, so the output voltage of bit line ■ is at the "L" level, so the output data D1 is 0. Note that transistor QH□ is not yet activated. Since the bit line b1 is connected, the output voltage of the bit line b1 remains at the "H" level, and the output data D2 becomes "1".

In this way, during the data read time, the bit line potential is at the power supply potential ■. It is determined by the time it takes to fall from 0 to ground potential vS8.

[Problem to be solved by the invention]

As mentioned above, the data read time in the conventional mask ROM is as follows:
．． (for example, 5V) to the ground potential v, s (for example, 0.) corresponding to the "L" level. This time is ultimately caused by the performance of the memory cell transistor itself and the parasitic capacitance of the peripheral circuit, so it is difficult to fundamentally eliminate it. However, due to recent trends in the increase in the amount of information and demands for faster information processing, shortening the readout time still remains an issue to be solved.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a ROM in which the change time of the bit line potential can be shortened in terms of the circuit, thereby making it possible to speed up the read operation.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides two bit line pairs (b0, ■) and a gate (G) connected to a word line (WL).
) and a first transistor (Q1) that is commonly connected to
and a memory cell consisting of a transistor pair of a second transistor (Q2) that applies a power supply potential (V, , ) to the other bit line (b.), and detects multiple voltages on the bit line pair (b0, ■). A differential sense amplifier (5) is provided.

[Effect]

In the present invention, when the word line (WL) is selected, each of the bit line pairs (b0, ■) has the same potential (v
This potential (vHID), which is HIO), is the power supply voltage ■. , and ground potential V3. For example, if V=5V and V=Ov, it is about 2°5■.

If the word line (WL> is selected in this state, the first and second transistors (Q
, Q2) are both turned ON.

Then, the first transistor (Q1) applies a ground potential (v88) to one bit line (b), in other words, it absorbs the bit line potential (vH□,) and returns to the ground potential (v8).
8) Lower it. The starting potential of this voltage drop is the above-mentioned intermediate potential (vF4□,). transistor (Q2) connects the other bit line (b) to the power supply voltage (Vo
0), in other words, the bit line potential (VHID)
is raised to the power supply voltage (Vo, ). The starting potential of this voltage increase is the above-mentioned intermediate potential (vHI.).

In this way, one bit line potential is the intermediate potential (V s□
, ) to the ground potential (V, , ), and the other bit line potential (vHI0) falls from the same intermediate potential to the power supply voltage (VD0
) stand up. As a result, a potential difference occurs between the power supply voltage and the ground potential in the bit line pair. This potential difference is detected by the differential sense amplifier, and data of logic "0" is read from the sense amplifier.

In this way, the bit line potential does not rise and fall between the power supply voltage and the ground potential, but instead rises and falls from an intermediate potential, which shortens the read time accordingly. Become.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

An embodiment of the present invention is shown in FIG. 1, and the same or overlapping parts as in FIG. 5 are given the same reference numerals and will be described below.

In FIG. 1, each memory cell has a first transistor Q
and a second transistor Q2. The gates of the first and second transistors Q1rQ2 are commonly connected to the word line WL. The bit line consists of two bit line pairs, each with b
0, ■o0, ■l.

b, the drain D of the first transistor Q1 is the first
Bit line. °, source S is connected to ground potential V88
It is connected to the. Drain D of second transistor Q
is the second bit line. and the source S is connected to the power supply potential v
Connected to 00. In other words, the first transistor Q1
and the second transistor Q, opposite potentials are applied to the first bit line b and the second bit line B, respectively.

An equalizing transistor Q3 is connected between the transistor Q3 and the gate G of the equalizing transistor Q3, and a read enable signal φ is applied to its gate G. Also, the first cut line. is connected to the + side input terminal of the differential sense amplifier 5, and the second bit l
1■ is connected to one side input terminal of the differential sense amplifier 5.

Since each memory cell is constituted by the above-mentioned structural units, corresponding reference numerals are given to other memory cell portions, and explanations thereof will be omitted.

An example of a pattern when a mask ROM using the above memory cells is mounted on an IC with a master slice structure is shown in FIG. 3('a), and the corresponding equivalent circuit is shown in FIG. 3(b).
As shown in No. 37 (a), A in the vertical direction in the figure
j Perform multilayer wiring with the already-wired metal as the first layer and the horizontal direction as the second metal layer, and connect the first metal layer to the transistors Q and Q2 through the contacts indicated by O, and connect the first metal layer to the transistors Q and Q2 through the contacts indicated by . The layer and the second layer are connected to form the circuit shown in FIG.

Next, the operation will be explained (see FIG. 2).

First, in a state where neither the read enable signal φ nor the selection signal to the word line WL is applied, that is, before the memory cell is read, the potential relationship at the previous read is " For the H” level (v ■) and the second bit line ■, the “H” level (v
■).

do.

Now, at time t1, the enable signal φ(“H”L
Suppose you are given an L level. Then, the equalizing transistor Q3 is turned on, and the first bit line b and the second bit line are connected. is shorted.

Due to this short circuit, the first bit line is switched on at time t.

and second bit mb. Both power supply potentials are V. , (“H” level) and the ground potential v88 (“L” level), which is in a floating state at an intermediate potential vH4D. For example, VDD
= 5 V, Vss= OV, then v141D
=2.5v.

Next, when the word line WL is selected and activated (“H” level), both the first transistor Q1 and the second transistor Q2 are turned on. Then, the first transistor Q
1, the potential of the first bit line b is set to the intermediate potential
The power supply potential is raised from H1o to vDD. On the other hand, in the second transistor Q2, the potential v■ of the second bit line b
is lowered from the intermediate potential ■ to the ground potential Vs,
ID As a result, the first bit line. A differential voltage corresponding to the potential difference between the ground potential v88 and the power supply potential 700 is generated between the second bit line and the second bit line (2). This differential voltage is input to the differential sense amplifier 5, and the differential sense amplifier 5 receives data D of logic "0".
Outputs 1 to complete the read operation.

As described above, the first and second bit lines b□.

Changes in the potentials v■, v, and o of (voo or ■3.) becomes faster, which means that the read time is shortened, that is, the read operation is faster.

Note that according to the present invention, one memory cell is connected to two transistors Q1. Q2, and the number of transistors increases compared to the conventional one-transistor system. However, if the present invention is applied to a general-purpose IC, there will be some restrictions due to limitations on the transistors that can be used.
When applied to a custom IC such as tion 5 specific IC, there are unused transistors depending on the user's specifications, so it is possible to reuse them.
Furthermore, even if the number of transistors is increased, there is no disadvantage in separately providing the device, considering that the readout time can be significantly faster (approximately 10 ns) than in the conventional case.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the amount of change in the bit line potential during data reading, thereby enabling high-speed reading.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, FIG. 3(a) is a plan view showing an example of mounting on a master slice IC, and FIG. 3(b) is a corresponding diagram. Equivalent circuit diagram, Figure 4 is a schematic diagram of a conventional mask ROM, Figure 5 is a conventional mask FtOM.
FIG. 2 is a circuit diagram of a memory cell of FIG. Ql...first transistor Q2...second transistor ■0, ■l...first bit line ■0, ■i...second bit line WL...word line φ...read enable Signal vDO...Power supply potential ■ss...Ground potential Patent attorney Igata Sadamoto Operation explanation diagram of the invention 2M Outline diagram of conventional mask ROM Figure 4D+:", Sale take

Claims (1)

[Claims] A pair of bit lines (b_0, ■) and a gate (G) are commonly connected to a word line (WL), and one bit line (b_0) is connected to a ground potential (V_S_S). a memory cell consisting of a transistor pair of a first transistor (Q_1) to supply a power supply potential (V_D_D) to the other bit line (■) and a second transistor (Q_2) to supply a power supply potential (V_D_D) to the other bit line (■); A read-only memory characterized by comprising: a differential sense amplifier (5) that detects a differential voltage;