JP2008234808A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a stable read operation in a semiconductor device including a ROM. <P>SOLUTION: For example, respective memory cells (e.g. MCO) are composed of two NMOS transistors (MN40t, MN40b), a drain of the MN40t is connected to a bit line BLTm being as one complementary bit line, and a drain of the MN40b is connected to a bit line BLBm as the other complementary bit line. Then, a source of the MN40t is connected to a common source line CSm, and a source of the MN40b is connected to power source voltage VDD. For example, when MC0 is read out, the BLTm, and the BLBm are a pre-charged, a word line WL0 is activated, the common source line CSm is driven from a VDD level to a VSS level. as this operation, the BLTm is connected to the VSS, and the BBm is connected to the VDD, by differential-amplifying them, stable operation having large noise margin can be performed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique useful when applied to a semiconductor device including a small capacity ROM (Read Only Memory).

  For example, Patent Document 1 discloses a ROM in which each memory cell is configured by a pair of MOS transistors. The gates of both MOS transistors are connected to a common word line. The drain of one MOS transistor is connected to one of the complementary bit line pair, and the drain of the other MOS transistor is connected to the other of the bit line pair. In addition, the source of one MOS transistor is connected to the source line or opened (opened), and the source of the other MOS transistor is opened or connected to the source line. .

In this configuration, during the read operation, the source line is driven to the ground voltage level while the bit line pair is precharged to the power supply voltage level. In other standby modes, the source line is also driven to the power supply voltage level while the bit line pair is driven to the power supply voltage level. As a result, the subthreshold leakage current in the memory cell during standby can be reduced, and the power supply voltage of the ROM can be reduced. Further, since the MOS transistor is connected to each of the bit line pairs, the load is uniform during the read operation, and the read operation can be stabilized and speeded up.
International Publication No. 03/071553 Pamphlet

  2. Description of the Related Art In recent years, so-called system LSIs in which various functions such as a microcomputer and an SOC (System On a Chip) are mounted on a single chip have been used, for example, representatively of cellular phones. In such a system LSI, there is a case in which a ROM having a small capacity (for example, several K to several tens of K bits) that cannot be electrically rewritten is stored, for example, for storing a product ID number or the like. is there. This ROM is called a mask ROM or the like. As a storage method of the logical information, for example, whether or not one end of a MOS transistor in each memory cell is connected to a predetermined potential via a contact hole, A method of increasing or decreasing the concentration of the diffusion layer is widely known.

  FIG. 13 shows a schematic configuration example of a memory array in a ROM studied as a premise of the present invention, and (a) to (d) are circuit diagrams showing different configuration examples. The configuration example of FIG. 13A includes a memory cell MC composed of one MOS transistor at the intersection of a plurality of word lines WL0 to WLn and a bit line BL. For example, the memory cell MC0a located at the intersection of WL0 and BL stores, for example, “0” by connecting the source of the MOS transistor to the ground voltage VSS. Further, the memory cell MC1a located at the intersection of WL1 and BL stores, for example, “1” when the source of the MOS transistor is opened.

  The bit line BL is always set to the level of the power supply voltage VDD. For example, when MC0a is read, the voltage level of BL is lowered toward the 'L' level by the MOS transistor of MC0a by bringing WL0 into an active state ('H' level). This voltage level of BL is input to the inverter circuit INV via the Y switch YS, and INV performs an inverting operation when the potential level of BL reaches the logic threshold value and outputs read data.

  In the configuration example of FIG. 13B, compared to the configuration example of FIG. 13A, the source of the MOS transistor in the memory cell storing “1” is connected to the power supply voltage VDD, and the bit line The difference is that BL is precharged. That is, in FIG. 13A, for example, the source of the MOS transistor in the memory cell MC1a is in an open state, but in FIG. 13B, the source of the MOS transistor in the corresponding memory cell MC1b is the power supply voltage. Connected to VDD. In FIG. 13B, when the read operation is started, the precharge switch PSW is switched from the VSS side to the VDD side to place the bit line BL in the precharge state, and the charge of this BL is the memory cell to be accessed. A read operation is performed by detecting whether or not the battery is discharged through the MC by the inverter circuit INV.

  In the configuration example of FIG. 13C, compared to the configuration example of FIG. 13B, the source of the MOS transistor in the memory cell storing “1” is opened, and the inverter circuit INV Instead, a sense amplifier circuit SA serving as a differential amplifier is used. That is, in FIG. 13C, as in FIG. 13A, the source of the MOS transistor in the memory cell (for example, MC1c) storing “1” is opened. In FIG. 13C, in the same read operation as in FIG. 13B, the sense amplifier circuit SA differentially amplifies the potential level of the bit line BL based on the reference voltage Vref, and reads the result. Output as data.

  Here, in the configuration examples of FIGS. 13A and 13B, the transition time of the inverter circuit INV is slow, the through current increases, and the read operation may not be speeded up. On the other hand, in the configuration example of FIG. 13C, the read operation can be speeded up to some extent by using the sense amplifier circuit SA, but a stable read operation can be performed when noise is mixed in the bit line BL. There is no fear. Therefore, a configuration example as shown in FIG. This configuration example reflects the characteristics described in Patent Document 1.

  The configuration example of FIG. 13D includes two MOS transistors in one memory cell, and a read data is obtained by amplifying a signal read to the complementary bit line pair BLT and BLB by the sense amplifier circuit SA. It is the composition which obtains. For example, in the memory cell MC0d located at the intersection of the word line WL0 and the bit line pair BLT, BLB, the gates of two MOS transistors are commonly connected to WL0, the drain of one MOS transistor is connected to BLT, and the other MOS transistor Are connected to BLB. The source of the one MOS transistor is connected to the common source line CS, and the source of the other MOS transistor is in an open state.

  In the memory cell MC1d located at the intersection of the word line WL1 and BLT and BLB, the gates of the two MOS transistors are commonly connected to WL1, the drain of one MOS transistor is BLT, and the drain of the other MOS transistor is Connected to BLB. Contrary to the memory cell MC0d, the source of this one MOS transistor is opened, and the source of the other MOS transistor is connected to the common source line CS. For example, MC0d stores “0” information and MC1d stores “1” information due to the difference in the source connection method.

  In the read operation, BLT and BLB are set to the precharge state of the power supply voltage VDD by the precharge switch PSW, the word line (for example, WL0) is activated, and CS is switched from VDD to VSS by the common source switch CSW. As a result, for example, in the memory cell MC0d, the potential of BLT decreases with the discharge to CS, and the potential of BLB is maintained as it is. Therefore, read data is obtained by amplifying this potential difference with SA. When the read operation is completed, VDD is supplied to CS by CSW, and VDD is supplied to BLT and BLB by PSW.

  When such a configuration is used, as described above, the potential difference between the source and drain of the MOS transistor in the memory cell MC becomes zero except during the read operation, so that the subthreshold leakage current can be reduced. In addition, since the differential amplification method using complementary bit line pairs is used, it is resistant to noise and enables a high-speed and stable read operation. Further, since the MOS transistors are connected to both BLT and BLB in each memory cell MC, the load is equalized and a more stable read operation is possible.

  However, when the memory array as shown in FIG. 13D is applied to the system LSI as described above, the capacity of the bit line decreases as the memory capacity decreases, and noise resistance may be reduced. FIG. 14 is a diagram for explaining the relationship between bit line capacitance and noise tolerance in the memory array of FIG. As shown in this figure, a parasitic capacitance Ce exists between each bit line BLT, BLB and the ground voltage (power supply voltage), and a parasitic capacitance Ct exists between each bit line BLT, BLB and the common source line CS. Exists.

  In FIG. 14, in the case of a small capacity, the lengths of the bit lines BLT and BLB are shortened, and the values of both Ce and Ct are small. For example, with respect to the line noise induced from CS to BLT and BLB during the read operation, the influence can be reduced as the capacitance value of Ce is larger than the capacitance value of Ct. Further, the external noise induced in BLT and BLB from the outside during the read operation can be reduced as the Ce capacitance value increases.

  In a system LSI or the like, with high integration, for example, a data wiring or the like used in a circuit other than the ROM may be provided in a wiring layer or the like on a region where the ROM is formed. These are sources of external noise for the ROM. Furthermore, the amount of line noise and extraneous noise increases as the speed increases. Therefore, there is a need for a ROM having high noise resistance and capable of a stable read operation. Note that in a method in which a ROM having a large capacity of, for example, several hundreds K or more is applied to the SOC or the like and a part of the ROM is used, the bit line capacity and the like can be maintained to some extent, and thus such a problem does not occur. Sometimes. However, there is a strong demand for miniaturization and power saving particularly in mobile phones and the like, and it is desirable to set the required minimum capacity value.

  Accordingly, one of the objects of the present invention is to realize a stable read operation in a semiconductor device including a ROM. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A semiconductor device according to an embodiment of the present invention includes a mask ROM having a complementary bit line structure, and each memory cell of the mask ROM is constituted by two or more MIS transistors. The gates of the first and second MIS transistors that are constituent elements of the memory cells are connected to a common word line, and the source and drain of the first MIS transistor are connected to one of the complementary bit lines and the common source line. The source / drain of the second MIS transistor is connected to the other of the complementary bit lines and the power supply voltage wiring. A voltage on the high potential side is applied to the power supply voltage wiring, and a voltage that switches from the high potential side to the low potential side during a read operation is applied to the common source line.

  When such a configuration is used, there is no node in the first and second MIS transistors that is in the open state as described in the background art, and one of the complementary bit lines is set to the low potential side voltage during the read operation. Since the other of the complementary bit lines is connected to the high potential side voltage, the noise margin and the like are large, and a stable read operation is possible.

  In addition, the semiconductor device according to the embodiment of the present invention has a configuration in which a dummy MIS transistor is further provided in each memory cell described above. In the dummy third and fourth MIS transistors, one end of the source / drain is connected to one and the other of the complementary bit lines, respectively. By providing such a dummy MIS transistor, the load capacity of the complementary bit line can be sufficiently secured, and the noise resistance can be improved. That is, for example, in a small-capacity mask ROM used in a system LSI or the like, the load capacity of the bit line may be small and noise resistance may be insufficient, but such a problem can be solved.

  By using the semiconductor device according to the embodiment of the present invention, a stable read operation can be realized even with a small capacity ROM.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is used as an example of a transistor, and a MOS (Metal Oxide Semiconductor) transistor is used as an example of the transistor. In each drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding a circle symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a schematic diagram showing an example of a system configuration using the semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a mobile phone system, for example, in which a system LSI (semiconductor device) SYS_LSI such as an SOC or a microcomputer is used. For example, a CCD camera, a keyboard KEY, a display LCD, a speaker SPK, a microphone MIC, and the like are connected to the SYS_LSI, and the SYS_LSI processes various data including audio, images, and the like related thereto. In addition, the SYS_LSI inputs / outputs wireless data to / from the wireless processing unit RF. The RF modulates the radio data input from the SYS_LSI and transmits it via the antenna ANT, and demodulates the radio data received from the ANT and outputs it to the SYS_LSI.

  FIG. 2 is a block diagram showing a configuration example of the system LSI in FIG. A system LSI (semiconductor device) SYS_LSI shown in FIG. 2 includes, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM, a bus state controller BSC, various logic circuits LOG, an A / D converter ADC, and a PLL (Phase Locked Loop), FLASH memory, fuse (FUSE), external input / output circuit I / O, and the like. Each of these blocks is connected by an internal bus, and the BSC has an arbitration function for the internal bus.

  LOG corresponds to various things as needed, such as DSP (Digital Signal Processor), a graphic accelerator, LCD (Liquid Crystal Display) controller, etc., for example. The fuse (FUSE) holds various trimming information of the power source and frequency. The ADC is used in various processes including audio / image processing. Note that the power supply voltages V1, V2, and V3 in FIG. 2 have values of, for example, 1.2V, 3.3V, and 5.0V, respectively. V3 is required for writing and erasing the FLASH memory, and is generated by boosting V1.

  The ROM is, for example, a mask ROM that stores an identification ID of SYS_LSI and the like, and has a small capacity (for example, several K to several tens of K bits). Since this ROM operates at the same low power supply voltage V1 (1.2 V) as that of a CPU or the like, the logic judgment margin is reduced accordingly, and high noise resistance is required. Although not shown, in the wiring area at the upper part of the ROM, for example, wiring of an internal bus may pass, and these may become noise sources and affect the ROM.

  FIG. 3 is a block diagram showing a schematic configuration example of the ROM in the semiconductor device of FIG. The ROM illustrated in FIG. 3 includes a memory array ARY, a word driver WD, a column switch YSW, a read amplifier RD_AMP, a multiplexer MUX, a latch circuit LT, a control circuit CTL, and the like. The control circuit CTL receives a chip enable signal CE, a clock signal CLK, an address signal ADD, and the like from the outside, and decodes addresses and outputs various control signals. The memory array ARY has a small capacity and is not particularly limited. For example, the word array WL includes 8 to 64 word lines, 112 to 224 bit line pairs BLT and BLB, and their intersections. And a plurality of common source lines CS. For example, in the case of 64 × 224 pairs, the memory capacity is about 14K.

  The word driver WD activates predetermined word lines WL0 to WLn in the ARY upon receiving the address decoding by the CTL. The column switch YSW receives the control signal YSE by CTL, and takes the data of the bit line pairs BLT0 / BLB0 to BLTm / BLBm in the ARY into the global bit line pairs GBLT0 / GBLB0 to GBLTm / GBLBm. The read amplifier RD_AMP receives the control signal SAE from the CTL, differentially amplifies the data of each global bit line pair, and outputs the result to the internal read data lines QM0 to QMm. The multiplexer MUX receives the control signal SEL from the CTL, selects a part of QM0 to QMm, and outputs it to the latch circuit LT. For example, the MUX selects 1/4 to 1/8 from among 112 to 224 internal read data lines QM and outputs tens of bits of data. The latch circuit LT receives the control signal OE from the CTL and outputs external read data Q0 to Qk.

  Here, for example, when the configuration shown in FIG. 13D is applied to the memory array ARY of FIG. 3, a small number of MOS transistors such as 8 to 64 for each of the bit lines BLT and BLB, respectively. Will be connected. In particular, in the case of eight or the like, the capacity of each of the bit lines BLT and BLB becomes necessary small, and the noise resistance becomes low. Therefore, for example, a configuration as shown in FIG. 4 is used.

  4 is a circuit diagram showing a configuration example of the memory array of FIG. 3 in the semiconductor device according to the first embodiment of the present invention. The memory array ARY1 shown in FIG. 4 shows only a plurality of word lines WL0 to WLn and a pair of bit lines BLTm and BLBm crossing the word lines WL0 to WLn in the memory array ARY of FIG. A bit line pair is provided. A memory cell MC0 is provided at the intersection of the word line WL0 and the bit line pair BLTm, BLBm, and a memory cell MCn is provided at the intersection of the word line WLn and the bit line pair BLTm, BLBm. In addition, a common source line CSm extending in the same direction as that corresponding to the bit line pair BLTm, BLBm is provided, and further, corresponding to each word line WL0 to WLn, a power supply voltage line extending in the same direction (in FIG. Power supply voltage (VDD) is provided.

  MC0 is composed of two NMOS transistors MN40t and MN40b. MN40t has its gate connected to WL0, one of its source and drain connected to BLTm, and the other connected to common source line CSm. MN40b has its gate connected to WL0, one of its source and drain connected to BLBm, and the other to power supply voltage VDD. Connected to each. MCn includes two NMOS transistors MN4nt and MN4nb. MN4nt has its gate connected to WLn, one of its source and drain connected to BLTm, and the other connected to power supply voltage VDD. MN4nb has its gate connected to WLn, one of its source and drain connected to BLBm, and the other connected to CSm. Is done. In MC0 and MCn, the other connection destination of the source and the drain has an opposite relationship, whereby MC0 stores, for example, “0” information and MCn stores, for example, “1” information.

  The operation of the memory array ARY1 is the same as that of FIG. 13D described above. In a state where the bit line pair BLTm, BLBm is precharged to VDD, a predetermined word line WL is activated, and the common source line CSm is also activated. Is driven from VDD to the ground voltage VSS to perform a read operation. The difference from FIG. 13D is that the NMOS transistors MN40b and MN4nt on the side not connected to the common source line CSm in each memory cell MC are open in FIG. 13D, whereas in FIG. It is connected to VDD. Although not shown in the figure, in terms of the cross-sectional structure, in FIG. 4, the diffusion layers of MN40b and MN4nt are connected to the power supply voltage wiring VDD formed in the upper metal wiring layer or the like through the contact hole. In FIG. 13D, this contact hole does not exist, and the power supply voltage wiring VDD does not exist.

  FIG. 5 is a circuit diagram showing a configuration example of a memory array obtained by modifying FIG. The memory array ARY2 shown in FIG. 5 includes NMOS transistors MN50t, MN50b, MN5nt, and MN5nb similar to the MN40t, MN40b, MN4nt, and MN4nb in FIG. 4, and their connection relation is the same as that in the configuration example of FIG. However, in FIG. 5, the layout configuration is different from that in FIG. 4, and the power supply voltage wiring VDD is formed to extend in the same direction as the bit line pair BLTm, BLBm. MN5nt is connected. Since other configurations and operations are the same as those in FIG. 4, detailed description thereof is omitted.

  When the memory array configuration as shown in FIG. 4 or FIG. 5 is used, one bit line BL is connected to the common source line CS (ie, VSS) via the NMOS transistor and the other bit line is connected to the NMOS transistor during the read operation. To the power supply voltage VDD. Compared to this, in the case of FIG. 13D, one bit line is connected to VSS, and the other bit line is at a precharge level of VDD. This VDD precharge level may be slightly reduced by leakage from an open node through an NMOS transistor. In addition, since it is in a precharge state, it is greatly affected when noise is mixed. The smaller the bit line capacity, the greater the effect of this precharge level drop and noise.

  Therefore, when the configurations of FIGS. 4 and 5 are used, since one bit line is connected to VDD instead of the precharge state during the read operation, such a decrease in precharge level does not occur. Furthermore, since it is not a precharge state, the influence of noise can also be reduced. Therefore, the read margin can be expanded, high noise resistance can be obtained, and a stable read operation can be performed. Also, high-speed reading is possible.

  Further, except for the read operation, since the node on the opposite side of the bit line is VDD in both of the two NMOS transistors in the memory cell MC, the subthreshold leakage current can be reduced and the power supply voltage can be lowered. It is possible. Note that which layout configuration of FIG. 4 or FIG. 5 is used may be appropriately determined in consideration of the number and pitch of the required word lines and bit lines, the circuit area, and the like. However, the layout configuration example of FIG. 4 has a configuration in which the power supply voltage wiring VDD is sandwiched between the word lines WL as compared with the layout configuration example of FIG. There is an advantage that can be reduced.

  As described above, by using the semiconductor device according to the first embodiment, it is possible to improve noise tolerance in the ROM.

(Embodiment 2)
In the first embodiment described above, noise resistance is improved by connecting one end of the NMOS transistor in each memory cell MC to VDD. In the second embodiment, in addition to this, the capacitance of the bit line is increased. The noise resistance is further improved by increasing the noise. FIG. 6 is a circuit diagram showing a configuration example of the memory array of FIG. 3 in the semiconductor device according to the second embodiment of the present invention.

  A memory array ARY3 shown in FIG. 6 includes a plurality of word lines WL0 to WLn and bit line pairs BLTm and BLBm intersecting with the word lines WL0 to WLn, and each word line WL is formed of a set of two. For example, WL0 is configured by a word line WL0_0 and a word line WL0_1 that are adjacent to each other, and these are connected to each other. Memory cell MC0 is provided at the intersection of word line WL0 (WL0_0, WL0_1) and bit line pair BLTm, BLBm, and memory cell MCn is provided at the intersection of word line WLn (WLn_0, WLn_1) and bit line pair BLTm, BLBm. Is provided.

  In addition, a common source line CSm extending in the same direction as that corresponding to the bit line pair BLTm, BLBm is provided, and further, corresponding to each word line WL0 to WLn, a power supply voltage line extending in the same direction (in FIG. Power supply voltage (VDD) is provided. Note that only one bit line pair BLTm, BLBm is shown here, but actually, a plurality of bit line pairs are provided.

  MC0 includes four NMOS transistors MN60t, MN60b, MN60t_d, and MN60b_d. MN60t has a gate connected to WL0_0, one of the source and drain connected to BLTm, and the other connected to common source line CSm. MN60b has a gate connected to WL0_0, one of the source and drain connected to BLBm, and the other connected to power supply voltage VDD. Connected to each. In the MN 60t_d, the gate is connected to WL0_1, one of the source and the drain is connected to BLTm, and the other is opened. In the MN 60b_d, the gate is connected to WL0_1, one of the source and the drain is connected to BLBm, and the other is opened.

  Similarly, MCn is also composed of four NMOS transistors MN6nt, MN6nb, MN6nt_d, and MN6nb_d. MN6nt has its gate connected to WLn_0, one of its source and drain connected to BLTm, and the other connected to VDD. MN6nb has its gate connected to WLn_0, one of its source and drain connected to BLBm, and the other connected to CSm. . In MN6nt_d, the gate is connected to WLn_1, one of the source and the drain is connected to BLTm, and the other is opened. In MN6nb_d, the gate is connected to WLn_1, one of the source and the drain is connected to BLBm, and the other is opened.

  As described above, the configuration example of FIG. 6 is such that two dummy NMOS transistors are added in each memory cell MC as compared with the configuration example of FIG. 4 described above. That is, for example, in MC0, MN60t and MN60b in FIG. 6 have the same connection relationship as MN40t and MN40b in FIG. 4, and in addition, dummy NMOS transistors MN60t_d and MN60b_d are connected to BLTm and BLBm, respectively. Yes. The dummy NMOS transistors MN60t_d and MN60b_d are activated in the same manner when the gates of MN60t and MN60b (that is, WL0) are activated during the read operation, thereby increasing the load capacities of BLTm and BLBm. Bear. The read operation procedure is the same as that in FIG.

  As described above, when the configuration example of FIG. 6 is used, the number of NMOS transistors connected to the bit lines BLTm and BLBm is doubled compared to the configuration example of FIG. A load capacity of BLBm is obtained. Therefore, noise resistance is further improved as compared with the case of FIG. 4, and a stable read operation is possible. Although not shown in the drawing, a set of two word lines (for example, WL0_0, WL0_1) in FIG. 6 may be configured to be simultaneously driven by two individually provided driver circuits, or common. It may be configured to be driven by one driver circuit. In the former case, it is not always necessary to connect a set of two word lines to each other.

  FIG. 7 is a circuit diagram showing a configuration example in which the memory array of FIG. 6 is modified. The memory array ARY4 shown in FIG. 7 is different from the memory array ARY3 of FIG. 6 in the following two points. The first point is that one of a set of two word lines WL is fixed to the ground voltage VSS. That is, for example, the memory cell MC0 in FIG. 7 includes four NMOS transistors MN70t, MN70b, MN70t_d, and MN70b_d corresponding to the four NMOS transistors MN60t, MN60b, MN60t_d, and MN60b_d in MC0 in FIG. Among these, the gates of dummy NMOS transistors MN70t_d and MN70b_d are fixed to VSS.

  The second point is that a node on the side different from the bit line BL in the dummy MMOS transistor is connected to the common source line CS or the power supply voltage VDD. That is, for example, in MC0 of FIG. 7, one end of the source / drain of MN70t_d is connected to the common source line CSm in common with one end of the source / drain of MN70t, and one end of the source / drain of MN70b_d is connected to the source / drain of MN70b. It is connected to the power supply voltage VDD in common with one end.

  In such a configuration example, the dummy NMOS transistor always maintains an off state with the VSS of its gate, and bears the function of increasing the load capacities of BLTm and BLBm, as in the case of FIG. . Further, since one end of the dummy NMOS transistor is connected to VDD or CS, almost no subthreshold leakage current is generated except during the read operation. Therefore, as in the case of FIG. 6, noise tolerance can be improved, and a stable read operation can be realized.

  In the configuration example of FIG. 7, one of the two word lines is fixed to VSS, but this one word line is activated together with the other word line as in the case of FIG. It is also possible. In this case, power consumption may increase, but each bit line BLTm, BLBm can be connected to VDD or CS (that is, VSS) via two NMOS transistors, thus realizing high driving capability and high-speed reading. It becomes possible. Needless to say, the capacity of the bit line can be sufficiently secured, so that a stable read operation is possible. Furthermore, in the configuration example of FIG. 6 or FIG. 7, two dummy NMOS transistors are provided in each memory cell MC. However, depending on the allowable circuit area, four or six such dummy transistors are provided. It is also possible to provide individual pieces.

  FIG. 8 is a diagram for explaining the parasitic capacitance of the dummy NMOS transistor in the memory array of FIG. 6 or FIG. As shown in FIG. 8, the dummy NMOS transistor MN_d has various parasitic capacitances such as a gate-drain capacitance Cgd, a gate-source capacitance Cgs, a substrate-drain capacitance Cbd, and a substrate-source capacitance Cbs. . These capacitance values change depending on various voltage conditions of MN_d, but can contribute as load capacitance between the bit lines BLTm and VSS or between BLTm and VDD.

  FIG. 9 shows an example of the layout configuration of the memory array of FIG. 6, wherein (a) is a schematic diagram showing an outline thereof, and (b) is a circuit diagram of a layout image corresponding to (a). . The circuit shown in FIG. 9B is equivalent to the circuit shown in FIG. In the layout configuration example shown in FIG. 9A, two N-type diffusion layers NDF are provided, and a plurality of gate wiring layers PO made of polysilicon or the like are provided thereon via a gate insulating film (not shown). Yes. Each of the plurality of gate wiring layers PO corresponds to a separation layer that separates a pair of word lines (word line pairs) as described in FIG. 6 and word line pairs adjacent to each other.

  9A and 9B, for example, a set of two word lines WLn_0 and WLn_1 included in the memory cell MCn described in FIG. 6 are arranged adjacent to each other as a word line pair, and are adjacent to and adjacent to each other. Word line pairs WLn-1_0 and WLn-1_1 included in the memory cell MCn-1 are arranged, and an isolation layer is arranged between the two word line pairs. Here, the ground voltage VSS is supplied to the isolation layer, whereby the adjacent memory cells (MCn and MCn−1) are isolated. By using this separation layer, as described in Patent Document 1, it is possible to reduce the area as compared with the case of performing separation using an oxide film or the like.

  9A and 9B, the diffusion layer between two word lines included in the word line pair is connected to the bit line BLT or BLB of the upper wiring layer via a contact hole (not shown). On the other hand, in the diffusion layers on both sides of the two word lines, the node corresponding to the dummy NMOS transistor is opened by providing no contact hole, and the node corresponding to the normal NMOS transistor is not shown. It is connected to VDD or CS of the upper wiring layer through a contact hole.

  FIG. 10 shows an example of the layout configuration of the memory array of FIG. 7, where (a) is a schematic diagram showing an outline thereof, and (b) is a circuit diagram of a layout image corresponding to (a). . The circuit shown in FIG. 10B is equivalent to the circuit shown in FIG. In the layout configuration example shown in FIG. 10A, as in the case of FIG. 9, two N-type diffusion layers NDF are provided, and a plurality of layers made of polysilicon or the like are formed on the upper layer via a gate insulating film (not shown). A gate wiring layer PO is provided. Each of the plurality of gate wiring layers PO corresponds to a separation layer that separates a pair of word lines (word line pairs) as described in FIG. 7 and word line pairs adjacent to each other.

  10A and 10B, for example, word lines WLn and VSS included in the memory cell MCn described in FIG. 7 are arranged adjacent to each other as word line pairs, and in close proximity thereto, A word line pair (WLn-1 and VSS) included in the adjacent memory cell MCn-1 is arranged, and an isolation layer is arranged between the two word line pairs. Here, the ground voltage VSS is supplied to the isolation layer, whereby the adjacent memory cells (MCn and MCn−1) are isolated. Here, the diffusion layer between two word lines included in the word line pair is connected to VDD or CS of the upper wiring layer via a contact hole (not shown). On the other hand, the diffusion layers on both sides of the two word lines are connected to the bit lines BLT or BLB of the upper wiring layer through contact holes (not shown).

  In such a layout configuration, the area can be reduced. On the other hand, if the capacity of the ROM itself is small as described with reference to FIG. 1, for example, as shown in FIG. In the case of a transistor, there is a possibility that the bit line capacity cannot be secured sufficiently. Therefore, as shown in FIG. 9 and FIG. 10, one memory cell is composed of four (or more) NMOS transistors, so that a sufficient bit line capacity can be ensured in a minimum circuit area. It becomes possible.

  As described above, by using the semiconductor device of the second embodiment, a more stable read operation than that of the first embodiment can be performed.

(Embodiment 3)
In the third embodiment, a configuration example in which the configuration example in FIG. 4 described in the first embodiment is modified will be described. FIG. 11 is a circuit diagram showing a configuration example of the memory array in the semiconductor device according to the third embodiment of the present invention. The memory array ARY5 shown in FIG. 11 includes two NMOS transistors in one memory cell MC, as in FIG. 4, and the connection relationship is substantially the same as in FIG. The difference from FIG. 4 is that in FIG. 4, the power supply voltage wiring VDD is provided in the same direction as the extending direction of the word line WL, and the common source line CS is provided in the same direction as the extending direction of the bit line BL. In FIG. 11, conversely, CS is provided in the same direction as the extending direction of WL, and VDD is provided in the same direction as the extending direction of BL.

  That is, in FIG. 11, a plurality of word lines WL0 to WLn and a plurality of common source lines CS0 to CSn corresponding to the word lines extend in the same direction and intersect with WL0 to WLn and CS0 to CSn. In the direction, the bit line pair BLTm, BLBm and the power supply voltage wiring VDD extend. A memory cell MC0 is provided at the intersection of WL0 and BLTm, BLBm, and a memory cell MCn is provided at the intersection of WLn and BLTm, BLBm. MC0 is composed of two NMOS transistors MN110t and MN110b. Each node of MN110t is connected to WL0, BLTm, and VDD, and each node of MN110b is connected to WL0, BLBm, and CS0. MCn includes two NMOS transistors MN11nt and MN11nb. Each node of MN11nt is connected to WLn, BLTm, and CSn, and each node of MN11nb is connected to WLn, BLBm, and VDD.

  When such a configuration is used, as in the case of FIG. 4, in addition to enabling a stable read operation, the number of common source lines CS driven during the read operation is smaller than in the case of FIG. Therefore, current consumption can be reduced. More specifically, FIGS. 4 and 11 show only one pair of bit lines BLTm and BLBm, but actually, a plurality of pairs of bit lines BLT0 / BLB0 to BLTm / BLBm are provided. In the case of FIG. 4, a plurality of common source lines CS0 to CSm are further provided corresponding to each of the bit line pairs.

  Here, when the read operation is performed in the configuration example of FIG. 4, it is necessary to activate the word line WL0 and drive all the plurality of common source lines CS0 to CSm from VDD to VSS, for example. Therefore, the current consumption accompanying this driving increases. On the other hand, when the read operation is performed in the configuration example of FIG. 11, for example, the word line WL0 may be activated and one common source line CS0 may be driven from VDD to VSS. Therefore, current consumption associated with this driving can be reduced. As another effect, the power source voltage wiring VDD is not the common source line CS but extends in the same direction as the bit line pair BLTm, BLBm. Therefore, a line induced to the BLTm, BLBm during the read operation. Noise can be reduced. However, even in the arrangement configuration of the common source line CS as shown in FIG. 4, the common-mode noise can be reduced by differentially amplifying BLTm and BLBm.

  FIG. 12 is a circuit diagram showing a configuration example including a part of peripheral circuits in the memory array of FIG. In FIG. 12, two word lines WL adjacent to each other are taken as one set, and one common source line CS is provided for each set. That is, CS01 is provided corresponding to WL0 and WL1, and CSij is provided corresponding to WLn−1 and WLn. Each word line WL0 to WLn is driven by a word driver WD, and the WD activates a predetermined word line in response to an address decode signal XDEC and a control signal (read enable signal) RE from the control circuit CTL.

  Each common source line CS01 to CSij is driven by a common source driver CSD. The CSD drives CS01 by, for example, NOR operation of WL0 and WL1, and similarly drives CSij by NOR operation of WLn−1 and WLn. . Thereby, for example, when WL0 or WL1 is activated, CS01 is driven to VSS. Thus, by making one common source line correspond to a plurality of word lines, it is possible to increase the area efficiency of the common source driver CSD and the common source line CS.

  The bit lines BLTm and BLBm are connected to the sense amplifier circuit SA via Y switches (PMOS transistors) YSmt and YSmb, respectively. The Y switch corresponds to the column switch YSW in FIG. 3, and the sense amplifier circuit SA corresponds to the read amplifier RD_AMP in FIG. YSmt and YSmb are turned on in response to a control signal (YS enable signal) YSE from the control circuit CTL, and SA receives a control signal (sense amplifier enable signal) SAE from the CTL and determines a potential difference between BLTm and BLBm. Amplify differentially. Further, a precharge circuit PRE_C is connected to each bit line BLTm, BLBm. PRE_C includes two PMOS transistors, and when receiving a control signal (precharge signal) PRE from the control circuit CTL, BLTm and BLBm are connected to the power supply voltage VDD via the two PMOS transistors.

  As described above, by using the semiconductor device according to the third embodiment, in addition to the stable read operation similar to that in the first embodiment, it is possible to reduce power consumption and the like. Here, the configuration example of FIG. 4 is modified to show the configuration example in which the common source line is provided in the same direction as the word line. Similarly, for example, FIG. 9 and FIG. Similar modifications can be made. That is, for example, a layout configuration in which VDD and CS are interchanged in FIGS. 9 and 10 may be used.

  As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The semiconductor device according to the present invention is a technique that is particularly useful when applied to a small-capacity mask ROM used in a system LSI or the like, and is not limited to this, and can be widely applied to general mask ROMs.

1 is a schematic diagram showing an example of a system configuration using the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of the system LSI. FIG. 3 is a block diagram illustrating a schematic configuration example of a ROM in the semiconductor device of FIG. 2. FIG. 4 is a circuit diagram showing a configuration example of a memory array of FIG. 3 in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a configuration example of a memory array obtained by modifying FIG. 4. FIG. 4 is a circuit diagram showing a configuration example of a memory array of FIG. 3 in a semiconductor device according to a second embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a configuration example in which the memory array of FIG. 6 is modified. FIG. 8 is a diagram for explaining a parasitic capacitance of a dummy NMOS transistor in the memory array of FIG. 6 or FIG. 7. FIG. 6 shows an example of the layout configuration in the memory array of FIG. 6, (a) is a schematic diagram showing an outline thereof, and (b) is a circuit diagram of a layout image corresponding to (a). FIG. 7 shows an example of the layout configuration in the memory array of FIG. 7, (a) is a schematic diagram showing an outline thereof, and (b) is a circuit diagram of a layout image corresponding to (a). FIG. 10 is a circuit diagram showing a configuration example of a memory array in a semiconductor device according to a third embodiment of the present invention. FIG. 12 is a circuit diagram illustrating a configuration example including a part of the peripheral circuit in the memory array of FIG. 11. The example of schematic structure of the memory array in ROM examined as a premise of this invention is shown, (a)-(d) is a circuit diagram which shows a different example of a structure, respectively. FIG. 14 is a diagram for explaining the relationship between bit line capacitance and noise tolerance in the memory array of FIG.

Explanation of symbols

SYS_LSI System LSI
CCD CCD camera KEY Keyboard LCD Display SPK Speaker MIC Microphone RF Wireless processing unit ANT Antenna I / O External input / output circuit LOG Logic circuit BSC Bus state controller ADC A / D converter FUSE Fuse LT Latch circuit MUX Multiplexer RD_AMP Read amplifier YSW Column switch ARY Memory array CTL control circuit WD Word driver MN NMOS transistor WL Word line BLT, BLB Bit line CS Common source line VDD Power supply voltage VSS Ground voltage MC Memory cell C Capacity PO Gate wiring layer NDF Diffusion layer CSD Common source driver SA Sense amplifier circuit YS Y switch PRE_C Precharge circuit INV Inverter circuit PSW Precharge Pitch CSW common source switch

Claims (5)

Multiple word lines,
A plurality of bit line pairs each extending in a direction intersecting with a direction in which the plurality of word lines extend and having complementary first and second bit lines;
A plurality of common source lines driven by either the high potential side voltage or the low potential side voltage;
A plurality of power supply voltage lines to which a high potential side voltage is applied;
A plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit line pairs;
Each of the plurality of memory cells includes two or more MIS transistors including first and second MIS transistors,
The first and second MIS transistors are commonly connected to a first word line whose gate is one of the plurality of word lines,
In the first MIS transistor, one of a source and a drain is connected to the first bit line, and the other is connected to one of the plurality of common source lines.
In the semiconductor device, one of a source and a drain of the second MIS transistor is connected to the second bit line, and the other is connected to the power supply voltage wiring. The semiconductor device according to claim 1,
Each of the plurality of memory cells further includes third and fourth MIS transistors,
The third and fourth MIS transistors have a gate connected to a second word line adjacent to the first word line, the gate of which is one of the plurality of word lines;
The third MIS transistor has one of a source and a drain connected to the first bit line,
In the semiconductor device, the fourth MIS transistor has one of a source and a drain connected to the second bit line. The semiconductor device according to claim 1 or 2,
The plurality of common source lines extend in the same direction as the plurality of word lines,
One of the plurality of common source lines is driven from a high potential side voltage to a low potential side voltage in response to activation of any of the plurality of word lines. The semiconductor device according to claim 2,
In the third MIS transistor, the other of the source and the drain is open,
The fourth MIS transistor is a semiconductor device characterized in that the other of the source and the drain is open. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device is a system LSI,
The semiconductor device, wherein the plurality of memory cells are mask ROMs of tens of K bits or less included in the system LSI.

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