JPH02144737A - Counting circuit control system - Google Patents

Abstract

PURPOSE:To decrease the number of hardware digits and at the same time to flexibly change the desired number of digits at every counter or measurement and to secure the accurate measurement by dividing the measuring counters included in a unit to be measured into the most significant digit and other parts. CONSTITUTION:In a device consisting of a unit 1 to be measured and a measurement unit 2, plural measuring counters 11 included in the unit 1 are divided into the most significant digits 11a and other parts 11b for example. At the same time, the digit 11a of the each counter 11 reads the working value of the unit 1 out of the unit 2 at a specific frequency and adds the working value to the value of an area corresponding to each counter 11 of a memory 23 included in the unit 2. Then the parts 11b are read out except the most significant digits 11a of the counters 11 after the working of the unit 1 is stopped and then synthesized with the value of the corresponding area of the memory 23 of the unit 2 as the value of each counter 11. As a result, the number of hardware digits can be decreased for each counter 11 of the unit 1. At the same time, the number of necessary digits can be flexibly changed at every counter or measurement to ensure the accurate measurement.

Description

[Detailed Description of the Invention] [Summary] Regarding a control method for a plurality of performance measurement counters provided in a unit under test that constitutes a computer system, when configured with hardware, a counter with a relatively large number of digits can be controlled. In the case of a one-digit error, it is not possible to guarantee the correct value.Also, when configured using software, measurement errors may occur.In particular, in the case of parallel machines, performance may vary depending on how jobs are divided. The purpose of this is to solve the problem that the operation of the circuit to be measured may differ, making it impossible to perform accurate measurements on the circuit to be measured.
In an apparatus consisting of the above-mentioned unit to be measured (
A plurality of measurement counters (R
1, R2, ~), for example, the most significant digit (R1-A,
R2-A.

~) and other parts (R1-B, R2-B, ~), and the most significant digit of each measurement counter (I11, R2, ~) indicates the operation of the unit under test (Vl). the value inside,
Read from the measurement unit (V2) at a specific frequency,
It is added to the value of the area corresponding to each measurement counter (1?1.R2, ~) in the memory (1) in the measurement unit (V2), and after the unit under test (Vl) stops operating, Read out the parts (R1-B, R2-B, ~) other than the most significant digit of each of the above measurement counters (R1, R2, ~),
The value of each measurement counter (R
1, R2°~).

[Industrial application field]

The present invention relates to a control method for a plurality of performance measurement counters provided in a unit under test that constitutes a computer system.

Recently, for example, IJ SP (LISP), PROG (P
I? There is an active trend in the development of parallel machines, artificial intelligence machines, large-scale machines, etc. that execute programs written in special high-level languages such as 0LOG).

Since there is little data on past hardware knowledge and hardware performance regarding such new machines, we focused on the fact that programs written in such languages have many processes that are executed repeatedly. This part is configured with hardware to improve the performance of the parallel machine, artificial intelligence machine, etc.

In this case, it is necessary to understand how the hardware part actually operates, evaluate it, and build a high-performance parallel machine, artificial intelligence machine, etc. The program is executed, the number of times the hardware part operates is counted, and its effectiveness is evaluated.

At this time, if the machine were to evaluate itself, there would be a large overhead and there is a risk that the evaluation would be different from the actual behavior of each hardware, so external devices such as service processors (SVPs), etc. It is practical to read out and evaluate the values of each counter in the unit under test (machine).

However, if the counter is constructed from pure hardware, there are problems such as the need to provide several types of counters with a relatively large number of digits, and the inability to maintain a correct value when a digit error occurs.

Also, if the counter is implemented in software, an extra step is required for counting, which may cause measurement errors, and especially in the case of parallel machines, it may be necessary to divide the processing among multiple machines. Depending on the method used, there are problems such as changes in the behavior of the hardware or lack of reproducibility.There is a need for a counter circuit control method that can avoid these various problems for the performance evaluation counter. It's starting to happen.

[Prior Art and Problems to be Solved by the Invention] FIG. 3 is a diagram illustrating a conventional counting circuit control method, and particularly shows a hardware-based method.

The unit to be measured l-(ml is specifically the main unit of the computer system, and the unit to be measured (V2) 2 is, for example, a service processor (SVP).

The unit under test (Vl) 1 has the aforementioned hardware circuit, that is, the circuit under test (PI, R2, . . . -) 13, and the circuit under test (PL, R2, -) 13 performs some operation. The interface circuit (mouth 1.Q2
．． --) 12 detects and the counter circuit (R1, R2,
-・) Controls 11 and makes it count amplify.

The count value is transferred from the service processor (SVP) 2 to the count register (rl, r2.--) in each counter circuit (R1, R2, -') 11, for example, by a known scan-in/out mechanism. The service processor (SVP) 2 evaluates each circuit under test (PI, R2, -----) 13 by reading the value of .

In such a conventional system, as shown in the figure, the counter circuit 1 of each counter circuit (171, R2, ---) 11 is
-Register (rLr2.-) It had the count value directly in ie.

Therefore, each count register (rl
.

r2.・-) If the number of digits (or number of bits) of lie is different and the number of operations of the circuit under test (PL, R2, -) 13 is large, the register (rl
, r2) required lie.

In addition, in the counter circuit (Ri) 11 constructed by -degree, if an increment operation is performed more than expected and a digit error occurs, there is a problem that the correct value cannot be held.

Next, the circuit under test (PL, R2, -.
-) Consider the case of counting the number of operations of 13.

In this case, first, for example, a specific circuit under test (Pi)
If counting processing is performed in a program or subroutine related to 13, the circuit under test (Pi)
This requires a step to count 13, which increases the overhead in the subroutine, and causes problems such as measurement errors and lack of reproducibility due to the counting process.

In addition, the counting process is performed by the operating system (O8
) etc., measurement errors caused by individual programs can be avoided, but the operating system (O
As the overhead increases in step 5), it becomes difficult to specify the timing to start a program that uses each circuit under test (Pi) 13, making it difficult to accurately evaluate the operation of the circuit under test (Pi) 13. There was a problem with becoming.

Furthermore, in the case of parallel machines, each circuit under test (
Pi) 13 may behave differently, and from this point of view as well, there was a problem that accurate evaluation was difficult.

In view of the above conventional drawbacks, the present invention provides a control method for a plurality of performance measurement counters provided in a unit under test that constitutes a computer system, which requires a relatively large number of digits when realized by hardware. The need for a large number of counters; the inability to guarantee the correct value when one digit is off; and the possibility that measurement errors will occur if it is realized by software 1. Particularly in the case of parallel machines, it is difficult to divide jobs The purpose of this invention is to provide a counting circuit control method that solves the problem of not being able to accurately measure the circuit to be measured because the operation of the circuit to be measured may differ depending on the method of measurement.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the counting circuit control system of the present invention.

The above problems are solved by a count circuit control system configured as follows.

Unit to be measured 1-(Vl)1 and measurement unit (V2)
2, a plurality of measurement counters (R1, R2, ~) 11 provided in the unit to be measured 1-(Vl) 1 are, for example, the most significant digit (R1-8). , R2-Δ, ~) 11.
11 and other parts (R1-B, R2-8, ~)
11b, and each measurement counter (R1, R2,
The most significant digit of 11 reads out the operating value of the unit under test (Vl) 1 from the measuring unit (V2) 2 at a specific frequency, and stores the value in the memory (V2) in the measuring unit (V2) 2 at a specific frequency. M) Each measurement counter in 23 (R1, R2, ~
)11, and after the operation of the measured unit 1-(Vl)1 has stopped,
The most significant digits (R1-A, R2-A, ~) of each of the above measurement counters (R1, R2, ~) 11. Parts other than 11a (
R113, R2-B.

~) 11b is read and combined with the value of the corresponding area on the memory (M) 23 in the measurement unit (V2) 2 to obtain the value of each measurement counter (R1, R2, ~) 11. Configure it as follows.

[Effect]

That is, according to the present invention, in a control method for a plurality of performance measurement counters provided in a unit to be measured constituting a computer system, a plurality of measurement counters provided in the unit to be measured constitute a computer system. For example, by focusing on the fact that the overflow of the most significant digit (Ri-A
) and the other part (Ri-[1), and while the unit under test is in operation, a measurement unit, for example, a service processor (SVP), sends information to each measurement counter in the unit under test. , multiple most significant digits (
The most significant digit (Ri-A) is read out periodically and added to the value of the specific area corresponding to each counter in the local memory (M) in the measurement unit.
) by repeating returning the value to 0, the upper digit part of each counter is constructed on the memory.

At this time, the buffer (Ri-C) of the value of the most significant digit of each measurement counter is stored in the buffer (Ri-C) of the value of the most significant digit of each incrementer (At) by the measurement unit. Read the most significant digit (Ri-A) and set it to 0''
The buffer (Ri
-C) is moved to the most significant digit (R4-A), and itself is “
Return to 0''.

Then, at the time when the operation of the unit under test stops, the portion of each counter other than the above-mentioned topmost part (Ri-B)
is read out and stored in the local memory (M
) is combined with the value of the upper digit part constructed within ) to obtain the value of all digits of each measurement counter.

Therefore, the number of hardware digits of each measurement counter in the unit under test is relatively small and may be fixed.
Since the upper digit part constructed on the memory is allowed up to the size of the memory in the bit direction, a very large value can be counted with the above-mentioned relatively small amount of hardware. Furthermore, there is an effect that the required number of digits can be changed flexibly for each counter/measurement.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a principle diagram of the counting circuit control method of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. -(Vl
) 1, the unit to be measured 1-(Vl)
For example, the measurement counter (Ri) 11 in 1 is divided into the most significant digit (Ri-A) 11a and the other part (Ri-A).
B) divided into 11b and the unit to be measured 1-(Vl)
1 is in operation, the most significant digit (R1-Δ) 11a of the measurement counter (R4) 11 is read at a specific frequency, and each measurement counter in the storage section (M) in the measurement unit (V2) 2 is read out. The most significant digit of each measurement counter (Ri) 11 is constructed by adding it to the area corresponding to the counter (R1) 11, and when the unit under test 1-(Vl)1 stops operating. Means for reading the removed portion (R4-8) and combining it with the above-mentioned upper digits to generate values for all digits of each counter is necessary for carrying out the present invention.

Hereinafter, the counting circuit control system of the present invention will be explained with reference to FIG. 2 while referring to FIG.

In FIG. 2, Pl, R2, -.13 are the measured circuits provided in the unit to be measured, for example, the main unit of the computer system, and are hardware circuits often used when executing the above-mentioned program. The present invention relates to a counting operation for counting how many times the circuit under test (PI, R2, -.) 13 operates during program execution.

In the present invention, as described above, each measurement counter (Ri) 11 has, for example, the most significant digit (Ri-A
) 11a and the other part (Ri-B) 11b.

Now, the program is executed in the unit under test (ml), and in response to any change in the circuit under test (Pi) 13, the control circuit (R1) 12 sets the measurement counter (Ri).
11 to increase the counter value.

Measurement unit 1-(V2)2, for example, a central processing unit (CPU) of a service processor (SVP) of a computer system.
) 21 is connected to the measurement counter (I) of the unit under test (Vl) 1 via the read/write circuit (E) 22.
li) Read out the most significant digit (R4-A) 11a of 11 sequentially, for example, by a known scan-in/out mechanism,
The new carry value is added (“+1”) to the value of the upper digit corresponding to each measurement counter (Ri) 11 held in the storage unit (M) 23, and the value of the upper digit (Ri−8) is )11
Return the value of a to 0°.

Each measurement counter (Ri) 11 buffers (Ri-C
) 11c temporarily holds the carry value output from the adder (Ai) 11d when the most significant digit (R4A) 11a is accessed from the measurement unit I-(V2)2, and uses it in the cough measurement unit 1. - (V2) After the access from 2 is completed, the value is transferred to the most significant digit (Ili-A
) 11a, and operates so that it is at "0°".

The above operation is repeated while the unit under test (Vl) is in operation, and the period is determined by each measurement counter (R4).
) While all the most significant digits (Ri-A) 11a of 11 are updated once in the measurement counter (R4) 11 (that is, a carry from the adder (incrementer) 11d comes), The value of the most significant digit (Ri-A) 11a is set to be read out from the measurement unit (V2) 2 at least once. (For example, the earliest measurement counter (Ri
) 11 update cycles or less. ) In this way, the unit under test 1-(Vl)1 has stopped operating (i.e.,
After the program execution has finished), the measurement unit (V2
) 2's central processing unit (CPU) 21, the part (Ri-B) 11b excluding the most significant digit is read out, and combined with the value of the corresponding upper digit in the storage unit (M) 23,
Each measurement counter (Ri) shall be the value of all 11 digits.

At this time, if the value remains in the buffer (Ri-C) 11c, it must be moved to the most significant digit (R4-^) 11a and added to the most significant digit corresponding to each counter (Ri) 11. Therefore, in reality, the measured unit 1-(
After Vl) 1 stops operating, the most significant digit (Ri-A) 11a is read out before reading out the portion (Ri-B) Ilb excluding the most significant digit.

In this way, the values of all digits of each measurement counter (Ili) 11 can be known.

As described above, the present invention provides a device comprising a measurement unit (V2) 2 and a unit to be measured (ml), in which the measurement counter (R4) 11 in the unit to be measured (Vl) 1 is set to the most significant digit. (Ri-A) 11a and other parts (Ri-B) Ilb, and when the unit to be measured 1-(Vl)1 is in operation, the measurement counter (Ri
) The most significant digit (R4-A) 11a of 11 is read out at a specific frequency, and the storage section (M
) is added to the area corresponding to each measurement counter (Ri) 11 to construct the upper digits, and the unit to be measured (Vl)
When ■ stops operating, each measurement counter (
Ri) 11 except for the most significant digit (Ri-B) is read out and combined with the above-mentioned most significant digit to generate values for all digits of each counter.

In the above embodiment, the part excluding the most significant digit (1
7i-B) 11b is a measurement counter (Ri) 11
It goes without saying that it may be different for each case.

Also, in the above embodiment, the upper digit is one digit, that is, it is
Although the case where it is the most significant digit has been described, it goes without saying that the case is not limited to this.

〔Effect of the invention〕

As explained above in detail, the count circuit control method of the present invention is applicable to the unit under test (Vl) and the measuring unit l-
(V2), for example, to measure a plurality of performance measurement counters provided in the unit under test (Vl) constituting a computer system, the unit under test (ν1) For example, the plurality of measurement counters (R1, R2-) provided therein are divided into the most significant digits (R1-A, R2-A, ~) and the other parts (
1?1-B, R2-8, ~), and the most significant digit of each measurement counter (R1, R2, ~) indicates the value of the measuring unit (m) during operation. V2) at a specific frequency and add it to the value in the area corresponding to each measurement counter (R1, R2, ~) in the memory (R1) in the measurement unit (V2), and VL)
After the operation of each of the above measurement counters (R1,
Read out the parts (R1-B, R2-B, ~) other than the most significant digits (R1-A, R2-A~) of R2,~), and store them on the memory (M) in the measurement unit (V2). Combined with the values of the corresponding areas above, each measurement counter (R1,
R2, ~), the number of hardware digits for each measurement counter in the unit under test is relatively small, and the upper digits built on the memory are Since it is permissible up to the size of the memory in the bit direction, very large values can be counted with the relatively small amount of hardware mentioned above. Furthermore, there is an effect that the required number of digits can be changed flexibly for each counter/measurement.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the counting circuit control method of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional count circuit control method. It is. Part (Ri-8) 11c is Banff y (Ri-C). lid is an adder (Ai) or an incrementer. 12 is a control circuit (Qi), 13 is a circuit under test (
Pi). 2 is a measurement unit (V2) or a service processor (SVP); 21 is a central processing unit (CPU); 22 is a read/write circuit (E). Reference numeral 23 indicates a storage unit (M), a local memory (M), or a memory, respectively. In the drawings, 1 indicates a unit to be measured I-(Vl) or a main unit of the computer system. 11 indicates a measurement unit. Measurement counter (Ri) 11a is the most significant digit (Ri-^) of the measurement counter (Ri).
).

Claims (1)

[Claims] Unit to be measured (V1) (1) and measuring unit (V2)
) (2), a plurality of measurement counters (R1, R2, ~) (11) provided in the unit to be measured (V1) (1) are connected to the upper digits (R1 -A, R2-A, ~) (11a) and other parts (R1-B, R2-B, ~) (11b), each measurement counter (R1, R2, ~) (11
The upper digit of ) indicates that the value during operation of the unit under test (V1) (1) is read out from the measurement unit (V2) (2) at a specific frequency, and the value in the measurement unit (V2) (2) is Each measurement counter (R1, R2) in the memory (M) (23)
, ~) (11), and after the unit under test (V1) (1) stops operating, the upper digits of each measurement counter (R1, R2, ~) (11) are added to the value of the area corresponding to (11). Read out the part (R1-B, R2-B, ~) (11b) other than (R1-A, R2-A, ~) (11a),
Memory (M) (2) in the above measurement unit (V2) (2)
3) A count circuit control method characterized by controlling the value of each measurement counter (R1, R2, -) (11) by combining it with the value of the corresponding area above.