JP2001147914A - Vector operating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vector processor, with which high-accuracy arithmetic processing is performed by reducing an error caused by exponent matching in the case of adding different exponents. SOLUTION: Concerning the vector processor provided with at least one vector register and an adder for applying total sum operating processing to vector data in the relevant vector register, this device is provided with a data relocating means for relocating vector data in the vector register, and total sum operating processing is performed by successively inputting the data relocated by the relevant data relocating means to the adder and adding the data in order from the element of a smallest key value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector operation device, and more particularly, to a vector operation device capable of performing high-precision arithmetic processing by reducing an error caused by index matching when performing a vector sum operation.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional vector operation device for performing a vector sum operation. As shown in FIG. 5, a conventional vector operation device includes a vector register 111 for storing vector data, an adder 121 for performing a sum operation,
A vector register 112 for storing the operation result. In FIG. 5, when a sum command, that is, a command word 300 is issued from a command control unit (not shown), a command word 30 is issued.
RR field 30 specifying the read register in 0
The vector data is read from the vector register 111 specified by 2 and input to the adder 121. The adder 121 performs a summation operation on the input data, and stores the final result in the vector register 112 specified by the WR field 303 that specifies the write register in the instruction word 300. The sum operation processing method in the adder 121 is as follows.

First, one vector data is read out from the vector register 111 storing the vector data every clock, and is sequentially input to the adder 121. The adder 121 is configured such that the addition result other than the final result is input to the adder 121 again and added to the vector data read from the vector register.

FIG. 6 is a schematic diagram showing the processing in the adder 121 of the vector operation device shown in FIG. For example, if the processing time in the adder 121 is four clocks, the elements read from the vector register 111 are input to the adder 21 again after four clocks and added.

Here, the vector data is represented by a1, a2, a
3, a4, a5, a7, a6, a7, a8. . . And Data a1 is stored in the vector register 1 at the first clock.
11 and is input to the addition processing 1 in the adder 121 at the second clock, where addition with the immediate value “0” is performed. The processes 2 and 3 in the adder are sequentially performed, and the result of a1 + 0 is obtained by the process 4 in the adder at the fifth clock. Then, at the next clock (6th clock), the result a
1 + 0 is input to the adder processing 1 again.

On the other hand, at the fifth clock, data a5 is read from the vector register 111. At the sixth clock, this data a5 is input to the adder processing 1, and added to the input a1 + 0 again. , A1 + a5 are performed. Similarly to the case of a1, the addition of the data a2, a3, and a4 to the immediate value 0 is performed in the adder processing (a2 + 0, a3 + 0, a4 + 0), and the result is 7,
At the eighth and ninth clocks, it is again input to the processing 1 in the adder, and a
The results of 2 + a6, a3 + a7, a4 + a8 are obtained.

Here, a1 + a5, a2 + a6, a3 +
The addition results of a7, a4 + a8 are S1, S2, S
3, S4, S1 and a9 at the 10th clock and S2 and a10, 12 at the 11th clock.
S3 and a11 at the clock, S4 and a at the 13th clock
12, S1 + a9, S2 + a10, S3 + a
11, the result of S4 + a12 is obtained.

Although there are various methods for calculating the final result, it is assumed here that the final result is obtained by the method shown in FIG. FIG. 7 shows a method of calculating the final result when the number of vector processing elements is eight. S1, S2, S3, and S4 are calculated by the method described above. At the timing when S3 is input to the in-adder processing 1, the arithmetic unit is controlled so that S1 is input to the in-adder processing 1, and S1 + S3 = S5 is calculated. Similarly, it is assumed that at the timing when S4 is input to the in-adder processing 1, the arithmetic unit is controlled so that S2 is input to the in-adder processing 1, and S2 + S4 = S6 is calculated. It is also assumed that the arithmetic unit is controlled so that S5 is input to the in-adder processing 1 at the timing when S6 is input to the in-adder processing 1, and the sum S5 + S6 is calculated.

As described above, one sum result is finally obtained, and the result is stored in the vector register 12.
Generally, the summation processing in the vector operation device is designed to speed up the processing by regressing the data in the adder as described above. When performing scalar processing, elements are usually added in element order from a1, but when processing is performed by a vector operation device, they are not added in element order.
The order of addition differs from that in scalar processing. However, it is necessary for the addition processing to perform the following index matching before the addition processing as is known.

[0010] Floating point data handled on a computer is usually represented by a hexadecimal number, and can be represented by an exponent part and a mantissa part. In addition processing, in general, in the exponent matching, the smaller exponent is adjusted to the larger exponent. Since the mantissa having the smaller exponent is shifted right by the difference between the exponents of the two data to be added, the shifted out bits are discarded. As described above, since it is necessary to perform exponent matching in the addition processing, when the exponent difference between two data to be added is large, the number of bits to be shifted out increases,
The addition result will include an error.

This error will be briefly described below by representing data handled on a computer by a decimal number. It is assumed that the number of significant digits of the adder is five digits after the decimal point, and a specific operation when the number of vector processing elements is eight will be described. a1 = 1.0000E
+00, a2 = 2.00000E + 00, a3 = 3.0
0000E + 00, a4 = 4.000000E + 00, a
5 = 500000E + 00, a6 = 1.0000E
+00, a7 = 2.00000E + 00, a8 = 1.0
Assuming that 0000E + 06, S1 to S5 which are intermediate addition results
S6 and the final result (sum) are as follows. S1 = a1 + a5 = 1.00000E + 00 + 5.00000E + 00 = 6.00000E + 00 S2 = a2 + a6 = 2.00000E + 00 + 1.00000E + 00 = 3.00000E + 00 S3 = a3 + a7 = 3.00000E + 00 + 2.00000E + 00 = 5.00000E + 00 S4 = a4 + a8 = 4.00000E + 00 + 1.00000E + 06 = 0.00000E + 06 + 1.000
00E + 06 = 1.00000E + 06 S5 = S1 + S3 = 6.00000E + 00 + 5.00000E + 00 = 1.1000E + 01 S6 = S2 + S4 = 3.00000E + 00 + 1.00000E + 06 = 0.00000E + 06 + 1.000
00E + 06 = 1.00000E + 06 Total = S5 + S6 = 1.10000E + 01 + 1.00000E + 06 = 0.00001E + 06 + 1.0
0000E + 06 = 1.00001E + 06 The final result of the summation processing is 1.00001E + 06.

When a similar calculation is processed by a scalar, a
Since the elements are added in order from 1 to a8 in element order, the final result (sum) is as follows. a1 + a2 = 1.00000E + 00 + 2.00000E + 00 = 3.00000E + 00 ... S1 S1 + a3 = 3.00000E + 00 + 3.00000E + 00 = 6.00000E + 00 ... S2 S2 + a4 = 6.00000E + 00 + 4.00000 E + 00 = 1.00000E + 01 ... S3 S3 + a5 = 3.00000E + 01 + 5.00000E + 00 = 1.50000E + 01 ... S4 S4 + a6 = 3.00000E + 01 + 1.00000E + 00 = 1.60000E + 01 ... S5 S5 + a7 = 1.60000E + 01 + 2.00000E + 00 = 1.80000E + 01 ... S6 S6 + a8 = 1.80000E + 01 + 1.00000E + 06 = 1.00002E + 06 ... summation Although it depends on the input data, The final sum result may change between vector processing and scalar processing depending on the addition order.

[0013]

However, when the sum processing result differs between the scalar processing and the vector processing, the result of the scalar processing is considered to be correct in most cases. This is because, in the program, the addition is performed in the order of the elements, so that an error generated by exponent matching at the time of scalar processing is inevitable. As described above, when the sum processing results are different, it is possible to perform the scalar processing only in the portion of the program source where the sum processing occurs. However, in this case, there is a problem in that the processing time is slow because a portion that can be processed by the vector operation is dared to be processed by the scalar.

Further, when a higher precision operation result is required than at the time of scalar processing, the elements to be processed are rearranged in ascending order, and then the processing is performed by scalar, thereby making it possible to reduce errors due to index matching and the like. Become. However, in this case, a program source for rearranging the processing elements is required, which requires labor and reduces processing time.

As described above, in the vector operation processing,
The order of addition at the time of summation processing is different from that at the time of scalar processing because the speed of the summation processing is increased.However, with a conventional vector operation device, the addition order cannot be changed at the time of vector summation processing. Depending on the data to be processed, there is a problem that the accuracy of the sum result of the vector processing is inferior to the sum result of the scalar processing. Further, since there is no means for rearranging the input data, a calculation result with higher precision than that performed by the scalar processing cannot be expected.

The present invention has been made in order to solve the above-mentioned problem. A vector which can obtain a high-accuracy summation processing result by rearranging input data in ascending order during vector summation processing and further performing addition in element order. It is an object to provide an arithmetic device.

[0017]

In order to solve the above-mentioned problems, a vector operation device according to the present invention comprises a vector having at least one vector register and an adder for performing a sum operation on vector data in the vector register. In the processing device, data rearranging means for rearranging vector data in the vector register, and the data rearranged by the data rearranging means are sequentially input to the adder, and the data is added in the order of the element having the smallest key value. It is characterized in that the summation processing is performed.

With this configuration, the addition process can be performed in the order of small data, so that an error generated by index matching can be suppressed.
Therefore, a highly accurate summation processing result can be obtained.

Further, in the vector operation device according to the present invention, the data rearranging unit may rearrange the vector data, a data storing unit storing the data rearranged by the data sorting unit, and the data storing unit. And a data read timing instructing means for reading out the vector data stored in the adder at a predetermined timing and sending the read out data to the adder.

Further, in the vector operation device according to the present invention, the adder is configured such that an intermediate addition result other than the final addition result is input to the adder again, and the data read timing instructing means includes: Is input to the adder again, and at the same time, the next element is read from the data storage means and instructed to be input to the adder.

With this configuration, the vector data can be rearranged, and thereafter, the data can be read out and sent to the adder in synchronization with a predetermined timing, particularly, the operation timing of the adder. It is possible to execute a simple summation processing.

Further, the vector operation device of the present invention sends the vector data in the vector register directly to the adder, and sends the vector data to the adder via the data rearranging means. A second data line; and a data supply switching unit for switching a vector data supply line to the adder between the first data line and the second data line.

As described above, when it is not necessary to rearrange the vector data, the data can be added in the same order, so that an appropriate adding process according to the case can be performed.

Further, the vector operation device according to the present invention is characterized in that the rearrangement of the vector data is performed in ascending order.

As described above, by rearranging the vector data in ascending order, the addition process can be performed in ascending order of data, so that an error generated by index matching can be reduced.

Further, the vector operation device according to the present invention is characterized in that an instruction signal as to whether or not to perform the rearrangement processing of the vector data is set in an instruction word created by a compiler.

Further, the vector operation device according to the present invention is characterized in that an instruction signal as to whether or not the rearrangement processing of the vector data is performed is set in a process state word.

With this configuration, the program executor can rearrange the data in ascending order only at an arbitrary position in the ascending order, so that the execution time of the entire program can be highly accurate without extremely slowing down. Can get results

Further, the vector operation device of the present invention specifies a part of the summation operation performed in the operation device,
A vector summation process is performed on the designated portion via the rearranging means.

With this configuration, it is possible to execute a high-accuracy summation processing without extremely delaying the execution time of the entire program.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A vector processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of the first exemplary embodiment of the present invention. The vector processing device of the present invention includes a vector register 11 for storing vector data, an adder 21 for processing a summation operation,
The apparatus includes an input switching unit 30 for switching whether or not to rearrange vector data, a data rearranging unit 40 for rearranging vector data in ascending order, and a vector register 12 for storing an operation result.

The input switching means 30 directly inputs the vector data read from the vector register 11 to the adder 21 in accordance with the data sort instruction signal 50,
Alternatively, whether to supply the data to the adder 21 via the data rearranging means 40 is switched. The data rearranging means 40
It comprises a data sorting means 41, a data storage means 42, and a read timing control means 43. The data sorting unit 41 rearranges the vector data of a plurality of elements transmitted through the input switching unit 30 in ascending order, and stores the result in the data storage unit 42. The vector data in the data storage means 42 is read by the read timing instructing means 43 and then supplied to the adder 21. The read timing instructing means 43 instructs the timing of reading each vector data from the data storage means 42. The timing is determined by the processing time in the adder 21, and the result of addition of the preceding element is input to the adder 21. At the same time, the next element is read out from the data storage means 42 and instructed to be input to the adder 21. still,
The adder 21 inputs the intermediate result other than the final operation result to the adder 21 again, and stores only the final result in the vector register 1.
2 is stored.

FIG. 2 is a diagram showing instruction words in the vector processing device of the present invention. In instruction 100, OP
A field 101 indicates an operation code indicating an instruction, an RR field 103 specifies a vector register from which data is read, and a WR field 104 specifies a vector register into which an operation result is written. The sort instruction bit 102 is a bit for specifying whether input data should be rearranged in ascending order or normal summation processing should be performed without rearrangement.

When performing the normal summation processing without rearranging the data, the source instruction bit 102 is set to "0".
In order to rearrange the input data, "1" is specified. This bit designates “0” or “1” when the compiler generates an instruction word. If a compiler instruction line is written in a part of the program, the rearrangement is performed only for the sum operation instruction in only the specified part. On the other hand, in the case of specifying by a compile option or the like, the rearrangement can be performed for all the sum operation instructions in the program. When the sort instruction bit 102 is "0", the data sort instruction signal 50 shown in FIG. 1 becomes "0", and normal summation processing is performed. When the sort instruction bit 102 is "1", the sort The instruction signal becomes "1", the data is rearranged, and the arithmetic processing is executed.

In the above-described embodiment, the sort instruction signal 50 is determined by the sort instruction bit in the instruction word 100. However, for example, the process state word 2 shown in FIG.
A sort instruction signal may be provided in 00, set as an initial setting value of HW, and targeted for the previous sum operation instruction.

Next, the flow of the operation of the vector processing apparatus according to the present invention will be described with reference to FIGS. In FIG. 1, when a sum operation instruction is issued from an instruction control unit (not shown), a vector register 11 is specified by an RR field 103 in an instruction word 100 (see FIG. 2), and vector data is read from this register. It is. Next, when the data sort instruction signal 50 is “0”, the data switching means 30
The data rate is switched so that the vector data read from 1 is directly input to the adder 21. on the other hand,
When the data sort instruction signal 50 is "1", the route is switched to the data rearrangement means 40, and the vector data is input to the data rearrangement means 40.

When the data sort signal 50 is "1",
The vector data from the vector register 11 is sent to the data sorting means 40, and the data sorting means 41 sorts the data of a plurality of elements in ascending order. This result is stored in the data storage means 42. The data is read from the data storage means 42 according to the timing signal to the read timing instructing means 43, and is input to the adder 21. The timing at which the read timing means 43 reads the vector data is determined by the processing time in the adder 21,
At the same time as the result of addition of the preceding element is input to the adder 21, the next element is read from the data storage means 42 and input to the adder 21. Intermediate results other than the final result in the adder 21 are input to the adder 21 again, and only the final result is sent to the vector register designated by the WR field 104 in the instruction word 100, in this case, the vector register 12,
Is stored.

When the data sort signal 50 is "0", that is, when the vector data read from the vector register 11 is directly input to the adder 21, it is the same as the conventional summation processing, and the description is omitted here. I do. The addition method in the floating point addition in the adder 21 is as follows.
Since it is publicly known, description thereof is omitted here.

Next, referring to FIG.
The processing operation in the adder 21 according to the present invention when “1” is “1” will be described in detail. Here, assuming that the processing time in the adder 21 is 4 clocks, the data rearranged by the data rearranging means 40 in the ascending order is A1, A2, A3, A
4. . . And

As shown in FIG. 4, at the clock 1, the first element (A1) is read from the data storage means 42,
At the next clock 2, it is input to the in-adder processing 1. At this time, the adder 21 adds A1 to the immediate value “0”. Next, after the processes 2 and 3 in the adder, the result of A1 + 0 is obtained in the process 4 in the adder at the fifth clock. This result is input to the in-adder processing 1 again at the next clock (the sixth clock). Since it is possible to predict in advance that the result of A1 + 0 is input to the in-adder processing 1 at the sixth clock, the read timing instructing means 43 reads A2 from the data storage means 42 at the fifth clock,
At the sixth clock, the next element (A2) is input to the processing 1 in the adder. That is, the read timing instruction means 43 reads data from the data storage means 42 every four clocks.

As shown in FIG. 4, at the sixth clock, A1 + A2 (= S1) is obtained in the processing 1 in the adder. Similarly, at the ninth clock, the third element (A3) is read from the data storage means 42, and at the tenth clock, S1 and A3 are input to the in-adder processing 1, and the in-adder processing 2, 3 are performed. After the 13th clock, S1 + A3 (= S2)
Is calculated. Thus, the data sorting means 41
The summation process is performed by adding the vector data rearranged in ascending order in ascending order of the data, and the finally calculated sum is stored in the vector register 12.

[0042]

As described above, according to the vector processing apparatus of the present invention, after the vector data to be subjected to the summation processing are rearranged in ascending order, the addition processing can be performed in ascending order of the data. Error can be suppressed. Therefore, a highly accurate calculation result can be obtained.

Further, since the program executor can rearrange the data and perform the arithmetic processing only for the summation processing at an arbitrary position, a high-precision processing can be performed without extremely delaying the execution time of the entire program. The result can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a vector operation device according to the present invention.

FIG. 2 is a diagram showing an instruction word in the vector operation device of the present invention.

FIG. 3 is a diagram showing a process state word in the vector operation device of the present invention.

FIG. 4 is a diagram showing a processing operation in an adder of the vector operation device according to the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional vector operation device.

FIG. 6 is a diagram showing a processing operation in an adder of a conventional vector operation device.

FIG. 7 is a diagram showing another processing operation in the adder of the conventional vector operation device.

[Explanation of symbols]

 11, 12, 111, 112 Vector register 21, 121 Adder 30 Input switching means 40 Data rearranging means 41 Data sorting means 42 Data storage means 43 Read timing instructing means 50 Data sort signal 100 Command word 101, 301 OP field 102 Sort instruction Bit 103, 303 RR field 104, 304 WR field 200 Process status word 201 Sort instruction bit 300 Command word

Claims (8)

[Claims] 1. At least one vector register,
In a vector processing device comprising an adder for performing a sum operation on the vector data in the vector register, a data rearranging unit for rearranging the vector data in the vector register, and adding the data rearranged by the data rearranging unit to the adder. A vector operation device for sequentially inputting the data to the elements and adding the data in the order of the element having the smallest key value to perform the summation processing. 2. The vector operation device according to claim 1, wherein the data rearranging unit is a data sorting unit that rearranges the vector data, a data storage unit that stores the data rearranged by the data sorting unit, A vector operation device comprising: a data read timing instructing unit that reads out vector data stored in a data storage unit at a predetermined timing and sends the data to the adder. 3. The vector operation device according to claim 1, wherein the adder is configured such that an intermediate addition result other than the final addition result is input to the adder again, and the data read timing is set. A vector operation device, wherein an instruction means instructs to read out the next element from the data storage means and to input the next element to the adder at the same time that the addition result of the preceding element is input to the adder again. 4. The vector operation device according to claim 1, wherein a first data line for directly sending vector data in the vector register to the adder, and the vector rearrangement means for reordering the vector data. And a second data line for sending the vector data to the adder through the data supply switching means for switching a supply line of vector data to the adder between the first data line and the second data line. A vector operation device, comprising: 5. The vector operation device according to claim 1, wherein the rearrangement of the vector data is performed in ascending order. 6. The vector operation device according to claim 1, wherein an instruction signal as to whether or not the vector data is rearranged is set in an instruction word created by a compiler. A vector operation device characterized by the above-mentioned. 7. The vector operation device according to claim 1, wherein an instruction signal indicating whether or not to perform the rearrangement processing of the vector data is set in a process state word. Vector arithmetic unit. 8. The vector operation device according to claim 1, wherein a part of a summation operation performed in the operation device is specified, and the rearrangement unit performs processing on the specified portion. A vector operation device, wherein a vector sum operation process is performed via a computer.