JPH02142170A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH02142170A JPH02142170A JP63296826A JP29682688A JPH02142170A JP H02142170 A JPH02142170 A JP H02142170A JP 63296826 A JP63296826 A JP 63296826A JP 29682688 A JP29682688 A JP 29682688A JP H02142170 A JPH02142170 A JP H02142170A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- cooling element
- heat
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000001816 cooling Methods 0.000 claims abstract description 25
- 230000005855 radiation Effects 0.000 abstract description 2
- 230000017525 heat dissipation Effects 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 3
- 230000005679 Peltier effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［８Ｉ要〕
半導体装置用パッケージの改良に関し、放熱能力を増大
し、しかも、半導体装置の消費電力が増大しても、同一
のパンケージで対応することを可能にする半導体装置用
パンケージを提供することを目的とし、
冷却面が被収容半導体装置に対接して設けられ、前記の
被収容半導体装置の電源線と直列に接続されるペルチェ
冷却素子を有するように構成する。[Detailed Description of the Invention] [Required 8I] Regarding the improvement of packages for semiconductor devices, a semiconductor that increases heat dissipation capacity and allows the same package to cope with increased power consumption of semiconductor devices. The object of the present invention is to provide a pancage for a device, the cooling surface of which is provided in opposition to a semiconductor device to be accommodated, and is configured to have a Peltier cooling element connected in series with the power supply line of the semiconductor device to be accommodated.
本発明は、半導体装置用パッケージの改良に関する。ｖ
ｊ−に、半導体装置用パッケージの放熱特性を向上する
改良に関する。The present invention relates to improvements in packages for semiconductor devices. v
j-, the present invention relates to an improvement for improving the heat dissipation characteristics of a package for a semiconductor device.
半導体装置用パンケージとは、半導体素子を物理的、化
学的、機能的に保護し、信頼性を向上させる目的で、外
部の環境条件から気密封止する容器であって、セラミッ
クパッケージ、プラスチンクパッケージ等があるが、半
導体装置の大型化とともに、その放熱能力を増大する必
要性が益々増大してきている。A semiconductor device pancage is a container that is hermetically sealed from external environmental conditions for the purpose of physically, chemically, and functionally protecting semiconductor elements and improving reliability, and includes ceramic packages and plastic packages. However, as the size of semiconductor devices increases, the need to increase their heat dissipation capacity is increasing.
〔発明が解決しようとする課題］
放熱能力を増大するのに、伝統的には、比較的大きな金
属塊等をもって構成されるヒーＩ・シンクを使用するか
、さらに、このヒートシンクにフィンを付加する等の手
法が使用されていたが、さらに放熱能力の大きな半導体
装置用パッケージの開発が望まれていた。また、従来は
、消費電力の大きい半導体装置を開発するごとに、それ
に見合う放熱能力のあるパッケージを新たに開発しなけ
ればならず、経済的負担が大きかった。[Problems to be Solved by the Invention] Traditionally, heat dissipation capacity has been increased by using a heat sink made of a relatively large metal block or by adding fins to the heat sink. However, there was a desire to develop a package for semiconductor devices with even greater heat dissipation capacity. Furthermore, conventionally, each time a semiconductor device with large power consumption was developed, a new package with a corresponding heat dissipation capacity had to be developed, which caused a heavy economic burden.
本発明の目的は、これらの欠点を解消することにあり、
放熱能力を増大し、しかも、半導体装置の消費電力が増
大しても、同一のパッケージで対応することを可能にす
る半導体装置用パッケージを提供することにある。The purpose of the present invention is to eliminate these drawbacks,
It is an object of the present invention to provide a package for a semiconductor device that has increased heat dissipation capability and can cope with an increase in power consumption of the semiconductor device using the same package.
上記の目的は、冷却面が被収容半導体装置（２）に対接
して設けられ、前記の被収容半導体装置（２）の電源線
と直列に接続されてなるペルチェ冷却素子（５）を有す
る半導体装置用パンケージによって達成される。The above object is to provide a semiconductor device having a Peltier cooling element (5) whose cooling surface is provided facing the accommodated semiconductor device (2) and connected in series with the power supply line of the accommodated semiconductor device (2). This is accomplished by a device pancage.
本発明に係る半導体装置用パッケージにおいては、ペル
チェ効果を使用したペルチェ素子を積極的に利用したも
のである。In the semiconductor device package according to the present invention, a Peltier element using the Peltier effect is actively utilized.
第４図参照
ペルチェ素子とは、例えば、Ｎ型半導体に第４図に示す
ように直流電流を流すと、電流が流入する側では発熱が
起り、電流が流出する側では熱の吸収が起るという現象
、すなわち、’ｌ流が流出する例の熱が電流の流入する
側に移送されるというペルチェ効果を利用するものであ
る。電流の流出側電極を半導体装置用パッケージに収容
される半導体装置に対接して設け、電流の流入側電極を
半導体装置用パッケージの外壁側に設ければ、半導体装
置の発生ずる熱がペルチェ素子によって半導体装置用パ
ッケージの外壁側に強制的に移送されるので、放熱能力
が増大、する。Refer to Figure 4 A Peltier element is, for example, when a direct current is passed through an N-type semiconductor as shown in Figure 4, heat is generated on the side where the current flows in, and heat is absorbed on the side where the current flows out. This phenomenon utilizes the Peltier effect, in which heat in the case where the current flows out is transferred to the side where the current flows. If the current outflow side electrode is provided opposite to the semiconductor device housed in the semiconductor device package, and the current inflow side electrode is provided on the outer wall side of the semiconductor device package, the heat generated by the semiconductor device can be absorbed by the Peltier element. Since the heat is forcibly transferred to the outer wall side of the semiconductor device package, the heat dissipation capacity increases.
半導体装置内において発生する熱をＰ、放熱廿をＣとす
ると、半導体装置の温度上昇ΔＴは、ΔＴ＝Ｋ （Ｐ−
Ｃ） ・・・・・・・・ （１）となる、こ−でＫは
比例定数である。If the heat generated in the semiconductor device is P and the heat radiation is C, then the temperature rise ΔT of the semiconductor device is ΔT=K (P−
C) ...... (1), where K is a proportionality constant.
電源電圧を■、電源電流を１とすると、発熱噴Ｐは、
Ｐ＝１ ・ ■
となる。ペルチェ冷却素子による放熱ｍｃと電源電流■
との間には、
Ｃ＝Ａ・■
の関係がある。ご−でＡは比例定数である。When the power supply voltage is 1 and the power supply current is 1, the exothermic jet P is P=1.2. Heat dissipation MC and power supply current by Peltier cooling element ■
There is a relationship between C=A・■. A is a constant of proportionality.
したがって第（１）式は、次のように変（＾できる。Therefore, equation (1) can be changed as follows.
ΔＴ＝Ｋ （１−Ｖ−Ａ ・Ｉ） ＝Ｋ （Ｖ−Ａ）
１ベルチエ冷却素子の比例定数へを電＃電圧■に近づ
けることにより、温度上昇ΔＴを０に近づけることがで
きる。すなわち、消費電力の異なる半導体装置を実装し
ても、半導体装置の温度上昇を常に０に近づけることが
可能である。ΔT=K (1-V-A ・I) =K (V-A)
1 By bringing the proportionality constant of the Bertier cooling element closer to the voltage (2), the temperature rise ΔT can be brought closer to 0. That is, even if semiconductor devices with different power consumptions are mounted, the temperature rise of the semiconductor devices can always be kept close to zero.
なお、Ｐ型半導体よりなるペルチェ素子を使用する場合
には、電流の流入側において熱の吸収が起るので、電流
の流入側電極を半導体装置に対接して設ければよい。Note that when a Peltier element made of a P-type semiconductor is used, since heat absorption occurs on the current inflow side, the current inflow side electrode may be provided opposite to the semiconductor device.
以下、図面を参照しつ一１本発明の三つの実施例に係る
半導体装置用パンケージについて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, three embodiments of the present invention will be described with reference to the drawings.
勇−し桝
第１図参照
第１図において、１はセラミンク、プラスチック等のパ
ッケージであり、２は半導体装置であり、３は電源用そ
の他のビンであり、４はボンディングワイヤであり、５
は例えばＮ型のペルチェ冷却素子である。この例では、
ペルチェ冷却素子５を一番電位の低い電源ピン３１に接
続する場合を示している。一番電位の、Ｗい電源ピン３
２から供給される′Ｗｌ源電流電流導体装置２に供給さ
れた後、ペルチェ冷却素子５の、パッケージｌの外壁側
に配設された電極から流入し、半導体装置２に対接する
電極から流出し、一番電位の低い電源ピン３１へ流れる
。Ｎ型のペルチェ冷却素子を使用する場合には、電流の
流出する側の熱が吸収され、電流の流入する側で放熱さ
れるので、半導体装置において発生する熱が強制的にパ
ッケージの外側に移送されて放熱能力が増大する。Refer to Figure 1 of Yushimasu In Figure 1, 1 is a package made of ceramic, plastic, etc., 2 is a semiconductor device, 3 is a power supply and other bottles, 4 is a bonding wire, and 5 is a package made of ceramic or plastic.
is, for example, an N-type Peltier cooling element. In this example,
A case is shown in which the Peltier cooling element 5 is connected to the power supply pin 31 having the lowest potential. The highest potential, W power supply pin 3
After being supplied to the current conductor device 2, the current flows into the Peltier cooling element 5 from the electrode disposed on the outer wall side of the package l, and flows out from the electrode facing the semiconductor device 2. , flows to the power supply pin 31 with the lowest potential. When using an N-type Peltier cooling element, heat is absorbed on the side where the current flows out and heat is radiated on the side where the current flows in, so the heat generated in the semiconductor device is forcibly transferred to the outside of the package. heat dissipation capacity increases.
］」１舛
第２図参照
Ｐ型のペルチェ冷却素子を使用する場合を第２図に示す
、この場合、Ｐ型のペルチェ冷却素子５の電流の流入側
電極と流出側電極とを第１例とは反対に配設する。1. Refer to Figure 2. Figure 2 shows a case where a P-type Peltier cooling element is used. Place it opposite to.
ｍｌ
第３図参照
ペルチェ冷却素子５を一番電位の高い電源ピン３２に接
続する場合を第３図に示す。ml See FIG. 3 FIG. 3 shows a case where the Peltier cooling element 5 is connected to the power supply pin 32 having the highest potential.
以上説明せるとおり、本発明に係る半導体装置用パッケ
ージにおいては、ペルチェ冷却素子が、その冷却面が被
収容半導体装置に対接して設けられ、被収容半導体装置
のｔ流線と直列に接続されるので、半導体装置の発生す
る熱がペルチェ冷却素子によって強制的にパッケージの
外壁側に移送され放熱されるので、放熱能力が増大し、
また、電源電流が増大して半導体装置の発熱量が増大し
ても、ペルチェ冷却素子による放熱量も電源電流に比例
して増大するので半導体装置の温度上昇は一定となり、
同一のパッケージを使用することができ経済的利益が大
きい。As explained above, in the semiconductor device package according to the present invention, the Peltier cooling element is provided with its cooling surface facing the accommodated semiconductor device, and is connected in series with the t-flow line of the accommodated semiconductor device. Therefore, the heat generated by the semiconductor device is forcibly transferred to the outer wall of the package and radiated by the Peltier cooling element, increasing the heat radiating capacity.
Furthermore, even if the power supply current increases and the amount of heat generated by the semiconductor device increases, the amount of heat dissipated by the Peltier cooling element also increases in proportion to the power supply current, so the temperature rise of the semiconductor device remains constant.
The same package can be used, which has great economic benefits.
第１図、第２図、第３図は、本発明の三つの実施例に係
る半導体装置用パッケージの構成図である。
第４図は、ペルチェ冷却素子の原理説明図である。
パッケージ、
半導体装置、
ビン、
一番電位の低い電源ピン、
一番電位の高い電源ピン、
ボンディングワイヤ、
ペルチェ冷却素子。1, 2, and 3 are configuration diagrams of packages for semiconductor devices according to three embodiments of the present invention. FIG. 4 is an explanatory diagram of the principle of the Peltier cooling element. Packages, semiconductor devices, bottles, lowest potential power pins, highest potential power pins, bonding wires, Peltier cooling elements.
Claims (1)
前記被収容半導体装置（２）の電源線と直列に接続され
てなるペルチェ冷却素子（５）を有する ことを特徴とする半導体装置用パッケージ。[Claims] A cooling surface is provided facing the accommodated semiconductor device (2),
A package for a semiconductor device, comprising a Peltier cooling element (5) connected in series with the power supply line of the semiconductor device to be accommodated (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63296826A JPH02142170A (en) | 1988-11-22 | 1988-11-22 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63296826A JPH02142170A (en) | 1988-11-22 | 1988-11-22 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02142170A true JPH02142170A (en) | 1990-05-31 |
Family
ID=17838659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63296826A Pending JPH02142170A (en) | 1988-11-22 | 1988-11-22 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02142170A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7022553B2 (en) * | 1998-08-31 | 2006-04-04 | Micron Technology, Inc. | Compact system module with built-in thermoelectric cooling |
| US7268019B2 (en) | 2004-09-22 | 2007-09-11 | Halliburton Energy Services, Inc. | Method and apparatus for high temperature operation of electronics |
-
1988
- 1988-11-22 JP JP63296826A patent/JPH02142170A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7022553B2 (en) * | 1998-08-31 | 2006-04-04 | Micron Technology, Inc. | Compact system module with built-in thermoelectric cooling |
| US7268019B2 (en) | 2004-09-22 | 2007-09-11 | Halliburton Energy Services, Inc. | Method and apparatus for high temperature operation of electronics |
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