JPH02141885A - Microcomputer - Google Patents

Abstract

PURPOSE:To freely select the memory macro by controlling an interface circuit by a memory address discriminating signal allocated to each memory device. CONSTITUTION:Plural kinds of function blocks (CPU blocks) 301 having a central processor 300 and memory blocks 102 containing a memory device whose function and capacity are different are prepared, and arbitrary ones in the CPU blocks and the memory blocks 102 are combined. In this case, the memory blocks 102 contains a discriminating circuit 105 for discriminating a memory address allocated to the memory device and generating a discriminating signal 108, and also, the CPU block 301 exchanges data with the outside of this CPU block 301. An interface circuit 304 and an input terminal 100 of the discriminating signal 108 are provided, and this interface circuit 304 is controlled by the discriminating signal 108. In such a way, a memory macro 102 can be selected freely.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to functional blocks and memory blocks including a central processing unit (hereinafter referred to as CPU) and various peripheral hardware;
Regarding microcomputers that are developed by connecting layout data of functional blocks composed of user-defined circuits and user-defined circuits on a computer, in particular, we prepare multiple types of each of the above functional blocks, and The present invention relates to a microcomputer in which mask data is created and developed by registering corresponding layout data as a database on a computer, selecting necessary data from these databases, and connecting them on the computer.

[Conventional technology]

In recent years, with the progress of semiconductor technology, the field of application of microcomputers has been rapidly expanding, and at the same time, the requirements for each field of application have continued to become more diverse.

A production system for designing and commercializing semiconductor integrated circuits such as microcomputers in a short period of time that completely satisfies user requirements has currently been developed as a gate array, and has already achieved many results.

Furthermore, a new method called the megacell method has been developed as a method having higher functionality and higher degree of integration.

In this method, the layout information of each functional block such as the CPU, memory, timer, A/D converter, serial interface, etc. is registered in the computer as a database called macro information, and the connection diagram of this macro information created by the user is stored in the computer. The final mask information is created by connecting these macro information in a computer based on the above information. The feature of this method is that the engineering C manufacturer prepares a wide variety of functional blocks such as timers, memories, A/D converters, and serial interfaces, and the user can freely select the functional blocks as needed. The purpose is to create mask information for an integrated circuit within a short period of time, thereby allowing the user to complete development of the desired integrated circuit within a short period of time.

Among these, regarding memory macros, in order to respond to various memory capacity requests from users, IC manufacturers prepare multiple types of memory macros with different capacities in advance, and users can choose from among these memory macros to create their own system. The macro with the optimal capacity is selected.

FIG. 3 shows a block diagram of a conventional single-chip microcomputer with built-in memory. In this conventional example, the C
Only the PU core macro and memory macro are illustrated, and other functional blocks such as a timer are omitted.

The CPU core macro 301 includes a CPU 300, a host 303 for interfacing with the outside of the chip, a macro interface circuit 304, and an address discrimination circuit 305.
They are interconnected by an address bus 306 and a data bus 307. Further, a memory macro 302 is connected to the outside of the CPU core macro 301 via a macro interface circuit 304.

The CPU 300 outputs the memory reference address onto the address bus 306, activates the write signal 309 during write processing, and synchronizes the data bus 30 with the same timing.
Outputs data on 7, and outputs read signal 31 during read processing.
0 is made active and the data on the data bus 307 is taken into the CPU 300 in synchronization with the same timing. The port 303 is an interface circuit block used when the CPU 300 refers to an external device such as a memory set outside this chip.The address bus 306 has an output driver 303-1, and the data bus 307 has a bidirectional buffer. 303-2, write signal 309 and read signal 310
Output drivers 303-3 and 303-4 are respectively set for the external address bus 311 and external data bus 312 for devices outside the chip (not shown in this conventional example) under the control of an address discrimination signal 308, which will be described later. In addition, an external write signal 313 and an external read signal 314 are output. The macro interface circuit 304 is
This is an ink face circuit for exchanging data with macros set outside the core macro 301. Address bus 3
06 has an output driver 304-1. data bus 307
a bidirectional buffer 304-2, and an output driver 304-3 for the write signal 309 and read signal 310, respectively.
04-4 is set, and the address discrimination signal 30 is set like the port.
8 outputs a macro address bus 315, a macro data bus 316, a macro write signal 317, and a macro read signal 318 to the macro cells on the chip. Address discrimination circuit 305 discriminates reference address information on address bus 306, and activates address discrimination signal 308 when memory macro 302 inside the chip is the reference target.

In general, in the megacell system, the user can freely select the macrocell, and the memory macro can also be selected from a plurality of macros with different capacities. However, if the address discrimination conditions of the address discrimination circuit 305 described above are fixed, the memory macros 30 with different memory capacities
It is necessary to change the address discrimination circuit 305 in the CPU core macro 301 every time the memory macro 3 is connected.
This becomes a major obstacle when freely selecting and setting 02.

[Problem to be solved by the invention]

As explained above, the capacity differs like memory macros,
ff SCREEN ROM When another functional block is connected, the conventional circuit has the drawback that the problem of changing the address discrimination circuit in the CPU core arises, which becomes a major obstacle to the free selection of the macrocell.

[Means to solve the problem]

A microcomputer according to the present invention includes a functional block having at least a central processing unit (hereinafter referred to as a CPU block) and a plurality of types of memory blocks including memory devices with different functions and capacities, and a CPU block and a plurality of types of memory. It is developed by combining arbitrary blocks.

At this time, the memory block includes a determination circuit that determines the memory address to be allocated to the memory device and generates a determination signal, and also includes an interface circuit for exchanging data with the outside of the CPU block and an input terminal for the determination signal. A major feature is that this interface circuit is controlled by a discrimination signal.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a block diagram of a first embodiment of the present invention. In this embodiment, the address discrimination circuit is not set in the CPU core, but is provided in the memory macro side, and a discrimination signal is generated within the macro according to the difference in memory capacity, and the CPU
Send to core. In this embodiment, like the conventional example, only a CPU core macro including a CPU and a memory macro are illustrated, and other functional blocks are omitted.

The CPU core macro 101 includes a port 3o3 for interfacing with the outside of the CPU 30o1 chip, and a macro interface circuit 304 to be described later, and an address bus 30.
6 and a data bus 307. Also,
A memory macro 102 is connected to the outside of the CPU core macro 101 via a macro interface circuit 304.

CPU: ff7ffri I: cPU3oo in +101
Since this function is the same as that explained in the conventional example, detailed explanation will be omitted. The CPU core macro 101 has an input terminal 110 (hereinafter referred to as a discrimination signal input terminal) for an address discrimination signal 108 output from a memory macro 102, which will be described later.
04 is enabled. The operations of the port 303 for interface with the outside of the chip and the macro interface circuit 3o4 are the same as those described in the conventional example, except that the source of the address discrimination signal 1080 input to each is different from the conventional example. Further explanation will be omitted.

The memory micro 102 based on the present invention includes an address discrimination circuit 105 in addition to memory cells (not shown in this embodiment), and constantly determines whether the address is its own based on the address information output on the address bus 306. If the address is determined to be one's own address, the address determination signal 108 is activated. In the first embodiment, even if a memory macro 102 having an arbitrary memory capacity is connected, address discrimination processing is performed on the memory macro 102 side, so even when changing the type of memory macro 102, the CPU core macro 1
There is no need to change the circuit configuration of any hardware including 01.

Next, a second embodiment of the present invention will be described with reference to the block diagram of FIG. Similarly to the first embodiment, the second embodiment also has C
Only a CPU core including a PU and a memory macro are illustrated, and other functional blocks are omitted.

The second embodiment has a similar configuration to the first embodiment, but three types of memory macros, a mask ROM macro 202-1, a RAM macro 202-2, and an EEROM macro 202-3, are connected as memory macros, and each memory Macros can be connected with any capacity.

The configuration of the CPU core macro 201 is that the discrimination signal input terminal is 210-1.210-2.210-3 for each memory macro.
Since this embodiment is the same as the first embodiment except that it requires the power of three people, detailed connections will be omitted. Note that the three types of discrimination signals are connected to the port 303 and the macro interface 304 via the logical OR gate 220. In the second embodiment, by considering the type of memory to be connected in advance, each memory macro 2
Memory of any capacity can be connected without depending on the capacity or type of 02.

〔Effect of the invention〕

As explained above, according to the present invention, by setting the address discrimination function on the memory macro side, there is no need to change the logic circuit in the CPU core macro, and it is possible to freely set a memory macro of any capacity. It is. Furthermore, mask ROM% RAM.

By setting address discrimination signal inputs for the types of memories that can be connected in advance, such as EEFROM, in the CPU core macro, arbitrary memory macros can be connected without setting any additional circuits between the macros.

When the present invention is applied to a megacell system, the chip size can be reduced by reducing the additional circuits as described above, and the CPU
It is expected that the development period will be shortened because the core macro can be used as is without any circuit changes, and the practical effects are very high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment based on the present invention, and FIG. 3 is a block diagram of a conventional example. 300...CPU, 301,201,101・
...CPU core macro, 302,102 old...
Memory macro, 303...Po), 304...
...Macro interface L 305,105
... Address discrimination circuit, 306 ... Address bus, 307 ... Group data bus, 309 ...
...Write signal, 310...Read signal, 3
03-1,303-3,303-4.304-1,30
4-3, 304-4... Output driver, 303
-2,304-2...Bidirectional buffer, 308
...Address discrimination signal, 311...External address bus, 312...External data bus,
313...External write signal, 314...
・External read signal, 315... Macro address bus, 316... Macro data bus, 317
- Old: Macro write signal, 318: Macro read signal, 108: Address determination signal,
110,210-1.210-2,210-3...
...Discrimination signal input terminal, 202-1...Mask ROM macro, 202-2...RAM macro,
202-3...EEPROM macro, 220.
...Logic OR gate. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] At least, by combining a functional block having a central processing unit (hereinafter referred to as a CPU block) with any memory block among multiple types of functional blocks consisting of memory devices with different functions and capacities (hereinafter referred to as a memory block). In the microcomputer to be developed, the plurality of types of memory blocks include a determination circuit that determines in advance a memory address to be allocated to each of the memory devices and generates a determination signal, and the CPU block includes a determination circuit that generates a determination signal. 1. A microcomputer comprising: an interface circuit for exchanging data with a computer; and an input circuit for the discrimination signal, the interface circuit being controlled by the discrimination signal.