JPH02141197A - Input output channel connection controller - Google Patents

Abstract

PURPOSE:To relieve load on a software and to simplify the circuit constitution of a synchronizing means by outputting a connection control data from a data supply means in a prescribed order and giving a latch timing signal to each register in order from a synchronizing means in matching with the sequence. CONSTITUTION:A processor gives an output selection data Dout in the order of register R1 R2 R3. Then an enable signal of a shift register 6 is set to input a clock signal CLK synchronously with the revision of the output channel selection data Dout to the shift register 6 via an inverter 7. As shown in figure, while the data Dout to be given to the register R1 is outputted, a latch timing signal T1 is generated from the shift register 6. That is, the shift register 6 acts like a synchronizing means and the data Dout to be given in order is latched in order to prescribed register R1-R3 and switches S11-S34 are controlled desirably.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output channel connection control device for controlling connections between a plurality of input channels and a plurality of output channels.

2. Description of the Related Art The configuration of a typical conventional input/output channel connection control device is shown in FIG. Here, to simplify the explanation, the number of input channels is three and the number of output channels is four.

As shown in FIG. 3, input channels IN+, IN2,
IN3 and output channel OUT+, 0UT2.0UT3
, OUT, and a matrix circuit is constructed, and a switch SIJ is connected to each intersection of the matrix. When switch SIj is turned on, input channel IN and output channel 0UTj are connected.

One input channel INI and each output channel 0UTI ~
There are switches S++sS+z and OUT respectively.
S13 and Ski are interposed, and these four switches 5
The 1t-8th group is a control unit, and a control signal is supplied from the 4-bit register R1 to these switches St+"S. In correspondence with each input channel, each switch is Sll-S14, S21-S24, S3
．． It is divided into three groups, 834 to 834, and registers R3, R2, and R1 correspond to each group, respectively.

The inputs of each register RI'''-Rs are commonly connected to bus 1, and 4-bit connection control data (output channel selection data) Do is supplied from a processor (not shown).
ut is input in parallel to each register RI"""Rs via buffer 2.When latch timing signals T, ~T, are applied to each register R2-R3, input data is latched and its Each bit of data becomes a control signal for four switches 5tt-8i4.

It is the decoder 3 that generates the latch timing signals T1-T. Input channel selection data Din is input to this decoder 3 from the processor (not shown) via a buffer 4, and one strobe signal STB
and a timing signal T generated by the timing control circuit 5 in accordance with the clock signal CLK. is supplied. The input channel selection data Din is a 2-bit code that expresses which manual channel is to be connected.
The decoder 3 decodes this and generates a timing signal T1.
Either one of T2 and T is output.

FIG. 4 shows the operation timing of the above configuration. The processor controls the connection between the input channel IN and the output channels OUT, .about.OUT. Input channel selection data Din.

4-pit output selection data D indicating which of OUT and 0UT4 to connect to. Output ut. Then, the timing signal T is output from the decoder 3, and the output selection data Dout is sent to the register R1.
and switches S11 to S8 according to the data.
14 is controlled. The processor then receives input selection data Din and output selection data D. ut is updated and data D is stored in register R2. By latching ut, the connection between input channel N2 and output channels OUT, .about.0UT4 is controlled. Similarly, Din.

DOut is updated and data D is stored in register R3. By latching ut, input channel IN and output channel OUT
Controls the connection with T, ~OUT,.

Problems to be Solved by the Invention In the conventional input/output channel connection control device described above, the output selection data Dout is assigned to which register R+, R2, R5.
Since the configuration is such that the processor side specifies one by one whether to latch as input selection data Din, the burden on the processor side becomes considerably large in devices with a large number of input channels, and the circuit size of the buffer 4 and decoder 3 also increases. There was a problem with getting bigger.

This invention was made in view of the above problems, and provides a device that can efficiently connect and disconnect a large number of input/output channels with a simpler circuit configuration and simpler connection control processing. The purpose is to

Means for Solving the Problems The input/output channel connection control device of the present invention includes a plurality of registers for latching connection control data for controlling switches at respective connection points between a plurality of input channels and a plurality of output channels; The device includes data issuing means for sequentially supplying the connection control data to a common input bus of the plurality of registers, and synchronization means for sequentially supplying a latch timing signal to the plurality of registers in synchronization with the data issuing means. .

Effect: By outputting the connection control data to be applied to the plurality of registers from the data issuing means in a fixed order, and applying a latch timing signal from the synchronizing means to each register in turn in accordance with this order, each data is set to a predetermined value. It fits in the register. Therefore, a signal for selecting a register (input selection signal Din in the prior art) is not necessary.

Embodiment FIG. 1 shows the configuration of a connection control device according to an embodiment of the present invention, and FIG. 2 shows its operation timing. In this embodiment, as well as the conventional example shown in FIG. 3, for the sake of simplicity,
Assume that the number of input channels is 3 and the number of output channels is 4.

As in the conventional example, a switch 5II-834 is provided at each intersection of a matrix circuit consisting of input channels IN, ~IN3 and output channels OUT, ~0UT4! 7, S++~
The control signals for the SI4 group are from register R1 to 32
The control signals for groups 1 to S24 are from register R2.
S3. The control signals of groups S34 to S34 are respectively given from register R3. A common input path of each register R4 to R3 is supplied with 4-bit output channel selection data (connection control data) Dout from a processor (not shown) via a buffer 2.

It is the 3-bit shift register 6 that generates the latch timing signals T, -T, to each register R, -R3, which is different from the conventional one. The processor has registers R+-R
Output selection data Dout is given in the order of 2→R8. At that time, turn on the enable signal of shift register 6,
A clock signal CLK synchronized with the update of the output channel selection data Dout is input to the shift register 6 via the inverter 7.

Then, as shown in FIG. 2, while the data Dout to be given to the register R1 is being output, the shift register 6
A latch timing signal T+ is generated from the register R2, a latch timing signal T2 is generated when the data Dout to be applied to the register R2 is outputted one after another, and a latch timing signal T is generated when the data Dout to be applied to the register R5 is then outputted. That is, the shift register 6 operates as the synchronizing means described above, and the data Dout sequentially applied is latched in the respective predetermined registers R1 to R8 in order, and the switches Sll to S34 are controlled as desired.

Effects of the Invention As explained in detail above, in the input/output channel connection control device according to the present invention, the process of latching predetermined connection control data to a plurality of registers having a common input bus is synchronized with the data issuing means. Since this is performed by a simple timing distribution circuit, processing on the processor side is simpler than before even if the number of input/output channels is large, and the burden on software is significantly reduced. Further, the circuit configuration of the synchronizing means for performing timing distribution becomes extremely simple.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a device according to an embodiment of the present invention, FIG. 2 is an operation timing diagram thereof, and FIG. 3 is a schematic configuration diagram of a conventional example.
FIG. 4 is an operation timing chart of the conventional device. IN, ~IN, ... input channel, OUT, ~OUT
. ...output channel, S, 1 to S34...switch,
Dout...Connection control data (output channel selection data). Figure 1

Claims (1)

[Claims] a plurality of registers for latching connection control data that controls switches at connection points between the plurality of input channels and the plurality of output channels, and data for sequentially applying the connection control data to a common input bus of the plurality of registers. An input/output channel connection control device comprising an issuing means and a synchronizing means for sequentially applying a latch timing signal to the plurality of registers in synchronization with the data issuing means.