JPH02141035A - Subordinate phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To absorb delaying time fluctuation occurring at an interoffice transmission line and to attain the interoffice phase synchronization by receiving a base band signal and detecting the reference time. CONSTITUTION:By using that at subordinate phase synchronizing circuits 5a and 5b executing the interoffice phase synchronizing control and the absorption of the delaying time of a base band signal occurring at interoffice transmission lines 3a and 3b connecting a central radio base station A and respective peripheral radio base stations B and C, the fluctuation of the residual time of a regenerative clock signal is not accumulated, a long-time time base is prepared, and the oscillation frequency of a voltage controlled oscillator is suppressed within allowance based on the long-time time base. The signal is accumulated to a memory circuit, a writing clock and a reading clock are separated and the residual time fluctuation is absorbed. In such a manner, the absorption of a delaying time fluctuation occurring in the interoffice transmission lines 3a and 3b and the interoffice phase synchronization can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to technology for absorbing delay time fluctuations in inter-office transmission paths and for inter-office phase synchronization in a digital mobile radio communication system. ] An example of a digital mobile radio communication system in which a unit service area is constructed from a plurality of small zones is shown in Fig. 4, and a conventional phase synchronization circuit is shown in Fig. 5.

Control signals such as paging control signals and area control signals generated by the control signal generator 2 of the central radio base station A are transmitted after being added with a prescribed amount of delay by the delay adjustment circuit 4. 6d, the radio frequency f is modulated and transmitted (H).The control signal is transmitted to the small zone B and the small zone C via the inter-office transmission line 3c and the inter-office transmission line 3d, respectively. It is sent to the forming peripheral wireless base station B and peripheral wireless base station C.

An overlap zone D where the small zones overlap in both cases of simultaneous transmission and sequential transmission.

In order to increase the reception rate of mobile II B b at E, it is necessary to suppress baseband delay time fluctuations of control signals transmitted from each of the peripheral radio base stations and to achieve inter-station phase synchronization.

In each of the peripheral wireless base stations, the phase i11! l The above-mentioned middle 9 at 7c and 7d of the reception area! , receives a control signal sent from a radio base station, and uses phase synchronization circuits 22a and 22b so that the control signal No. 48 and the control signal transmitted via the inter-station transmission path are in phase. The amount of delay of the control signal transmitted via the inter-office transmission path is set. The control signal with the delay amount set is modulated on the same radio frequency as the central radio base station and transmitted 1j! It is sent from 6e and 6f.

In FIG.
-7'J knob 70 knob (hereinafter also simply referred to as 1-DFFJ) At 10C, the control signal is re-switched for waveform shaping etc.
It absorbs delay time fluctuations occurring in the inter-office transmission lines 3c and 3d.

Based on the phase difference signals detected by each of the phase adjustment receivers 7c and 7d, delay! l setting circuit 12b and delay circuit 2
In step 3, a delay is applied so that the control signals sent out from each of the peripheral wireless base stations are in phase with the control signals sent out from the central wireless base station.

[Problem to be solved by the invention]

However, in conventional phase-locked circuits, there is residual delay time fluctuation in the output of the PLL clock regeneration circuit, and it is not possible to completely absorb delay time fluctuations that occur in the inter-station transmission path. Delay time fluctuations remain.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a dependent phase synchronization circuit that absorbs delay time fluctuations occurring in inter-office transmission paths and performs inter-office phase synchronization.

[Means to solve the problem]

According to the invention, the above objects are achieved by the means specified in the claims.

That is, in the present invention, a unit service area is composed of a central radio base station, a plurality of peripheral radio base stations, an inter-office transmission path connecting the central radio base station and each peripheral radio base station, and a mobile device. In the phase-locked circuit in the peripheral radio base station, which is used in the digital mobile radio communication system and performs phase synchronization control and absorption of delay time fluctuations occurring in the above-mentioned inter-station transmission path, the phase-locked circuit in the central radio base station means for receiving a baseband signal controlled and transmitted based on a reference clock oscillator provided in the baseband signal and detecting a reference time from the baseband signal; and oscillation means having a function of controlling an oscillation frequency based on the reference time. , means for accumulating the signals sent from the inter-office transmission line in a -H memory, and reading and outputting the M-multiplied signal in synchronization with the output of the oscillation means; This is a dependent phase synchronization circuit that absorbs the delay time of the baseband signal occurring in the inter-office transmission path that connects peripheral radio base stations and performs inter-office phase synchronization control.

[For production]

In the dependent phase synchronization circuit of the present invention, a long-time time base is created by taking advantage of the fact that the residual time fluctuations of the recovered clock signal are not accumulated, and the oscillation frequency of the voltage-controlled oscillator is controlled within the tolerance based on this long-time time base. Keep it to.

Additionally, residual time fluctuations are absorbed by storing the signal in a memory circuit and separating the write clock and read clock.

Thereby, the configuration is such that it is possible to absorb delay time fluctuations occurring in the inter-office transmission path and perform inter-office phase synchronization.

〔Example〕

1, 2, and 3 are diagrams for explaining one embodiment of the present invention, in which FIG. 1 is a schematic diagram of a digital mobile radio communication system using the dependent phase synchronization circuit of the present invention, and FIG. FIG. 2 is a configuration diagram of a dependent phase locked circuit according to the present invention, and FIG. 3 is a phase change diagram of an output of the dependent phase locked circuit.

In FIG. 1, a control signal generator 2 generates control signals such as a call control signal and an area control signal based on a clock signal from a reference clock oscillator 1.

At the central radio base station A, a delay adjustment circuit 4 adds a prescribed amount of delay to the # signal, modulates the radio frequency f with the control signal, and sends it out from the transmitter 1f16a.

Each peripheral wireless base station B has inter-office transmission lines 3m and 3b.

The control signal transmitted to C is first input to the dependent phase synchronization circuits 5m and 5b.

In the dependent phase synchronization circuit shown in FIG. 2, a clock recovery circuit 9a generates a recovered clock signal dependent on the clock signal of the reference clock oscillator 1 from the inputted control signal. The memory circuit 14 uses a dual-boat memory that has two 7-dress paths 14c, 14d and two input/output ports 14a*14b for one memory cell, each having a function of being independently and asynchronously accessible. . On the input side of the memory circuit, using the recovered clock signal recovered by the clock recovery circuit 9a, the DF
At Floa, the control signal is switched again for waveform shaping, etc., and the write address counter circuit 11 is operated to sequentially write the control signal into the memory circuit 14.

On the output side, the frequency of the reproduced clock signal is divided by the reference time development raw circuit 13 to create a reference time, and the oscillation frequency of the voltage controlled oscillation circuit 20 is determined by the frequency counter circuit 1 based on the reference time.
Measure at 5.

The logic comparison circuit 16 compares the value measured by the frequency counter circuit 15 with the phase deviation tolerance set by the phase deviation tolerance setting circuit 17.

The D/A conversion circuit 21 converts the output of the logic comparison circuit 16 into a voltage.

In the phase change diagram of the dependent phase synchronization circuit output in Fig. 3,
The data curve indicated by a indicates the case where both a frequency deviation between the inter-office transmission line signal input and the voltage-controlled oscillator circuit 20 and a delay time variation in the inter-office transmission line occur. This represents the case where the average frequency is the same and there is only delay time variation in the inter-office transmission path.

As is clear from the figure, a change in the oscillation frequency of the voltage controlled oscillator 20 appears as a phase change in the output signal.

That is, the D
It is controlled by the voltage output of the /A conversion circuit 21.

The output of the voltage controlled oscillator circuit 20 is frequency-divided by a frequency dividing circuit 19, operates a read address counter circuit 18, and sequentially reads out the control signals written in the memory circuit 14 and reselects them by DFFIO and outputs them. .

The delay amount setting circuit 12m is connected to the phase 1jlI adjustment receiver 7a.
resetting the addresses of the writing address counter circuit 11 and the reading 7-address counter circuit 18 using a phase difference signal from lTb (frame synchronization);
The initial value of the frequency division counter of the frequency division circuit 19 is set so that the baseband phases of the control signals of each peripheral wireless base station B and C are in the same phase (bit synchronization).

Each of the peripheral radio base stations B and C modulates the output of the dependent phase synchronization circuit as a modulation signal to the same radio frequency f as that of the central radio base station A, and simultaneously or sequentially moves from the transmitters 116b and 6c. Send to.

〔Effect of the invention〕

As described above, by using the dependent phase synchronization circuit of the present invention, it is possible to absorb delay time fluctuations occurring in the interstation transmission path and perform interstation phase synchronization control.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a digital mobile radio communication system using the dependent phase-locked circuit of the present invention, FIG. 2 is a block diagram of the dependent phase-locked circuit of the present invention, and FIG. 3 is a diagram of the output of the dependent phase-locked circuit. FIG. 4 is a schematic diagram of a digital mobile radio communication system using a conventional phase-locked circuit, and FIG. 5 is a block diagram of a conventional phase-locked circuit. 1...Reference clock oscillator, 2.
...Control signal generator, 3a=3b
+3c, 3d... Inter-office transmission line, 4 ・
...Delay 5119 circuit, 5a, 5b.
...Subordinate phase synchronization circuit, 6m, 6b, 6
e+6d. 6e, 6f ・=- transmitter, 7a, 7b. 7c, 7cl...Phase rI4I4 receiving receiver 8ay8b...Mobile device, 9a,
9b... Clock regeneration circuit, 1
0a, 10b. 10c... D-7 Lip 70 Tubu (DFF)
・11...Writing address counter circuit ・12a, 12b...Delay amount setting circuit, 13
...Reference time generation circuit, 14 ...
... Memory circuit, 14av14b...
...I/O boat, 14c, 14d...
・・・Address bus, 15 ・・・・・・
・Frequency counter circuit, 16...
・Logic comparison circuit, 17 ・・・・・・
Phase deviation tolerance setting circuit, 18...
Read address counter circuit, 19 ・
... Frequency divider circuit, 20 ... Voltage controlled oscillation circuit, 21 ... D/A conversion circuit,
22a, 22b...phase synchronized circuit,
23 ・・・・・・Delay circuit agent Patent attorney Takayoshi Honma Diagram

Claims (1)

[Claims] A unit service area is composed of a central radio base station, a plurality of peripheral radio base stations, an inter-office transmission path connecting the central radio base station and each peripheral radio base station, and a mobile device. In the phase-locked circuit in the peripheral radio base station that is used in the digital mobile radio communication system and performs phase synchronization control and absorption of delay time fluctuations occurring in the above-mentioned inter-station transmission path, the phase-locked circuit in the central radio base station means for receiving a baseband signal controlled and transmitted based on a reference clock oscillator provided in the baseband signal and detecting a reference time from the baseband signal; and oscillation means having a function of controlling an oscillation frequency based on the reference time. , means for temporarily accumulating signals sent from the inter-office transmission path in a memory, and reading and outputting the accumulated signals in synchronization with the output of the oscillation means, the central radio base station and each of the peripheral radios A dependent phase synchronization circuit is characterized in that it absorbs delay time of a baseband signal occurring in an inter-office transmission line connecting a base station and performs inter-office phase synchronization control.