JPH0214101U

JPH0214101U -

Info

Publication number: JPH0214101U
Application number: JP9025588U
Authority: JP
Priority date: 1988-07-07
Filing date: 1988-07-07
Publication date: 1990-01-29

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示す構成図、第２図
は本考案の他の実施例を示す主要部の構成図、第
３図は従来技術の一例を示す構成図、第４図はそ
の動作説明図、第５図は同じく従来技術の一例を
示す構成図、第６図はその動作説明図である。２Ａ，２Ｂ……位置形コントローラ、３……制
御弁、４……ハイセレクタ、５Ａ，５Ｂ……加算
手段、６Ａ，６Ｂ……１次遅れユニツト。 Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of main parts showing another embodiment of the present invention, Fig. 3 is a block diagram showing an example of the prior art, and Fig. 4 is a block diagram showing an example of the prior art. FIG. 5 is a configuration diagram showing an example of the prior art, and FIG. 6 is an explanatory diagram of the operation. 2A, 2B... Position type controller, 3... Control valve, 4... High selector, 5A, 5B... Adding means, 6A, 6B... First order delay unit.

Claims

[Scope of utility model registration request]

A first position type controller that transmits a first operation output of a position type that has control-calculated the deviation between the first measured value and the first target value; A second device that transmits a second operation output.
a position type controller, a selector means for automatically selecting one of the first and second operation outputs and transmitting the operation output to the operating end, and first and second selector means for inputting the operation output of the selector means. an autoselector circuit comprising a first-order delay unit, and first and second adding means for adding the outputs of the first and second first-order delay units to the first and second operation outputs, respectively.