JPH0213970B2 - - Google Patents
Info
- Publication number
- JPH0213970B2 JPH0213970B2 JP24245684A JP24245684A JPH0213970B2 JP H0213970 B2 JPH0213970 B2 JP H0213970B2 JP 24245684 A JP24245684 A JP 24245684A JP 24245684 A JP24245684 A JP 24245684A JP H0213970 B2 JPH0213970 B2 JP H0213970B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- adder
- multiplier
- quantizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 3
- 238000013139 quantization Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は画像帯域圧縮装置に用いられる
DPCM回路特に３入力２出力デイジタル・デイ
ジタル変換器（以下本明細書において３入力２出
力Ｄ〜Ｄ変換器と略記する）及びこの２出力を加
算する加算器を用いた高速DPCM回路に係り、
予測のための信号を得る演算速度をより向上でき
る高速DPCM回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in an image band compression device.
Concerning a DPCM circuit, particularly a high-speed DPCM circuit using a 3-input 2-output digital-to-digital converter (hereinafter abbreviated as 3-input 2-output D-D converter) and an adder that adds these two outputs,
This invention relates to a high-speed DPCM circuit that can further improve the calculation speed for obtaining signals for prediction.
［従来技術］
第２図は従来の高速DPCM回路として、本出
願人が特願昭59−181061号で出願した本明の実施
例を示す図である。第２図において１は３入力２
出力Ｄ／Ｄ変換器、２は加算器、３と７は遅延素
子としてフリツプフロツプFF、４は量子化器、
５は加算器、６，８，９は予測係数ｐを乗算する
乗算器を示す。また各回路間の接続線上に短い斜
線とともに示す数字はビツト数の一例である。３
入力２出力Ｄ／Ｄ変換器１の下方からの２入力線
は１標本化周期前の信号を予測して入力するもの
で、その予測のための乗算器６，８，９を使用し
ている。即ち量子化器４の出力のDPCM信号は
乗算器８にて予測係数ｐを乗算され、３入力２出
力Ｄ／Ｄ変換器１に入力し、またFF７の出力で
ある１標本化周期前の値は、乗算器９にて予測係
数ｐを乗算されて３入力２出力Ｄ／Ｄ変換器１に
入力する。そして３入力２出力Ｄ／Ｄ変換器１に
入力しているPCM信号との間で２出力に変換さ
れ、この出力は加算器５にて加算され、FF２を
介して量子化器４に入力する。量子化器４におい
て量子化されたDPCM信号を出力するようにし
て、従来の予測のために２入力１出力の減算器を
用いるDPCM回路よりは高速なDPCM回路を実
現している。[Prior Art] FIG. 2 is a diagram showing an embodiment of the present invention, which was filed by the present applicant in Japanese Patent Application No. 181061/1983, as a conventional high-speed DPCM circuit. In Figure 2, 1 is 3 inputs 2
Output D/D converter, 2 is an adder, 3 and 7 are flip-flop FFs as delay elements, 4 is a quantizer,
5 is an adder, and 6, 8, and 9 are multipliers for multiplying the prediction coefficient p. Further, the numbers shown with short diagonal lines on the connection lines between each circuit are examples of the number of bits. 3
The two input lines from the bottom of the two-input/output D/D converter 1 predict and input the signal one sampling period before, and multipliers 6, 8, and 9 are used for this prediction. . That is, the DPCM signal output from the quantizer 4 is multiplied by the prediction coefficient p in the multiplier 8, inputted to the 3-input 2-output D/D converter 1, and the DPCM signal output from the FF 7, which is the value one sampling period before, is is multiplied by the prediction coefficient p in the multiplier 9 and input to the 3-input 2-output D/D converter 1. The PCM signal input to the 3-input 2-output D/D converter 1 is then converted into 2 outputs, and the outputs are added together in the adder 5 and input to the quantizer 4 via the FF 2. . By outputting a quantized DPCM signal in the quantizer 4, a DPCM circuit faster than a conventional DPCM circuit using a 2-input 1-output subtracter for prediction is realized.
第３図は第２図の３入力２出力Ｄ／Ｄ変換器１
と加算器２との組み合わせ及び遅延素子としての
FF３の接続を示す図である。第３図において、
１−０〜１−７は３入力２出力Ｄ／Ｄ変換器の各
桁の全加算器であり、図示の如く入力PCM信号
８ビツトA0〜A7に対し、第２図の乗算器９及び
乗算器８からの信号C0〜C7、B0〜B7のそれぞれ
の反転出力が更に入力され、それぞれよりの加算
した２出力は加算器の各桁毎の全加算器２−０〜
２−７に図示の如く入力される。なお第３図の例
は乗算器８の入力７ビツトの例であり、この場合
C0〜C6が有効であり、全加算器１−７のC7入力
は“０”となつている。即ち、変換器の各桁の加
算結果は対応する加算器の対応桁の全加算器に、
また桁上げ値はその上位桁の全加算器に入力され
ている。なおこの図で全加算器２−１〜２−７の
桁上げ出力は更に上位の全加算器に入力される
が、図示省略している。また上位桁を無視する場
合もある。全加算器２−０にはHVレベルとして
“１”が入力される。 Figure 3 shows the 3-input, 2-output D/D converter 1 in Figure 2.
and adder 2 and as a delay element.
It is a diagram showing the connection of FF3. In Figure 3,
1-0 to 1-7 are full adders for each digit of the 3-input 2-output D/D converter, and as shown in the figure, for the input PCM signal 8 bits A0 to A7 , the multiplier 9 in FIG. The respective inverted outputs of the signals C 0 -C 7 and B 0 -B 7 from the multiplier 8 are further input, and the summed two outputs from each are sent to the full adders 2-0 to 2-0 for each digit of the adder.
2-7 is input as shown in the figure. The example in Figure 3 is an example of 7 bits input to the multiplier 8, and in this case
C0 to C6 are valid, and the C7 input of the full adder 1-7 is "0". That is, the addition result of each digit of the converter is added to the full adder of the corresponding digit of the corresponding adder,
Further, the carry value is input to the full adder of its upper digit. In this figure, the carry outputs of the full adders 2-1 to 2-7 are input to the higher-order full adders, but they are not shown. Also, the upper digits may be ignored. “1” is input to the full adder 2-0 as the HV level.
３入力２出力Ｄ／Ｄ変換器では３入力信号の各
桁毎の全加算を行い、各桁毎に桁上値と加算結果
の２出力を取り出し、この各桁毎の加算結果と下
位桁よりの桁上げ値が加算器２の対応桁の全加算
器に入力され、それぞれ桁の加算結果を出力し
て、桁上げ出力は１桁上の全加算器に与えられる
ようになつている。 A 3-input, 2-output D/D converter performs full addition for each digit of the 3-input signal, takes out the carry value and the addition result for each digit, and combines the addition result for each digit with the addition result from the lower digit. The carry value is input to the full adder of the corresponding digit of adder 2, the addition result of each digit is output, and the carry output is given to the full adder of one digit above.
［発明が解決しようとする問題点］
しかしながらこの場合、処理速度を決定するク
リテイカルパスとしては、３入力２出力Ｄ／Ｄ変
換器１、加算器２、FF３、量子化器４、乗算器
８のループとなり、乗算器８の動作速度により全
体の動作速度を決めることとなつた。そして乗算
器８と量子化器４の動作速度は他の素子と比較す
るとやや遅いという問題があつた。[Problems to be Solved by the Invention] However, in this case, the critical paths that determine the processing speed include a 3-input 2-output D/D converter 1, an adder 2, an FF 3, a quantizer 4, and a multiplier 8. The operation speed of the multiplier 8 determines the overall operation speed. There was also a problem that the operating speeds of the multiplier 8 and the quantizer 4 were somewhat slow compared to other elements.
［問題点を解決するための手段］
前述の問題点を解決するため、本発明の採用し
た手段は、出力側に量子化DPCM信号を発生す
る第１の出力と量子化DPCM信号に予測係数を
乗算した信号を出力する第２の出力とを有する量
子化器と、
第１の加算器及び第１の遅延素子及び第１の乗
算器とを含み、且つ該第１の乗算器で該第１の遅
延素子の出力に予測係数を乗算し、この出力を前
記量子化器の第１の出力と共に前記第１の加算器
に入力して該第１の加算器の出力を前記第１の遅
延素子に入力して予測値を検出する予測値検出ル
ープと、第１の入力にPCM信号が、第２の入力
に前記量子化器の第２の出力が、第３の入力に前
記第１の遅延素子にて遅延された信号と第２の乗
算器により予測係数を乗算した信号が入力し、第
１・第２・第３の各入力の各ビツト毎に加算し
て、該加算結果と桁上げ値を出力する３入力２出
力デイジタル・デイジタル変換器と、該３入力２
出力デイジタル・デイジタル変換器出力が印加さ
れ、該２出力を加算する第２の加算器と、
該第２加算器出力が印加され該信号を遅延させ
る第２の遅延素子と、を具備し、
該第２遅延素子出力は前記量子化器の入力側に
接続したことである。[Means for Solving the Problems] In order to solve the above-mentioned problems, the means adopted in the present invention includes a first output that generates a quantized DPCM signal on the output side and a prediction coefficient for the quantized DPCM signal. a quantizer having a second output that outputs a multiplied signal; a first adder, a first delay element, and a first multiplier; The output of the delay element is multiplied by a prediction coefficient, this output is input to the first adder together with the first output of the quantizer, and the output of the first adder is multiplied by the prediction coefficient. a predicted value detection loop that detects a predicted value by inputting a PCM signal to a first input, a second output of the quantizer to a second input, and a predicted value to a third input of the first delay. The signal delayed by the element and the signal multiplied by the prediction coefficient by the second multiplier are input, and are added for each bit of each of the first, second, and third inputs, and the addition result and carry are A 3-input 2-output digital-to-digital converter that outputs a value, and the 3-input 2
a second adder to which the output of the digital-to-digital converter is applied and which adds the two outputs; and a second delay element to which the output of the second adder is applied and which delays the signal; The output of the second delay element is connected to the input side of the quantizer.
［作用］
本発明では従来の高速DPCM回路の第２の遅
延素子（第２図のFF３）の出力に、第２図の量
子化器４の代わりに量子化DPCM信号を発生す
る第１の出力と、量子化した後予測係数を乗算し
て出力する第２の出力を有する量子化器を設置
し、その代わりに量子化器の出力に予測係数を乗
算する乗算器を具備しない。この量子化した後予
測計数を乗算して出力する機能は、通常読出し専
用メモリ（ROM）を用いて容易に一体化して実
現できるため、この量子化器の入力から量子化器
の第１の出力またの遅延量と、同第２の出力まで
の遅延量は同じと考えられる。また従来の第１の
加算器の出力に予測係数を乗算せず、その代わり
に１標本化周期前の値（第２図のFF７の出力）
に予測係数を乗算して第１の加算器に入力する一
方予測係数の２乗を乗算して３入力２出力Ｄ／Ｄ
変換器に入力する。この予測計数を乗算する機能
は、通常乗算用LSI若しくは読出し専用メモリ
（ROM）を用いて容易に一体化して実現できる
ため、この予測計数の２乗を乗算する乗算器の遅
延量は、予測計数のみを乗算する乗算器の遅延量
と同じと考えられる。そのため前記３入力２出力
Ｄ／Ｄ変換器の第２入力となるルートに乗算器を
具備しないから、第２の遅延素子→量子化器の第
２出力→３入力２出力Ｄ／Ｄ変換器の第２入力→
第２の加算器→第２の遅延素子よりなるクリテイ
カルパスは乗算器の遅延分だけ予測信号を得るた
めの演算速度が向上できる。[Function] In the present invention, the output of the second delay element (FF3 in FIG. 2) of the conventional high-speed DPCM circuit is provided with a first output that generates a quantized DPCM signal instead of the quantizer 4 in FIG. Then, a quantizer having a second output that multiplies the quantized prediction coefficient and outputs the result is installed, and instead, a multiplier that multiplies the output of the quantizer by the prediction coefficient is not provided. This function of multiplying and outputting the predicted coefficients after quantization can be easily integrated and realized using a read-only memory (ROM), so that the input of the quantizer can be output from the first output of the quantizer. It is considered that the amount of delay until the second output is the same as the amount of delay until the second output. Also, the output of the conventional first adder is not multiplied by the prediction coefficient, but instead the value one sampling period ago (output of FF7 in Figure 2)
is multiplied by the prediction coefficient and input to the first adder, while multiplied by the square of the prediction coefficient to form a 3-input 2-output D/D.
Input to converter. The function of multiplying this predicted count can be easily integrated and realized using a normal multiplication LSI or read-only memory (ROM), so the delay amount of the multiplier that multiplies the square of this predicted count is It can be considered that the delay amount is the same as that of a multiplier that multiplies only Therefore, since a multiplier is not provided in the route that becomes the second input of the 3-input 2-output D/D converter, the second delay element → the second output of the quantizer → the 3-input 2-output D/D converter 2nd input→
In the critical path consisting of the second adder→second delay element, the calculation speed for obtaining the predicted signal can be improved by the delay of the multiplier.
［実施例］
第１図は本発明の実施例の構成を示すブロツク
図である。第１図において１は３入力２出力Ｄ／
Ｄ変換器、２は第２の加算器、３は第２の遅延素
子であるフリツプフロツプFF、５は第１の加算
器、７は第１の遅延素子であるフリツプフロツプ
FF、１０は量子化DPCM信号を発生する第１の
出力と量子化した後予測係数ｐを乗算して出力す
る第２の出力を有する量子化器、１１は予測係数
ｐ×ｐを乗算する第の乗算器、１２は予測係数ｐ
を乗算する第１の乗算器を示す。また各回路間の
接続上に短い斜線と共に示す数字はビツト数の一
例である。例えば数字の７、８、９、10、11は
各々27、28、29、210、211の演算精度を持つこと
を示す。[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In Figure 1, 1 has 3 inputs and 2 outputs D/
D converter, 2 is a second adder, 3 is a flip-flop FF which is a second delay element, 5 is a first adder, and 7 is a flip-flop which is a first delay element.
FF, 10 is a quantizer having a first output that generates a quantized DPCM signal and a second output that is multiplied by a prediction coefficient p after quantization; 11 is a quantizer that multiplies the prediction coefficient p×p; multiplier, 12 is the prediction coefficient p
1 shows a first multiplier that multiplies . Further, the numbers shown with short diagonal lines on the connections between each circuit are examples of the number of bits. For example, the numbers 7, 8, 9, 10, and 11 indicate calculation precision of 2 7 , 2 8 , 2 9 , 2 10 , and 2 11 , respectively.
今FF３の出力が量子化器１０に印加されたと
き、量子化器１０は従来と同様DPCM信号を第
１出力として出力すると共に、量子化して予測係
数ｐを乗算した値を第２出力とするように動作す
る。 Now, when the output of FF3 is applied to the quantizer 10, the quantizer 10 outputs the DPCM signal as the first output as in the past, and also outputs the value obtained by quantizing and multiplying by the prediction coefficient p as the second output. It works like this.
この量子化した後予測計数を乗算して出力する
機能は、通常読出し専用メモリ（ROM）を用い
て容易に一体化して実現できるため、この量子化
器の入力から、量子化器の第１の出力までの遅延
量と、同第２の出力までの遅延量は同じと考えら
れる。なお、この時第１の出力には、ROMを用
いで量子化DPCM信号を発生できる。そして量
子化器１０の第２出力は３入力２出力Ｄ／Ｄ変換
器１の第２入力となつている。 This function of multiplying and outputting the predicted coefficient after quantization can be easily integrated and realized using a read-only memory (ROM), so from the input of this quantizer, the first The amount of delay up to the output and the amount of delay up to the second output are considered to be the same. Note that at this time, a quantized DPCM signal can be generated as the first output using a ROM. The second output of the quantizer 10 is the second input of the three-input, two-output D/D converter 1.
また第１の遅延素子FF７の一方の出力は乗算
器１２を介して第１加算器５の入力となる。そし
て第１の加算器５の出力は第１の遅延素子として
動作するフリツプフロツプFF７に印加される。
第１の遅延素子FF７の他方の出力は第２乗算器
１１において予測係数ｐ×ｐを乗算する。この予
測計数の２乗を乗算する機能は、通常乗算用LSI
若しくは読出し専用メモリ（ROM）を用いて容
易に一体化して実現できるため、この予測計数の
２乗を乗算する乗算器の遅延量は、予測計数のみ
を乗算する乗算器の遅延量と同じと考えられる。
第２乗算器１１の出力は３入力２出力Ｄ／Ｄ変換
器１の第３入力となつている。 Further, one output of the first delay element FF7 becomes an input to the first adder 5 via the multiplier 12. The output of the first adder 5 is applied to a flip-flop FF7 which operates as a first delay element.
The other output of the first delay element FF7 is multiplied by the prediction coefficient p×p in the second multiplier 11. The function of multiplying the square of this predicted count is usually performed by a multiplication LSI.
Alternatively, it can be easily integrated using read-only memory (ROM), so the delay amount of a multiplier that multiplies the square of the predicted count is considered to be the same as the delay amount of a multiplier that multiplies only the predicted count. It will be done.
The output of the second multiplier 11 serves as the third input of the three-input, two-output D/D converter 1.
３入力２出力Ｄ／Ｄ変換器１において、第１入
力として入力しているPCM信号と前記第２・第
３入力信号から２出力を得て、これら出力は第２
加算器２において加算される。第２加算器２の出
力は第２の遅延素子として動作するフリツプフロ
ツプFF３を介して量子化器１０に印加される。 In the 3-input 2-output D/D converter 1, two outputs are obtained from the PCM signal input as the first input and the second and third input signals, and these outputs are
Added in adder 2. The output of the second adder 2 is applied to the quantizer 10 via a flip-flop FF3 which operates as a second delay element.
［発明の効果］
このようにして本発明によると、第２の遅延素
子→量子化器の第２出力→３入力２出力Ｄ／Ｄ変
換器の第２入力→第２の加算器→第２の遅延素子
よりなるルートの動作速度が早くなる。なおｐ×
ｐを乗算する第２の乗算器が量子化器と比較して
動作速度がより高速のときは、従来回路に比べて
乗算器１個分だけは確実に動作速度が向上でき
る。[Effects of the Invention] In this way, according to the present invention, the second delay element→the second output of the quantizer→the second input of the 3-input 2-output D/D converter→the second adder→the second The operating speed of the route consisting of delay elements becomes faster. Furthermore, p×
When the second multiplier that multiplies p has a faster operating speed than the quantizer, the operating speed can certainly be improved by one multiplier compared to the conventional circuit.
第１図は本発明の実施例の構成を示すブロツク
図、第２図は従来の高速DPCM回路のブロツク
図、で第３図は従来の３入力２出力変換器を示す
ブロツク図である。
１……３入力２出力Ｄ／Ｄ変換器、２……第２
の加算器、３……第２の遅延素子、４，１０……
量子化器、５……第１の加算器、６，８，９……
乗算器、７……第１の遅延素子、１１……第２の
乗算器、１２……第１の乗算器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional high-speed DPCM circuit, and FIG. 3 is a block diagram showing a conventional three-input, two-output converter. 1...3 input 2 output D/D converter, 2...2nd
adder, 3... second delay element, 4, 10...
Quantizer, 5...First adder, 6, 8, 9...
Multiplier, 7...first delay element, 11...second multiplier, 12...first multiplier.
１ ある地域を無線にてカバーするエリアを単位
無線セルとするいくつかの無線セルで構成するよ
うなシステムにおける前記セルの中央に設けられ
る基地局において用いられ、前記セル内の移動す
る局から送信される電波を受信する水平面内で指
向性をもつ３基のアンテナを３方向に向けて設置
する組のアンテナを上下の方向等に２組設置し
て、前記移動する局からの電波を待ち受ける時
は、１組のアンテナの３基アンテナにそれぞれ３
台の受信機を接続して待ち受け受信を行ない、受
信電波が存在する時は、３台の受信機の出力レベ
ルを比較して最高受信レベルのアンテナに１台の
受信機を接続し、もう１組のアンテナの内前記最
高受信レベルのアンテナと同じ方向のアンテナに
１台の受信機を接続し、残り１台の受信機は、最
高受信レベルの次に高いレベルのアンテナに接続
し、受信機の受信出力は、前記３台の受信機の内
瞬時最高受信レベルを示す受信機の受信出力のみ
を選択して出力し、受信レベルがある一定のレベ
ル以下になつた時あるいは一定時間たつた時は、
1 Used in a base station installed in the center of a cell in a system consisting of several wireless cells, each of which covers an area by radio as a unit wireless cell, and transmits data from a station that moves within the cell. When waiting for radio waves from the moving station, three sets of antennas with directivity are installed in the horizontal plane facing in three directions, and two sets of antennas are installed in the upper and lower directions, etc. is 3 antennas each in 1 set of antennas.
Connect two receivers to perform standby reception, and when there is a received radio wave, compare the output levels of the three receivers, connect one receiver to the antenna with the highest reception level, and connect the other receiver to the antenna with the highest reception level. Connect one receiver to the antenna in the same direction as the antenna with the highest reception level among the set of antennas, connect the remaining one receiver to the antenna with the next highest reception level, and connect the receiver to the antenna with the highest reception level. The reception output is selected and outputted only from the reception output of the receiver showing the instantaneous highest reception level among the three receivers, and when the reception level falls below a certain level or after a certain period of time has elapsed. teeth,
Claims (1)
力側に接続したことを特徴とする高速DPCM回
路。 A high-speed DPCM circuit characterized in that the output of the second delay element 3 is connected to the input side of the quantizer 10.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59242456A JPS61121619A (en) | 1984-11-19 | 1984-11-19 | High speed dpcm circuit |
| KR1019850006333A KR890004441B1 (en) | 1984-08-30 | 1985-08-30 | Automatic cording circuit |
| DE8585110978T DE3586932T2 (en) | 1984-08-30 | 1985-08-30 | DIFFERENTIAL CODING CIRCUIT. |
| EP85110978A EP0173983B1 (en) | 1984-08-30 | 1985-08-30 | Differential coding circuit |
| CA000489802A CA1338767C (en) | 1984-08-30 | 1985-08-30 | Differential coding circuit |
| US07/049,048 US4771439A (en) | 1984-08-30 | 1987-05-12 | Differential coding circuit with reduced critical path applicable to DPCM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59242456A JPS61121619A (en) | 1984-11-19 | 1984-11-19 | High speed dpcm circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61121619A JPS61121619A (en) | 1986-06-09 |
| JPH0213970B2 true JPH0213970B2 (en) | 1990-04-05 |
Family
ID=17089365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59242456A Granted JPS61121619A (en) | 1984-08-30 | 1984-11-19 | High speed dpcm circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121619A (en) |
-
1984
- 1984-11-19 JP JP59242456A patent/JPS61121619A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61121619A (en) | 1986-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2382536A1 (en) | System and method for accurately predicting signal to interference and noise ratio to improve communications system performance | |
| US5880973A (en) | Signal processing system and method for enhanced cascaded integrator-comb interpolation filter stabilization | |
| JP2930320B2 (en) | Digital signal processor | |
| US6285300B1 (en) | Apparatus and method for reducing power and noise through reduced switching recording in logic devices | |
| McCanny et al. | Hierarchical VHDL libraries for DSP ASIC design | |
| EP0173983B1 (en) | Differential coding circuit | |
| JPH0213970B2 (en) | ||
| EP0016048A1 (en) | Predictive differential pulse-code modulation apparatus | |
| JPH0863198A (en) | Vector quantization device | |
| Nishitani et al. | LSI signal processor development for communications equipment | |
| EP0054024A1 (en) | Subscriber line audio processing circuit apparatus. | |
| Shimabukuro et al. | Reconfigurable current-mode multiple-valued residue arithmetic circuits | |
| US5734679A (en) | Voice signal transmission system using spectral parameter and voice parameter encoding apparatus and decoding apparatus used for the voice signal transmission system | |
| US4617427A (en) | Square root circuit | |
| US7493354B2 (en) | FIR filter tap architecture for highly dense layout | |
| US6252530B1 (en) | D/A converter having mechanism for preventing analog signal distortion | |
| JP3237649B2 (en) | CDMA communication device | |
| JPH0239138B2 (en) | SABUNFUGOKI | |
| JPH0156577B2 (en) | ||
| Shanbhag et al. | VLSI implementation of a 100 MHz pipelined ADPCM codec chip | |
| JPS6037657B2 (en) | DPCM device | |
| JPS5932951B2 (en) | DPCM encoding circuit | |
| Vainio et al. | Architecture and circuit design for DSP-ASIC | |
| JP2793520B2 (en) | Sound determination circuit | |
| JPS6251830A (en) | Parallel processing type plane forecasting circuit |