JPH0156577B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] Bandwidth compression of image information includes intra-field prediction,
Inter-field prediction and intra-frame prediction are performed, and in the case of moving images, DPCM encoding is performed using inter-frame prediction, etc., but in principle, both are plane (two-dimensional) predictive DPCM encoding, and the present invention This paper relates to speeding up a circuit that performs predictive DPCM encoding.

In such a DPCM circuit, the number of pixels increases as the image quality increases, so it is necessary to operate at high speed, and a circuit that can operate at high speed without using special devices is desired.

On the other hand, as a high-speed DPCM encoder suitable for DPCM encoding using the most basic previous value prediction based on the immediately preceding signal value, the present applicant, which will be described below, has proposed a
-181061 (Unexamined Japanese Patent Publication No. 1983-58327) (August 1982)
There is a high-speed DPCM encoder filed on April 30th.

This includes a difference signal output means for outputting a difference signal from an input signal, a quantizer for quantizing the difference signal from the means and outputting a quantized difference signal, and a quantizer for multiplying the quantized difference signal by a prediction coefficient. The difference signal output means includes a first multiplier, a first prediction loop that generates a first prediction signal from the quantized difference signal, and a second multiplier that multiplies the prediction signal by a prediction coefficient. teeth,
A high-speed DPCM encoder characterized in that it has a function of generating a difference signal between an input PCM signal and the output signals of a first multiplier and a second multiplier, An example of prediction is shown, and specifically, the configuration is as follows.

That is, the output side includes a quantizer that outputs a quantized DPCM signal, a first adder, a third multiplier, and a first delay element, and the third multiplier outputs a quantized DPCM signal. The output obtained by multiplying the output of the adder by the prediction coefficient is delayed by the first delay element, inputted to the first adder together with the output of the quantizer, and the prediction is output to the output of the third multiplier. It has a prediction loop (local decoding circuit) that obtains the value, on the input side, the input on the first input
A PCM signal is input to a second input, a signal obtained by multiplying the output of the quantizer by a first prediction coefficient by a first multiplier is input to a third input, and a signal obtained by multiplying the output of the quantizer by a first prediction coefficient is input to a third input. A signal multiplied by a first prediction coefficient is inputted by a multiplier, and the second and third prediction coefficients are inputted from the first input.
and a difference signal output means for subtracting the input, and the output of the difference signal output means is delayed by a second delay element and connected to the input side of the quantizer.
It is a DPCM code.

Incidentally, in the above embodiment, as a difference signal output means,
3 inputs having a first, second and third input, with the second and third inputs inverted (for subtraction), the first input and the second and third inverted inputs; The three inputs correspond to a two-output digital-to-digital converter, which adds each digit and converts each digit into two outputs: a carry and an addition result. An adder (hereinafter abbreviated as adder A) that inputs the input into each digit, inputs the carry output to each digit one digit above the corresponding digit, and adds the two outputs. has been done.

The difference signal output means, which has three inputs and two outputs, is composed of a digital-to-digital converter and an adder A, since each digit part of the three-input and two-output digital to digital converter operates in parallel. It is much faster than a normal adder, which requires carrying out in sequence, and when viewed as a 3-input adder, it can be considered approximately as fast as a 2-input adder. .

The present invention attempts to obtain a circuit for high-speed planar predictive DPCM encoding based on this high-speed DPCM encoder.

[Conventional technology]

FIG. 3 is a block diagram of a conventional planar predictive DPCM circuit, and FIG. 4 is a general block diagram of a conventional planar predictive DPCM circuit.

In the figure, 1 is a subtracter, and 2 and 5 are delay elements.
FF, 3 is a quantizer, 4 and 6 are adders, 7 to 9,
12 to 14 are multipliers, and 10, 11, 15, and 16 are delay circuits.

First, to explain the operation using FIG. 3 in the case of plane prediction as an example of the conventional example, the loop from the output of adder 4 to the input of adder 4 through FF 5 is a prediction loop (local decoder). The prediction coefficient (α ₀ = 1/2) is added to the locally decoded signal which is the output of adder 4.
The output multiplied by , that is, the previous value predicted output, and the local decoded output are delayed by the delay circuit 16 to obtain the local decoded output for the pixel one line (scanning line) before the pixel corresponding to the local decoded output, and the predicted output is Coefficient (α ₁ =
1/4) and the local decoded output are delayed by the delay circuit 15 to obtain the local decoded output for the pixel 1 line (scanning line) + 1 pixel before the pixel for the local decoded output. is multiplied by the prediction coefficient (α ₂ = 1/4) in adder 6, and the output of adder 6 is sent to adder 4 via FF5.
By inputting it together with the output of quantizer 3,
As the output of the adder 6, a prediction loop is formed to obtain a planar predicted value by adding the predicted output corresponding to a different pixel in a line in the past than the previous value to the previous value predicted output, and this predicted output signal value subtracter 1
The input PCM signal value is subtracted from the input PCM signal value by FF2 and then input to the quantizer 3. In this example, the past three pixels (the previous pixel, the corresponding pixel of the previous line, and the one pixel before that) are input to the quantizer 3. Quantized DPCM plane predicted from signal values corresponding to 3 pixels)
A signal is now output from the quantizer 3.

In the above prediction loop, the first prediction loop for predicting the previous value and the second loop (plurality) for prediction using different pixels of a line further past than the previous value are combined by the adder 6. You can see that they are connected.

Next, to explain a general case using FIG. 4, the local decoded signal value of the output of the adder 4 and the value obtained by delaying the local decoded signal value of the output of the adder 4 and two or more pixels on the same line before the Locally decoded signal value (in the past in terms of scanning), 1 of the same frame or the same field
Multipliers 7, 8, ..., 9 and the prediction system α ₀ ,
Multiply by α ₁ , α ₂ , ..., α _o , add these multiplication results in an adder 6 to obtain a predicted signal value, and subtract this signal value from the input PCM signal in a subtracter 1.
The signal is delayed by one sampling period in the FF2, quantized in the quantizer 3, and output as a planar predictive DPCM signal.

[Problem that the invention seeks to solve]

However, the critical path that determines the operating speed (encoding processing speed) in this case is the subtracter 1, FF 2, quantizer 3, adder 4, and multiplier 7.
(12) is the loop of the adder 6, and there is a problem in that in order to increase the operating speed, a high-speed ECL device must be used, for example.

[Means for solving problems]

The above problem can be solved by using the prior value prediction high-speed DPCM encoder mentioned above in the earlier application by the present applicant.
This can be solved by extending it to a DPCM circuit.

In other words, the above-mentioned high-speed
First example of prior value prediction of DPCM encoder
A second adder is inserted on the output side of the first delay element of the prediction loop, and multiple pasts are delayed by two sampling periods (two pixels) or more based on the locally decoded value of the first adder. A third adder adds a plurality of predicted signal values obtained by multiplying the locally decoded signals by corresponding prediction coefficients, and inputs this output to the second adder via a third delay element. , forms a second prediction loop that outputs a second predicted value based on signal values past two sampling periods (two pixels) or more as the output of the third adder, and inputs the second predicted value to the difference signal output means. P.C.M.
As a signal, the output of the third adder is connected to the input PCM
This problem is solved by the high-speed DPCM circuit of the present invention in which the value subtracted from the signal is inputted via the fourth delay element.

[Effect]

In the case of the present invention, as mentioned above, it is based on the above-mentioned high-speed DPCM encoder of prior value prediction of the earlier application by the present applicant, and a 3-input 2-output digital-to-digital converter as in the embodiment thereof. and adder A
In the case where the difference signal output means is a combination of This is a loop of the second multiplier, which is faster than the conventional predictive DPCM encoder, and is a loop of the third multiplier from the output of the first delay element, which may be a critical path. A second adder that operates within the operating time of the quantizer is inserted into the path that passes through the quantizer, the 3-input 2-output digital-to-digital converter, and the adder A to the input of the second delay element. We focused on the fact that the DPCM circuit is not in the critical path, and configured the DPCM circuit using the solution described above.
Fast plane prediction even using ordinary devices
DPCM circuit can be realized.

〔Example〕

FIG. 2 is a block diagram of a high-speed plane prediction DPCM circuit according to an embodiment of the present invention, and FIG. 1 is a general block diagram of a high-speed DPCM circuit according to an embodiment of the present invention.

In the figure, 17 is a subtracter, 18, 21, 22 are FF delay elements, 19 is a 3-input 2-output digital-to-digital converter, 20, 23, 24, 25
is an adder, 26-30, 33-37 are multipliers, 3
Reference numerals 1, 32, 38, and 39 indicate delay circuits, and the same symbols represent the same functions throughout the figures.

To explain the case of plane prediction using FIG. 2 and comparing it with FIG. 3, the 3-input 2-output digital-to-digital converter 19, adder 20,
The DPCM circuit (excluding the adder 23) including the first prediction loop for previous value prediction consisting of the FF 2, the quantizer 3, the multipliers 33 and 34, the adder 24, the multiplier 35, and the FF 22 has the adder 20 Since it corresponds to adder A, the previous value prediction of the previous application by the applicant is
It is equivalent to the DPCM encoder, and subtractor 1 in Fig. 3,
Compared to the previous value prediction part of the DPCM circuit (excluding adder 6), which consists of FF2, quantizer 3, and the first prediction loop for previous value prediction (adder 4, multiplier 12, FF5), Since the 3-input 2-output digital-to-digital converter 19 operates faster than the subtracter 1, the circuit operates faster but at the same level.

Further, the local decoded signal value of one line before, which is delayed by the delay circuits 16 and 15 in FIG. Multiply the value by 1/4, FF
5 to the adder 4, and 2 sampling periods (2
Forming a second prediction loop for second prediction using past signal values (pixel minutes) and inputting
The point to be subtracted from the PCM signal is, in FIG. 2, by multiplying the local decoded signal value delayed by delay circuits 39 and 38, which is equivalent to delay circuits 16 and 15, by a prediction coefficient 1/4 by multipliers 37 and 36. The second predicted signal obtained by adding these signal values by the adder 25 is added to the first predicted signal.
The second prediction loop is formed by inputting the input to the adder 23 inserted into the prediction loop through the delay element FF21, and the second prediction signal is subtracted from the input PCM signal value by the subtractor 17. The subtracted output is input to the first input of a three-input, two-output digital-to-digital converter 19 via a delay element FF18, thereby making it equivalent.

In this way, the adder 23 inserted in the above-mentioned high-speed DPCM encoder of the earlier application by the present applicant
If the operating time of Via converter 19 and adder 20
Since the path leading to the input of FF2 is high-speed without reducing the operating speed, a high-speed DPCM circuit for planar predictive coding can be realized with a normal device.

Next, in a general case, a block diagram corresponding to FIG. 4 is shown in FIG. 1, with the adder 24
The local decoded signal value of the output of
Delayed local decoded signal value of two or more pixels before (past in terms of scanning) on the same line, delayed by delay circuits 31 and 32 in the same manner as 0 and 11, one or more lines of the same frame or the same field. The multipliers 29, .
The prediction coefficient prediction coefficients α ₁ , α ₂ , ..., α _o are multiplied by the prediction coefficients α 1 , α 2 , . Similarly FF2
1 to the adder 23, subtracted by the subtracter 17, and inputted to the 3-input, 2-output digital-to-digital converter 19 via the FF 18.

On the other hand, the multipliers 26 to 28 configure a planar high-speed DPCM circuit by multiplying by the prediction coefficient α ₀ .

In addition, in the case where the handled signal is 8 bits, 2's complement is used, and 1 bit is the sign bit,
3-input 2-output digital-to-digital converter 19
will be explained below.

3-input 2-output digital-to-digital converter 1
9 and the adder 20 (adder A), and the connection of each digit of the FF2 is shown in FIG.

Of the 8 bits of the signal, the 0th, 1st, . In FIG. 5, bit numbers 0, 1, . . . , 7 are shown attached to each digit.

3-input 2-output digital-to-digital converter 1
Each digit of 9 is a full adder for one digit, with carry input c as the first input, and two addition inputs as the second and third inputs.
There are three inputs. Each digit 19−
For 0 to 7, input A0 to 7 to the first input, and input A0 to 7 to the second input.
Input B0 to 7, C0 to 7 to the third input, and B0
7 and C0 to 7 for subtraction, an inverter is provided at each of the second and third inputs. As a result, for each digit, A+(-B)+(-C)=A-B-C
is calculated, and each digit is converted into two outputs: an addition result and a carry.

These two outputs for each digit are input to an adder 20 as shown. That is, the output of the addition result of each digit of the converter 19 is inputted to each corresponding digit, and the carry output is inputted to each digit one digit above the corresponding digit and added. At this time, one of the inputs of the adder of the least significant digit (LSB, bit number 0) and the carry input are set to H level "1" inputs. If it is set like this, the addition output (total) of the adder 20 will be A+(-B)
+(-C)=A-B-C, and as mentioned above, the calculation of the 3-input adder can be performed using the 3-input 2-output digital-to-digital converter 19 and the adder 20. [Effects of the Invention] As explained in detail, according to the present invention, a plane prediction method is used using a conventional device.
This has the effect of realizing a high-speed DPCM circuit that performs DPCM codes at high speed. Furthermore, if a high-speed device is used, there is an effect of further increasing the speed.

[Brief explanation of drawings]

Fig. 1 is a general block diagram of a high-speed DPCM circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of a high-speed DPCM circuit according to an embodiment of the present invention, and Fig. 3 is a general block diagram of a high-speed DPCM circuit according to an embodiment of the present invention. 4 is a general block diagram of a conventional planar predictive DPCM circuit, and FIG. It is a connection diagram. In the figure, 1, 17 are subtractors, 2, 5, 1
8, 21, 22 are FFs, 3 is a quantizer, 4, 6,
20, 23, 24, 25 are adders, 7 to 9, 12
~14, 26~30, 33~37 are multipliers, 19
is a 3-input 2-output digital-to-digital converter,
10, 11, 15, 16, 31, 32, 38, 3
9 indicates a delay circuit.

Claims (1)

[Claims] 1. A quantizer that quantizes a difference signal and outputs a quantized difference signal; a first multiplier that multiplies the quantized difference signal by a prediction coefficient; A first prediction loop that generates a first prediction signal by prediction, and a second prediction loop that multiplies the prediction signal by a prediction coefficient.
a multiplier; and a difference signal output means for generating a difference signal between the input PCM signal and the output signals of the first multiplier and the second multiplier. A second prediction loop that generates a second prediction signal based on one or more input signal values in the past than the previous value is added, and the first prediction signal and the first prediction signal are added to the first prediction loop. 2
An adder is inserted to combine the first and second prediction loops, and a subtracter is provided to subtract the second prediction signal from the input PCM signal. A high-speed DPCM circuit characterized in that a difference signal is input to a means for outputting a difference signal.