JPS5927144B2 - Differential encoding device for color television signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is particularly applicable to differential pulse encoding (differential pulse encoding) among apparatuses for encoding and decoding information for digital transmission.
ialPulseGodeModulation (hereinafter referred to as DPCM).

When a signal is encoded by DPCM, a well-known prediction method is the previous value prediction DPCM, in which a sample value at a previous sampling time is used as a predicted value for the next sampling time. On the other hand, as a method of directly differentially encoding an NTSC color television signal by frequency multiplexing the color signal using a subcarrier in the high frequency range of the luminance signal, prediction is also performed using sample values even earlier than the previous sampling time. Tokoro Takajiko DPCM
Moaro. In a DPCM that performs prediction using not only the previous sample value but also previous sample values, the prediction function, which is expressed by Z transformation, is a multimodal expression. Therefore, when configuring an encoding device using a high-order prediction function, the conventional configuration method in which the prediction filter that performs prior value prediction is replaced with a prediction filter that has the characteristics of the high-order prediction function is used.
When calculating the predicted value in the prediction filter, the prediction function is represented by a multi-vertical formula, so multi-stage addition processing is required. Therefore, when the sampling frequency becomes high, that is, the processing of the DPCM encoding circuit If the allowable time becomes shorter, problems arise such that the DPCM circuit configuration becomes impossible due to the increase in processing time, or even if it is possible, a sufficient operating margin cannot be secured. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-order DPCM device that can perform processing in a shorter time than conventional circuit configuration methods when performing DPCM using a high-order prediction function.

This will be explained in detail below using the drawings.

General VC. The DPCM encoder is the first when the prediction function is PZ) including the previous prediction DPCM and the high-order constellation
It consists of a circuit as shown in the figure.

In FIG. 1, block 101 is a delay element that delays the input signal by one sampling period D, or in other words, a register that operates with the sampling clock (hereinafter, delay element will be used in the sense of register).Essentially, Although not necessary, it is added for the sake of explanation below. Block 103 is a quantizer, and block 106 is a predictor whose transfer function is PZ.
When the signals of each part are represented by Z transformation, as shown in Figure 1, the input signal is X'Z), the prediction error signal is E), the quantized output signal is applied by E5 (21S), and the quantizer 103. If the resulting quantization noise is expressed as QO), the relationship between the human input signal XZ) and the output signal EV) is expressed by the following equation. Therefore Q.

-0, the transfer function between the input signal X'Z) and the quantized output EV) is 1-PZ). On the other hand, consider a DPCM encoder which can shorten the calculation processing time and is constructed from a double loop differential circuit having two prediction means 21 and 22 as shown in FIG. In Fig. 2, 204 is a molecularizer, 207 and 210 are prediction functions P(
2, P'22 predictors, 203, 208, 211 are delay elements that delay the signal by the sampling period D. Similarly, when expressed by z transformation, the input signal is XZ), the output signal of the subtracter 201 is E2 (7.), and the quantized output signal is E' (2).
, the output signal of the adder 206 is Y, (2), the adder 209
Letting the output signal of Y2 (2S) be the following relational expression from the inner differential circuit. Furthermore, the following relational expression is shown from the outer differential circuit.

The following equation is immediately derived from these equations (2), (3), (4), and (5). ) 1JLV1' Therefore, equation (6) is the input signal XZ) which is obtained by delaying the input signal X'2 by one sampling period using equation (1). This is equivalent to replacing the transfer function (1-PZ) with Z-1.

Here, P((Z).Z-1 becomes P1(Z), P2'(
．． If we replace Z) and Z-1 with PnuZ), the transfer function of the encoder shown in Figure 2 becomes (1-Pl2)(1-P2
Z). Therefore, the DPC shown in the circuit of FIG.
The M encoder is a DPCM circuit with the configuration shown in Figure 1, and the prediction function is P1(2)+P2Z)+P1(21S).
．． P2Z). However, P
l2, P2Z) is a function of the first degree or higher of the variable Z-1.
Here PlZ) is a linear only function of variable Z-1, P2Z
) is expressed by a function of only quadratic or higher order of the variable Z-1, the second
With the circuit configuration shown in the figure, the path that usually takes the longest time for calculation (hereinafter such a path will be referred to as a critical path) is the quantizer 204, adders 206 and 209, predictor 210, and subtracter 201. and 202 to return to delay element 203.

However, by restricting the prediction function P2Z) to only a function of second or higher order of the variable Z-1, the prediction function P2Z) of the predictor 210 can be a function of only one or higher order.
At least one delay element is inserted between the input and output of 10, and the critical path changes. The delay element here means a register, and if data is fetched every clock, that data is held for one sampling clock cycle and output, and the calculation time for the path from one delay element to the next delay element is When the time is shorter than one sampling period, the correct calculation result is taken into the next delay element. Therefore, calculation processing can be performed separately for each delay element. The processing performed within one sampling period time in the difference circuit of the outer loop includes the path from delay element 203 to the delay element in the predictor 210, and from the delay element in the predictor to the delay element 20.
The process will be divided into up to three passes. Therefore, the number of processing stages is reduced and the time required for processing is shortened. Since the prediction function of the predictor 210 is a function of only the first order or higher order of Z-1, the critical path of arithmetic processing from the input to the output of the predictor 210 consists of a delay element that performs a first order delay and a first order delay element. Multiplier and 1 to obtain predicted value using coefficients
The path passes through an adder that adds the predicted value sum of second-order or higher-order coefficients to the predicted value of the next coefficient, but the order of operation of the delay elements can be changed, for example, it can be placed after the multiplier. In this case, the outer loop path of the encoder configured as a double loop is the delay element 203, the quantizer 204, the adders 206 and 209, the multiplier in the predictor 210, the delay element, the adder, and the subtracter 201. and 202 to the delay element 20
This will return to number 3.

On the other hand, if the prediction function PlZ) is set as PlZ)=αZ−1 (α is a constant and usually α<1), the prediction function P′I of the predictor 207
CZ, ) is a constant of α, and the predictor 207 can be composed of a multiplier with a coefficient α, and the critical path of the inner loop is the quantizer 204, adder 206, multiplier (predictor 207),
This is a loop that passes through the subtracter 202 and returns to the delay element 203.

Normally, subtraction takes about the same or slightly longer processing time than addition, and quantization and multiplication take longer than addition.
Comparing the processing time of the two outer passes with the processing time of the inner pass, it is possible to ensure that the outer two passes do not exceed the processing time of the inner pass, and the inner pass has the maximum processing time. becomes a loop.

That is, the maximum processing time is the time required to perform one stage of quantization processing, one stage of addition, one stage of multiplication, and one stage of subtraction. This is the same as the number of processing stages of the previous value prediction DPCM. On the other hand, if the encoding process is performed with the configuration shown in FIG.
Z)-α. P! Even if it is transformed into the form shown by the function (2))), the number of processing stages of the predictor 106 requires one multiplication process of the coefficient α and one addition process, and the addition process is required compared to the configuration shown in FIG. It will be at least one step larger. In other words, when it is a function of only quadratic or higher orders of P2 (P2) or variable Z-1, the prediction function is P(!7.)-αZ-1+P2(Z)-
If αZ-1·P22 is used, the encoding processing time can be shortened by using the encoding apparatus having the configuration shown in FIG.

As is clear from the above explanation, the delay element 203
Quantizer 204 and adder 20 not in the locations shown in the figure
6, the processing time can be similarly shortened. In addition, regarding the state of calculation in each processing stage, in a quantizer, the output value is not determined unless the value of all bits of the input is determined, but in an adder or subtracter, calculation processing is performed from the lower bits, and the higher bits are processed. Since a carry or a boro is sent to the bit, the output value gradually becomes fixed from the lower bit to the upper bit with a time delay (in the case of normally used elements, the output value is determined by a certain number). (The processing is performed in bit units, for example, 4 bits, and a carry or a boro is output.)

Therefore, when an adder or subtracter for parallel processing is constructed using two or more elements, even if the upper bit is not determined in the processing of the adder or subtracter, if the input to the lower bit is determined, the processing can be completed. possible and the output value is determined. For this reason, when performing arithmetic processing, if the addition and subtraction processing is configured to be performed continuously, if the lower bits are determined by the output of the previous stage, the lower bits of the next stage can be processed even if the upper bits are not determined. In the past, when the prediction function was PZ)-αZ-1, a quantizer and a predictor were placed between the subtracter and the adder, respectively, in a circuit that performed predictive DPCM encoding of the previous value of PZ)-αZ-1. In the device of the present invention, the delay element 203 is placed before the quantizer 204 or between the quantizer 204 and the adder 206, as shown in FIG. Since the configuration is such that the processing of addition and subtraction (the α multiplier is configured using a subtracter in the form of 1-2-m) is performed continuously, the DPCM encoding process is Time is getting shorter. As described above, when the encoding device of the present invention performs DPCM using a high-order prediction function, the transfer function is the product (1-PlZ) of the transfer functions of two differential encoding circuits.
)(1-P2(7.)), the configuration is a double-loop differential encoding circuit with two prediction means as shown in FIG. Alternatively, it is a differential pulse encoding device including means for later delaying the signal by one sampling period.

If this encoding device is used, DPC using the conventional configuration method can be
Compared to the M encoding device, it is possible to reduce the processing time required for differential encoding in one sampling period.
An embodiment of the present invention will be described in the case of an encoding/decoding apparatus that directly performs DPCM on an NTSC color television signal using a high-order predictive filter.

As a method for directly encoding an NTSC color television signal, when the sampling frequency Fs is Fs-3fsc, P/(Z)αZ is one of the prediction filters that efficiently predicts the vicinity of the zero frequency and subcarrier Fsc. -1+βZ
-3-αβZ-4 prediction function is used to perform DPCM. α and β are constants, for example α=0.5, β
=1-2-N (N is a positive integer). The transfer function of the DPCM encoder using this high-order prediction function is H2-(1-
αZ-1) (1-βZ-3), and the prediction function is P1(2)-αZ-1,
This corresponds to the case where P22=βZ-3.

An embodiment of an encoding device having this transfer characteristic is shown in FIG. Sampling frequency FsO) The PCM signal is input to the subtracter 301, and the prediction function P2C! is sent from the shift register 312 which delays the input signal by one sampling period and outputs it. ! ．． ) and the predicted signal A is calculated.

The difference signal C output from the subtracter 301 is added to the subtracter 302 and is then added to the prediction function P1(2) sent from the multiplier 307.
1S), and the output prediction error signal is delayed by one sampling period by the shift register 303. The output of the shift register 303 is sent to a quantizer 304, where it is quantized with a predetermined quantization characteristic, and the quantized signal is sent to an adder 306 and a code converter 305. A code converter 305 converts the code of the quantized signal and sends it to the transmission path. The quantized signal delayed by one sampling period, which is the output of the quantizer 304, and the prediction signal B, which was delayed by one sampling period by the shift register 308, are added by an adder 306, and the output is sent to a subtracter. 1 for the difference signal C of the input of 302
A locally decoded signal delayed by a sampling period appears.

The output of adder 306 is sent to multiplier 307 and adder 309.
The predicted signal B for the next sampling time appears at the output of the multiplier 307. The alpha multiplier simply shifts the input signal one digit lower. The characteristics of the prediction filter whose prediction function is P, CZ, )=αZ−1 are realized by shift registers 303 and 308, adder 306, and multiplier 307. The locally decoded signal of the difference signal C output by the adder 306 and the predicted signal A delayed by one sampling period by the shift register 313 are added by the adder 309, and the output is A locally decoded signal delayed by one sampling period appears. The output of the adder 309 is delayed by one sampling period in a shift register 310, multiplied by β in a multiplier 311, and further delayed by one sampling period in a shift register 312, thereby being predicted by a prediction function P2Z)=βZ-3. However, the predicted signal A is being calculated. The output of the shift register 312 (prediction signal A) is sent to the subtracter 301 and the shift register 313.
sent to. The β21-2-N multiplier 311 can be easily constructed by subtracting from the input signal a signal obtained by shifting the input signal N digits lower. Each shift register operates at a clock frequency Fs. Similarly, in order to reduce processing time, the decoding device configures the decoding processing circuit to be the product of two DPCM decoding loops, and adds one stage of shift register between the two decoding loops. As a result, the processing time of the decoding circuit can be reduced by one adder stage compared to the case where the decoding circuit is configured with one loop that is normally used. FIG. 4 shows an embodiment of a DPCM decoding device using a high-order prediction filter.

The decoding device has a decoding loop having a prediction filter with a prediction function P1(2)-αZ-1 and a prediction function P22=βZ-3.
It is constructed in the form of a product of loops with predictive filters. A code inversion circuit 41 converts the code sent from the transmission path.
The signal is converted into a signal level corresponding to the quantization level quantized by the quantizer 304 and sent to the adder 42. The adder 42 combines the signal sent from the sign inversion circuit 41 with the multiplier 4
The decoded signal of the difference signal C is obtained by adding the predicted signal B sent from the input signal C.4. The decoded signal of the difference signal C is sent to the shift register 4.
3 and then sent to a multiplier 44 to calculate and output a predicted signal B at the next sampling time. Further, the decoded signal of the difference signal C delayed by one sampling period by the shift register 43K is sent to the adder 45 and added to the prediction signal A sent from the shift register 49 to obtain a decoded signal. This decoded signal is delayed by one sampling period with respect to the input signal of the decoder. The decoded signal is sent to shift register 46. and shift register 46
, 48, 49 and the multiplier 47
)-βZ-3 pre-filter is used to calculate the predicted value A of the next sampling time. The shift register operates at a clock frequency Fs. Multipliers 44 and 47 are configured the same as multipliers 307 and 311 in FIG. Furthermore, when an NTSC color television signal is sampled at the sub-Nyquis sampling frequency Fs2fsc, PZ) = αZ-1 + βZ-2 - αβ is assumed to perform prediction efficiently.
There is also one that performs DPCM using the Z-3 prediction function.

α and β are constants, for example α20.5, β=1-2-
N (N is a positive integer).

In this case, the transfer function of the encoder is HeZ, )=(1−αZ
-1)(1-βZ-2), which makes the circuit configuration of FIG. 2 possible and corresponds to P1(2)-αZ-1, P2Z)-βZ-2. In other words, in the circuit described above, the prediction function P2Z) = βZ
The prediction filter for -3 may be changed to the prediction filter for prediction function P2Z)-βZ-2. Once P2α
DPC with prediction function of Z-1 force %-2-αβZ-3
The encoder circuit of M is the same as the encoder circuit shown in FIG.
It is constructed by removing the shift register 49 from the decoding circuit shown in the figure. Above, the prediction function is PZ)-αZ-1
βZ-3-αβZ-4 and P(Z)-αZ-1+βZ
-2-αβZ-3, ie PlZ)=αZ-1;
Examples were shown for the case of P2(Z)-βZ-3 or P2Z)=βZ-2.

As described above, according to the present invention, a DPCM device using a high-order prediction filter can perform encoding processing in a shorter processing time than an encoding device having a conventional configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a DPCM encoder according to a conventional method, FIG. 2 is a block diagram of a DPCM encoder according to the present invention, and FIG. 3 is a block diagram showing the configuration of a DPCM encoder according to an embodiment of the present invention. 4 are block diagrams showing the configuration of the DPCM decoder. 21, 22... Prediction means, 201, 202...
...Subtractor, 203, 208, 211...
Delay element, 204...Quantizer, 206, 20
9... Adder, 207, 210... Predictor, 301, 302... Subtractor, 303, 3
08, 310, 312, 313...Shift register, 304...Quantizer, 305...
・Sign converter, 306, 309...Adder, 3
07,311... Multiplier, 41... Sign inverse converter, 42,45... Adder, 43,4
6, 48, 49...Shift register, 44, 4
7... Multiplier.

Claims (1)

[Claims] 1 In a differential encoding device for a frequency multiplexed color television signal including a carrier color signal using a high-order measurement function, α is a positive constant, and P_2(Z) is a variable of only the second or higher order of the variable Z^-^1. If it is a function, the transfer function of differential encoding shown by Z transformation is (
It has a characteristic expressed as 1-αZ^-^1) (1-P_2(Z)), and the first
a first subtraction means for taking a difference between the output of the first subtraction means and a second prediction signal generated from the second prediction means; means for quantizing the prediction error signal generated by the subtraction means according to a predetermined rule; means for encoding and transmitting the quantized signal generated by the means; and a second subtraction means and the quantization means. means for delaying the signal by one sampling period after the interval or after the means for quantizing; 2 prediction means, and a first prediction means for decoding a local composite signal for the input signal from the local decoded signal and outputting a first prediction signal, A differential encoding device for color television signals characterized by shortened processing time.