JPH02138918U - - Google Patents

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Publication number
JPH02138918U
JPH02138918U JP4714189U JP4714189U JPH02138918U JP H02138918 U JPH02138918 U JP H02138918U JP 4714189 U JP4714189 U JP 4714189U JP 4714189 U JP4714189 U JP 4714189U JP H02138918 U JPH02138918 U JP H02138918U
Authority
JP
Japan
Prior art keywords
high frequency
gate
dual gate
control voltage
gain control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4714189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4714189U priority Critical patent/JPH02138918U/ja
Publication of JPH02138918U publication Critical patent/JPH02138918U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例の構成を示す回路
図、第2図は同実施例のソースと接地間のインピ
ーダンスのAGC電圧による変化を示すグラフ、
第3図は同実施例と従来例のAGC特性を比較す
るためのグラフ、第4図および第5図はこの考案
の他の実施例の構成を示す回路図、第6図は従来
の高周波増幅回路の構成を示す回路図、第7図は
従来の高周波増幅回路のAGC特性を示すグラフ
、第8図は従来の高周波増幅回路のソース容量と
最大減衰量との関係を示すグラフ、第9図はソー
ス容量の変化に伴うAGC特性の変化を示すグラ
フである。 2……デユアル・ゲートFET、7,9……コ
ンデンサ、8……可変容量ダイオード(可変容量
手段)、10,11,13,15……給電抵抗。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention, and FIG. 2 is a graph showing changes in impedance between the source and ground of the same embodiment depending on the AGC voltage.
Figure 3 is a graph for comparing the AGC characteristics of the same embodiment and the conventional example, Figures 4 and 5 are circuit diagrams showing the configuration of other embodiments of this invention, and Figure 6 is a conventional high frequency amplification. A circuit diagram showing the configuration of the circuit, Fig. 7 is a graph showing the AGC characteristics of a conventional high frequency amplifier circuit, Fig. 8 is a graph showing the relationship between the source capacitance and maximum attenuation of the conventional high frequency amplifier circuit, and Fig. 9 is a graph showing changes in AGC characteristics due to changes in source capacitance. 2... Dual gate FET, 7, 9... Capacitor, 8... Variable capacitance diode (variable capacitance means), 10, 11, 13, 15... Power supply resistor.

Claims (1)

【実用新案登録請求の範囲】 増幅素子として用いられるデユアル・ゲートF
ETの第1のゲートに入力信号が供給され、第2
のゲートに利得制御電圧が供給されて、利得が制
御される高周波増幅回路において、 前記デユアル・ゲートFETのソースと接地間
に、前記利得制御電圧に応じて容量が変化する可
変容量手段を設けたことを特徴とする高周波増幅
回路。
[Claims for Utility Model Registration] Dual gate F used as an amplification element
An input signal is provided to a first gate of the ET, and a second
In a high frequency amplifier circuit whose gain is controlled by supplying a gain control voltage to the gate of the dual gate FET, a variable capacitance means whose capacitance changes according to the gain control voltage is provided between the source of the dual gate FET and ground. A high frequency amplification circuit characterized by:
JP4714189U 1989-04-21 1989-04-21 Pending JPH02138918U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4714189U JPH02138918U (en) 1989-04-21 1989-04-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4714189U JPH02138918U (en) 1989-04-21 1989-04-21

Publications (1)

Publication Number Publication Date
JPH02138918U true JPH02138918U (en) 1990-11-20

Family

ID=31562818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4714189U Pending JPH02138918U (en) 1989-04-21 1989-04-21

Country Status (1)

Country Link
JP (1) JPH02138918U (en)

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