JPH02138437U - - Google Patents
Info
- Publication number
- JPH02138437U JPH02138437U JP1989047553U JP4755389U JPH02138437U JP H02138437 U JPH02138437 U JP H02138437U JP 1989047553 U JP1989047553 U JP 1989047553U JP 4755389 U JP4755389 U JP 4755389U JP H02138437 U JPH02138437 U JP H02138437U
- Authority
- JP
- Japan
- Prior art keywords
- bridge
- integrated circuit
- hybrid integrated
- circuit board
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989047553U JPH02138437U (ko) | 1989-04-20 | 1989-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989047553U JPH02138437U (ko) | 1989-04-20 | 1989-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02138437U true JPH02138437U (ko) | 1990-11-19 |
Family
ID=31563582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989047553U Pending JPH02138437U (ko) | 1989-04-20 | 1989-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02138437U (ko) |
-
1989
- 1989-04-20 JP JP1989047553U patent/JPH02138437U/ja active Pending