JPH02137215A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH02137215A JPH02137215A JP29129588A JP29129588A JPH02137215A JP H02137215 A JPH02137215 A JP H02137215A JP 29129588 A JP29129588 A JP 29129588A JP 29129588 A JP29129588 A JP 29129588A JP H02137215 A JPH02137215 A JP H02137215A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- manufacturing
- processes
- codes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000003550 marker Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor integrated circuit.
従来の半導体集積回路の製造においては、半導体基板を
複数枚トレーにいれ、前記トレーを管理単位として各製
造工程を進めるという方法がとられている。同一トレー
に入った複数枚の半導体基板は、同時に処理され1つの
ロットを形成している。この時、通常は前記トレーに添
付した管理札を前記ロットの工程の位置を識別するより
どころとしている。また前記トレーの番号をその目的に
使用する場合もある。さらに自動化の進んだ工場では、
半導体基板上に基板識別用のコードをマークし、このコ
ードを管理のよりどころとする場合もある。In the conventional manufacturing of semiconductor integrated circuits, a method is used in which a plurality of semiconductor substrates are placed in a tray and each manufacturing process is performed using the tray as a management unit. A plurality of semiconductor substrates placed in the same tray are processed simultaneously to form one lot. At this time, the control tag attached to the tray is usually used as a basis for identifying the process position of the lot. The tray number may also be used for that purpose. Furthermore, in highly automated factories,
In some cases, a code for identifying the board is marked on the semiconductor board, and this code is used as the basis for management.
管理札を使用する場合は前記ロットの処理されるべき工
程手順や処理条件は管理札に直接記述されている。作業
者は処理すべきロット(半導体基板の入ったトレーと管
理札)を受は取ると、この管理札を見ることによりその
処理条件を知り、基板を処理し工程の処理終了時に該当
工程が終了したことを管理札上に記録する。そして管理
札から次の工程の処理設備を知りロットを次工程に送る
。When a control tag is used, the process steps and processing conditions for the lot to be processed are written directly on the control tag. When a worker picks up a lot to be processed (a tray containing semiconductor substrates and a control tag), the operator learns the processing conditions by looking at the control tag, processes the substrates, and ends the process when the process is completed. Record what you have done on the management tag. The lot is then sent to the next process by knowing the processing equipment for the next process from the control tag.
一方トレーの番号や、半導体基板上にマークされたコー
ドを使用する場合は、処理されるべき工程手順や処理条
件、現在の工程位置などすべての製造ラインを制御する
ホスト計算機上に記録し、作業者はこれと対話すること
で処理条件を知り、処理を進めてゆく。On the other hand, when using tray numbers or codes marked on semiconductor substrates, the process steps to be processed, processing conditions, and current process positions are recorded on the host computer that controls all manufacturing lines, and the By interacting with it, the user learns the processing conditions and proceeds with the process.
上述した従来の半導体集積回路の製造方法は、管理孔に
よるもの及びトレーの番号による場合には、半導体基板
との対応が必ずしも保証されているとは限らず、作業者
の作業ミスや製造設備の故障などでしばしば対応関係が
ずれてしまう。これは半導体集積回路の製造工程は、異
なった工程で同一の設備を何度も使用すること、製造設
備は同時に多量の半導体基板を処理するため、複数のロ
ットが同時に設備に入って処理されること、設備で処理
するときには運搬用のトレーから専用のトレーに移し替
えること、などが主な原因となっている。またトレーの
番号や、半導体基板自体に書かれた識別コードを用い、
製造ラインのホスト計算機で管理する場合、計算機のマ
シンダウンは前もって予測不可能であり、計算機上のデ
ータと実物の不一致は避けられないものである。これに
よりロットの現工程が不明になるというトラブルが発生
する。また専用LSI(いわゆるカスタムLSI)では
、多品種小量生産が要求されており、−左半導体基板の
口径は大型化する一方であり、−度の生産で必要とされ
る半導体基板の枚数は減少しロット数は増大する一方で
ある。このような状況においては従来のように管理孔や
トレーの番号による管理は、管理が複雑になり、その点
からもミスが入りやすくなっている。In the conventional semiconductor integrated circuit manufacturing method described above, when using control holes and tray numbers, correspondence with the semiconductor substrate is not necessarily guaranteed, and there is a possibility of operator error or failure of manufacturing equipment. Correspondence often deviates due to malfunctions, etc. This is because the manufacturing process of semiconductor integrated circuits uses the same equipment many times in different processes, and because the manufacturing equipment processes a large number of semiconductor substrates at the same time, multiple lots enter the equipment and process at the same time. The main cause is the need to transfer the waste from transport trays to special trays when processing in equipment. In addition, using the tray number and identification code written on the semiconductor substrate itself,
In the case of management using a host computer on the production line, computer machine failure cannot be predicted in advance, and discrepancies between the data on the computer and the actual data are unavoidable. This causes a problem that the current process of the lot becomes unclear. In addition, dedicated LSIs (so-called custom LSIs) are required to produce a wide variety of products in small quantities, and the diameter of semiconductor substrates continues to increase in size, and the number of semiconductor substrates required for production is decreasing. However, the number of lots continues to increase. In such a situation, conventional management using management holes and tray numbers becomes complicated, and from this point of view, it is easy to make mistakes.
本発明の半導体集積回路の製造方法は、処理する半導体
基板上に少なくとも2工程以上の当該集積回路の製造工
程の処理設備及び処理条件を示す文字または記号を当該
工程の実行以前に刻印し、該当する工程の終了時に該文
字または記号をチェックオフする手段を有している。In the method for manufacturing a semiconductor integrated circuit of the present invention, characters or symbols indicating the processing equipment and processing conditions for at least two or more steps of manufacturing the integrated circuit are imprinted on the semiconductor substrate to be processed before the steps are performed. means for checking off the character or symbol at the end of the process.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)、(b)は本発明の第1の実施例を示す半
導体基板の平面図及び部分拡大平面図である。代表的な
半導体集積回路の製造工程であるSiを用いたCMOS
の製造工程では工程数は約300工程、使用設備は約4
0設備、各設備毎の処理条件は各設備毎に数条性〜数十
条件多くても99条件以下である。このため設備を表す
コードは2桁、条件を示すコードも2桁で十分である。FIGS. 1(a) and 1(b) are a plan view and a partially enlarged plan view of a semiconductor substrate showing a first embodiment of the present invention. CMOS using Si, a typical semiconductor integrated circuit manufacturing process
The manufacturing process involves approximately 300 steps and uses approximately 4 pieces of equipment.
0 equipment, the processing conditions for each equipment are several to several dozen conditions for each equipment, and at most 99 conditions or less. For this reason, a two-digit code representing equipment and a two-digit code representing conditions are sufficient.
従って採用するコードは4桁とし上2桁を設備コード、
下2桁を条件コードとする。これにより第2図(a>に
示す例のようにコード“1720”は、17が高電流イ
オン注入装置、20はボロンを50keVで2 X 1
015cra−2注入するといったように使うことがで
きる。本実施例では6インチのSi基板を用いる。この
場合周囲具は478 、77+nm 。Therefore, the code to be adopted is 4 digits, the first 2 digits being the equipment code,
The last two digits are the condition code. As a result, as in the example shown in FIG.
It can be used to inject 015cra-2. In this embodiment, a 6-inch Si substrate is used. In this case, the surrounding equipment is 478, 77+nm.
5mm内側の円周は447.36mmである。300工
程すべて半導体基板上に書くとする。使用する文字はS
E M I (Sem1conductor Equ
ipment andMaterials In5ti
tute )の標準文字とする。第2図(a)はこの文
字を拡大して書いたものであり、実際の寸法は第2[]
(b)にSEMI文字の外枠を用いて示すように幅が0
、406±0・025mm、高さが0.812±0.
0.25mm、ピッチは0.71±0.025 mmで
ある。従って4桁のコードは2.536mm X 0.
812mmで書くことができ、第1図に示すように5m
m内側の周と基板外周との間に、内側の周に接するよう
に放射状に本コードを工程順に書くと、間隔は0.30
4 mmであるから、内周側のピッチは帆812+0.
304−1.116 (mm)となり、300工程で
は1.116 X 300 = 334.8mmで書く
ことができ、充分に基板の表面外周上に書くことが可能
である。The circumference inside 5mm is 447.36mm. It is assumed that all 300 processes are written on a semiconductor substrate. The letter to use is S
E M I (Sem1conductor Equ
ipment and Materials In5ti
tute) as the standard character. Figure 2 (a) is an enlarged version of this character, and the actual dimensions are shown in Figure 2 []
The width is 0 as shown using the outer frame of the SEMI character in (b).
, 406±0.025mm, height 0.812±0.
0.25 mm, and the pitch is 0.71±0.025 mm. Therefore, the 4-digit code is 2.536mm x 0.
It can be written at 812mm, and 5m as shown in Figure 1.
m If you write this code radially in the process order between the inner circumference and the outer circumference of the board so that it touches the inner circumference, the interval is 0.30.
Since it is 4 mm, the pitch on the inner circumference side is 812+0.
304-1.116 (mm), and in 300 processes, it is possible to write 1.116 x 300 = 334.8 mm, which is sufficient to write on the outer circumference of the surface of the substrate.
また本実施例では半導体基板のオリエンテーションフラ
ット上基板内5mmの位置には品名を8桁で記入してい
る。これは設備が露光機の場合に、その品名と工程順か
ら使用するマスクを知ることができるからである。Further, in this embodiment, the product name is written in eight digits at a position 5 mm inside the substrate on the orientation flat of the semiconductor substrate. This is because if the equipment is an exposure machine, the mask to be used can be known from the product name and process order.
処理工程が一工程終了する毎に、該当コードをチェック
オフしてゆく。このチェックオフ及び最初の工程順のコ
ードのマークにはレーザマーカーを使用する。処理条件
のコードと実際の処理条件の詳細の対応は、該当設備の
コントローラに記憶させておけばよい。Each time one processing step is completed, the corresponding code is checked off. A laser marker is used to mark this check-off and first process order code. The correspondence between the processing condition code and the details of the actual processing condition may be stored in the controller of the relevant equipment.
第1の実施例では、全工程を書きかつチェックオフして
いたが、第2の実施例ではイオン注入、熱処理工程など
のパターンとして残らない工程でかつ再度処理の不可能
な工程にのみ本発明の適用する。In the first embodiment, all processes were written and checked off, but in the second embodiment, the present invention was applied only to processes such as ion implantation and heat treatment that do not remain as a pattern and cannot be reprocessed. apply.
半導体集積回路の製造工程では水洗や洗浄などのように
再度処理をしてもよい工程や、PR工程、エツチング工
程などのように基板上に形成されたパターンを見ること
でその工程が終了したか否かが判定できる工程がある。In the manufacturing process of semiconductor integrated circuits, there are processes such as water washing and cleaning that can be processed again, as well as PR processes, etching processes, etc., where it is possible to determine whether the process has been completed by looking at the pattern formed on the substrate. There is a process that allows you to determine whether or not it is possible.
このような工程には従来と同様の管理を行い、イオン注
入、熱処理工程には本方法を適用する。基板上にマーク
するコードやそのマーク方法などは第1の実施例と同様
とする。こうすることにより、全工程基板上の該当コー
ドをその都度チェックオフする必要がなくなり、かつ該
当基板の工程位置が不明となる事故をなくすことができ
る。Such steps are managed in the same way as conventional methods, and the present method is applied to ion implantation and heat treatment steps. The code marked on the board and the marking method are the same as in the first embodiment. By doing so, there is no need to check off the corresponding codes on all process boards each time, and it is possible to eliminate accidents in which the process position of the relevant board becomes unknown.
以上述べたように、本発明によると製造しようとする半
導体基板そのものに直接処理設備、処理条件に対応した
コードを書くことにより2作業者に対してその基板の工
程手順上の位置を知らしめ、作業ミスをなくし、ひいて
は不良ロットを減少させることができる。実施例では半
導体基板へのマーキングは、レーザマーカを用いて説明
したが、他の方法例えば文字のマーキングは露光、エツ
チングによる方法、チェックオフはダイヤモンドポイン
トなどを使うといった方法でも有効である。、またマー
キングする文字はSEMI文字を用いて説明したが他の
文字またはコードを用いても可能である。As described above, according to the present invention, by writing a code corresponding to the processing equipment and processing conditions directly on the semiconductor substrate to be manufactured, two workers are made aware of the position of the substrate in the process procedure, It is possible to eliminate work errors and reduce the number of defective lots. In the embodiment, a laser marker was used to mark the semiconductor substrate, but other methods are also effective, such as marking characters by exposure or etching, and checking off by using a diamond point. Furthermore, although SEMI characters have been used as marking characters, other characters or codes may also be used.
第1図(a)、(b)は本発明の第1の実施例を説明す
るための半導体基板の平面図及び部分拡大平面図、第2
図(a>、(b)は第1の実施例によるコードの例を示
す図である。
1・・・半導体基板、2・・・コード記入枠、3・・・
品名記入枠。1(a) and 1(b) are a plan view and a partially enlarged plan view of a semiconductor substrate for explaining the first embodiment of the present invention, and FIG.
Figures (a> and (b) are diagrams showing examples of codes according to the first embodiment. 1... Semiconductor substrate, 2... Code entry frame, 3...
Product name entry frame.
Claims (1)
板上に少なくとも2工程以上の当該集積回路の製造工程
の処理設備及び処理条件を示す文字または記号を当該工
程の実行以前に刻印し、該当する工程の終了時に該文字
または記号をチェックオフすることを特徴とする半導体
集積回路の製造方法。In a method for manufacturing semiconductor integrated circuits, characters or symbols indicating the processing equipment and processing conditions for at least two or more of the relevant integrated circuit manufacturing steps are imprinted on the semiconductor substrate to be processed before the execution of the relevant steps, and A method for manufacturing a semiconductor integrated circuit, characterized in that the character or symbol is checked off at the time of completion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29129588A JPH02137215A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29129588A JPH02137215A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02137215A true JPH02137215A (en) | 1990-05-25 |
Family
ID=17767038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29129588A Pending JPH02137215A (en) | 1988-11-17 | 1988-11-17 | Manufacture of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02137215A (en) |
-
1988
- 1988-11-17 JP JP29129588A patent/JPH02137215A/en active Pending
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