JPH02136902A - Data processor - Google Patents

Abstract

PURPOSE:To realize the highly accurate output control by setting the pulse output end timing based on the data which is previously set without saving the PC and the PSW into a stack space when an interruption process request is received. CONSTITUTION:A data memory 213 stores the process form information to designate a prescribed data process form. When a prescribed data process request is given to a CPU 200 from an interruption controller INTC 211, the CPU 200 interrupts an instruction executing process after detecting that a form designating means 220 points a prescribed data process. Then the CPU 200 operates a 1st comparing register 101, a capture register 105, and the memory 213 in order to control the generation of pulses to output ports P0 - P3. As a result, the output control is attained with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to pulse output in mechanical control, particularly to a data processing device that continuously outputs a plurality of pulses.

[Conventional technology]

Recently, microcomputers have been used for mechanical control. Basically, it is common to open and close valves, drive motors, etc. directly using PWM output pulses output from a microcomputer.

FIG. 7 shows an example of a pulse output pattern when four-tree pulse output is performed. - Numerically, pulse output control is
A method is used in which a pulse is made active (high level) after a certain time delay from the generation of some reference signal, and the mechanism is driven while the pulse output is active (high level). In this case, a certain time delay means the timing at which the pulse is output, and the period during which the pulse output is active (ie, active pulse @) means the control amount itself.

Hereinafter, a conventional pulse generator will be explained with reference to FIGS. 8 and 9. FIG. 8 is a block diagram of a conventional pulse generator, and FIG. 9 is a block diagram of conventional peripheral hardware. FIG. 8 shows the CPU 250, address bus 214
．． Data bus 205° INTC 240, program memory 212. Data memory 2132 Peripheral hardware 25
It consists of 1.

The CPU 200 includes an arithmetic logic unit (hereinafter referred to as ALU) 201. Temporary register 202゜General purpose register 203. Address buffer 204 (represented by AB in the figure), micro address (hereinafter referred to as μ address) generation unit 206゜μ'ROM 209. PC207,P
SW208. It is composed of a timing control section 225.

The INTC 240 also has an interrupt request flag 215 and outputs an interrupt request signal 218 to the timing control section 225. The timing control section 210
Outputs an interrupt request clear signal 2]7 to the TC240.

The INTC 240 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects the one interrupt source with the highest priority, and assigns the interrupt signal to that interrupt source. The corresponding interrupt request flag 215 is set. Although n interrupt request flags 2 and 5 are set when there are n interrupt requests, only one is shown in the figure. In addition, interrupt signals from external hardware, a priority level determination unit, and the like are not particularly shown.

Conventional interrupt processing is usually called vectored interrupt, and a vector table space is set in advance in a memory space, and this space stores entry addresses of interrupt processing programs corresponding to each interrupt source.

When a vectored interrupt occurs, a branch is made to the entry address corresponding to the interrupt source.

Next, the configuration of the peripheral hardware 251 will be explained using FIG. 9. Peripheral hardware 25] includes first to fourth down counters 901 to 90 based on clocks.
4, port register 909, and output port) PO to P3
The reference signal 0 corresponds to ports PO to P3.
~3 has been input. The reference signals O~3 are also IN
They are input to the TC 240 and make interrupt requests for PO to P3, respectively. The down counters 0 to 3 start counting operation when a count value is written from the data bus 205, and when a pollo occurs from the down counter, an interrupt request is generated to the INTC 240 and the counting of each down counter is stopped. It is configured to do this. In addition, the control of the output pulse is performed using the data bus 2.
From 05 onwards, this is done by directly writing the output level to the port register 909.

The explanation will be given below from the point where the reference signal 0 is generated at the port PO.

In normal instruction processing, the program address stored in the PC 207 is transferred to the address buffer 204, drives the address bus 214, and drives the program memory 2J.
, 2, the next instruction to be executed is fetched.

The fetched instruction is transferred to the μ address generation unit 206 via the data bus 205. μ address generation section 2
06 generates the address of μROM 209 from the instruction code. Thereafter, according to the instructions of the μ program for the instruction stored in the μROM 209, the general-purpose register 20
3. ALU201. Instructions are processed by manipulating the temporary register 202 and the like.

The INTC 240 constantly samples whether or not an interrupt request is generated from peripheral hardware, independently of the processing of the CPU 250, and if a request is generated, selects one request and issues an interrupt request corresponding to that source. flag 21
Set 5.

Now, when the reference signal 0 is input, an interrupt request is generated to the INTC 240, and the INTC 240 accepts the request. Output.

The last command of the μ program is a command for detecting whether an interrupt has occurred or not. When this command is issued, the timing control unit 225 sends an interrupt request signal 21
Sample the presence or absence of 8. If the interrupt request signal 218 is active, the interrupt request clear signal 217 is set to IN.
It is output to the TC 240 and the interrupt request flag 215 is cleared.

Next, connect the PC 207 and PSW 208 to the stack pointer (C
It is saved in the stack space pointed to by a register (not shown) set in the PU 250, and corresponds to the interrupt source stored in the vector table set at a specific address in the data memory 213. The entry address of the interrupt processing program is read and set in the PC 207 via the data bus 205. PC
The interrupt processing program starts execution from the program address newly set in 207.6 The interrupt processing program based on the interrupt processing request by reference signal 0 is the interrupt processing that specifies the timing to start pulse output from PO. ! The PU 250 writes data corresponding to the period from the generation of the reference signal 0 to the activation of the pulse output of the baud PO to the down counter 0.

In the processing of the instruction to terminate the interrupt processing program, the PO value saved in the stack space.

By returning the psw values to the PC 207 and PSW 208, respectively, processing is restarted from the next instruction at the time when the interrupt occurred.

Furthermore, when the above-described data is written by the CPU 250, the down counter 0 starts counting down in synchronization with this.

Next, the pulse output start timing during normal instruction execution is shown. When the poll signal 911 from the down counter O is generated, the INTC 240 accepts the interrupt request and outputs the interrupt request signal 218 to the timing control section 225, as described above.

When a command for detecting whether an interrupt has occurred is generated from the μ program, the timing control unit 225 samples the presence or absence of the interrupt request signal 218.

If the interrupt request signal 218 is active, an interrupt request clear signal 217 is output to the INTC 240,
Clear the interrupt request flag 215.

Next, the PC 207 and PSW 20g are saved to the stack space, the interrupt processing program branches to the entry address of the interrupt processing program corresponding to the interrupt source stored in the vector table set at a specific address in the data memory 213, and the interrupt processing program starts execution.

This interrupt processing program starts with the port register 90.
Read the contents of port register 9090 bit O
Since this is “0”, the interrupt processing starts the pulse output at PO (baud), and the port register 9
By setting bit 0 of 09 to “1”, the baud) PO
Set the output pulse from to high level and start pulse output.

In the processing of the instruction to terminate the interrupt processing program, the PO value saved in the stack space.

By returning the psw values to the PC 207 and PSW 208, respectively, the processing can be resumed with the next instruction at the time when the interrupt occurred.

Next is normal ()) life? , - During execution, once again, indicates pulse output end time]/get. When Borrow Shinsou 911 occurs from the rerun counter 0, the I
The NTC 240 accepts the interrupt request and sends an interrupt request signal; is output.

When the μ program generates a command for detecting whether or not an interrupt has occurred, the timing control unit 225 checks/pulls the presence or absence of the interrupt request signal 218.

If the interrupt request signal 218 is active, output 17 the interrupt request and serial signal 217 to the TNTC 240, clear the interrupt request flag 215, Next i: 'J' Star C207 and P S V = ' 208, ,, In the evening space, 3Fh M +, , Branch to the address of the interrupt processing program corresponding to the interrupt source stored in the vector table set at a specific address in the data/small memory 213. t
7. Interrupt processing program 1 starts execution This interrupt processing program first reads the contents of the f meet register 909 and executes baud) L== register 909
Since the bit 0 of the baud register 909 is ``0'', it is an interrupt process that lowers the pulse output at the port PO, and by setting the bit 0 of the baud register 909 to Low pulse: 1~, end pulse output f, 7..

During the processing of the instruction to terminate the interrupt processing program, the pC value was saved in the stack space.

By returning the PSW values to the PC 207 and PSW 208, respectively, processing is restarted from the next instruction at the time when the interrupt occurred.

Similar processing is performed from port P1 to port P3 in the same way. Control is done in a certain way.

[Problem J to be solved by the invention 1-7 Above 1. Ta. 1. The microcontroller accepts the reference signal for pulse output generation as an interrupt signal, and uses 1 and 5 in the interrupt processing program to make the pulse rise, fall, etc. Since we are controlling
As the number of times the reference signal is generated increases, the number of interrupt requests such as reference signal interrupt, pulse rise timing, and fall timing also increases17.
When returning from the interrupt processing program to the main processing, the process of saving the contents of the stack to the stack and returning the contents of the stack to the PC and PSW occurs frequently, and the CP used for saving and returning
U time becomes enormous. On the other hand, CI) U is not only responsible for pulse control, but also for other
-The CPTJ performs various miscellaneous tasks such as evening processing, etc., and as the output pulse frequency increases, the CPTJ time allocated to these main processing decreases, and in some cases, processing that cannot be done at all may occur. obtain. Therefore, control using modern high-speed, high-precision mechanical controllers has become extremely difficult.

With method A), the interrupt processing at each timing of pulse output rise and fall is controlled only by conventional software processing.
There will be a delay in the time it takes for the programming process to start, and a delay in the time it takes to write f/- data to the port. Since the device issues an interrupt processing request for each reference signal and down counter for the down counter, the increase in the reference signal and down counter due to the increase in the number of output pulses increases the INTC
As the number of interrupt request flags within the system and the number of interrupt request signal lines also increase, the wiring area between the INTC and peripheral hardware will also increase.As the amount of hardware for the entire system increases, product cost I. Raise it to 1-maikotona Zl.

[Means to solve the problem]

The present invention provides a CPU including a PC, a PSW, and a general-purpose register 8μROM, and an IN
In a processing device having a TC, a program memory, a data storage memory, and a peripheral circuit, the peripheral circuit includes a first timer, a first conveyor register, a capture register, a second timer, and a second timer. The INTC includes a function register, a plurality of output ports for pulse generation, and means for selectively generating set pulses for the output ports, and in addition to generating conventional interrupt processing requests, The device includes means for generating a request for predetermined data processing, and format indicating means for distinguishing between a conventional interrupt processing request and the request for the predetermined data processing, and a processing format for the predetermined data processing is stored in the data memory. Specified processing mode information is stored, and requests for specified data processing from INTC are sent to C
When issued to the PU, if the CPU detects that the format instruction means is instructing predetermined data processing, the CPU interrupts the instruction execution process and executes the instruction execution process with the first conveyor register according to the processing format information. , it has the feature of controlling pulse generation from multiple output ports by manipulating the capture register and data memory.

In this way, it is equipped with dedicated hardware that provides the pulse output start timing and dedicated hardware that provides the pulse output end timing. Therefore, when the pulse output start timing is received as an interrupt request signal,
By setting the desired pulse output end timing based on preset data without saving the PC and PSW to the stack space, it is possible to perform pulse output control for a plurality of pulse output ports.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

A first embodiment based on the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of peripheral hardware of the first embodiment, and FIG. 2 is a block diagram of a pulse generator showing the first embodiment.

The pulse generator of the present invention includes a CPU 200. address bus 214. Data bus 205. INTC 211, program memory 212. It is composed of a data memory 213 and peripheral hardware 221.

The CPU 200 has an ALU 201. Temporary register 2
02. General purpose register 203. Address buffer 204 (
(Represented by AB in the figure).

μ address generation unit 206. μROM209. PC207
, PSW208. It is composed of a timing control section 210.

The INTC 211 also includes an interrupt request flag 215 and a format designation flag 216.
10, the interrupt request signal 218 and the mode specifying means 2
Outputs 20. The timing control section 210 is an INTC
It outputs an interrupt request clear signal 217 and a form change signal 219 to 211.

The INTC211 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects the one interrupt source with the highest priority, and applies the interrupt signal to that interrupt source. The corresponding interrupt request flag 215 is set. Although n interrupt request flags 215 and mode specification flags 216 are each set when there are n interrupt requests, only one set is shown in the figure. In addition, interrupt signals from external hardware, priority determination units, etc.
Since it is not directly related to the gist of the present invention, it is not particularly illustrated.

The CPU 200 can process an interrupt request from the INTC 211 in two ways.

One is traditional vectored interrupt processing, and the other is
In the processing mode that is the gist of the present invention, when an interrupt occurs, the vector table is not referenced and the data memory 2 is
This is a mode in which predetermined data processing is executed based on processing mode information preset to a specific address in 13.

Hereinafter, this predetermined data processing will be referred to as a macro service.

The designation of a vectored interrupt or a macro service is made using the type designation flag 216. When the CPU 200 sets the type designation flag 216 to "0", it is designated as a vectored interrupt, and when it is set to "1", it is designated as a macro service. Ru.

The dedicated hardware configuration according to the present invention and the flow of pulse output processing by the macro service will be described below. First, the first factor is the structure of the peripheral hardware 221.

Peripheral hardware 221 includes clock-based free-running timers 100 . Hump pair register 101 that performs comparison operation with respect to free running timer 100
(written as COMPO in the figure) and 102 (written as COMPO in the figure)
Pl) and 1o3 (written as COMP2 in the diagram) and 1
04 (written as COMP3 in the figure), capture register 1o5 (written as CAP in the figure), bit selection register 109 (written as SR in the figure), event counter 1o6 whose count source is external pulse T1, event counter 106 Conveyor register 107 (COMPA written on the left in the figure) that performs a comparison operation with respect to output capo) PO~
Consists of P3.

The coincidence signals 111, 112, 113, 114 are output from the conveyor registers 101, 102, 103, 104, respectively, and the coincidence signal 1.17 is output from the conveyor register 107.
is output from. The capture register 105 stores the value of the free running timer 100 in synchronization with the output of the match signal 117. The clock input to the free running timer 100 has a resolution within the control tolerance range.

Furthermore, an external input signal T1 indicating the amount of change in an external event (for example, a signal indicating the rotation angle of the crankshaft) is input to the event counter 106 as a count source, and the conveyor register 107 receives this event counter 1 as a count source.
．． 06 and generates a match signal 117. Event counter 106 is cleared by external clear signal 130. The external clear signal 130 corresponds to the reference signal described in the conventional example, and is configured to clear the timer 106 every time the reference signal is generated.

Next, processing type information that specifies the processing type of the macro service of the present invention will be explained. FIG. 3 shows the structure of processing mode information. The processing mode information is placed at a specific address in the data memory 213, and the processing mode information in this example is composed of a 1-byte header section having a channel pointer and an 8-byte macro service channel pointed to by the channel pointer. Ru.

The macro service channel in this example is configured assuming output of four pulses, and is composed of word data (for PO/-P3) specifying the pulse width.

Word data 0, 1, 2.3 are ports PO, P, respectively.
I, P2. Word data that defines the pulse width of the pulse output output from P3.Based on this value, the conveyor registers 101, 102, 103 and 104 reset the pulse outputs of PO, PL, P2 and P3, respectively. Word data to be.

Stored by the CPU 200.

The macro service in this example is activated by the match signal 117 from the conveyor register 107.

Before the macro service is started, the CPU 200 initializes the macro service channel and hardware. Further, in the bit selection register 109, in order to specify that the port to which a pulse should be output first is PO, only the bit corresponding to port PO is set to 1 and the other bits are set to 0.

Furthermore, the conveyor register 107 that performs a comparison operation with respect to the event counter 106 contains data corresponding to the period from the reference signal generation to the pulse rise timing in the vector interrupt processing program that is activated at the timing at which the external clear signal 130 is generated. Set by CPU 200.

FIG. 4 is a flowchart showing the macro service of this example, which is actually μ program controlled.

Hereinafter, with reference to FIGS. 1 to 4 and 7,
A detailed explanation of macro services will be provided.

First, when a match signal 117 is generated from the fun pair register 107 to the event counter 106r, 5
From the initial value of R109, only the RS flip-flop of port PO is set, and the output pulse from port PO becomes high level. At the same time, according to coincidence M No. 117,
The value of free running timer 100 is stored in capture register 105. Also, the match signal 1]7 generates an interrupt request to INTC2i1.

When the INTC 211 accepts the match signal 1170 interrupt request, the interrupt request flag 215 corresponding to this source is set.
is set, and the interrupt request signal 218 is activated.

Timing control unit 210 samples request signal 218 at the end of command processing, and since it is active, samples form specifying means 220. When the format specifying means 220 detects "1" indicating macro service, the PC
207, μROM209 while retaining PSW208
Generates a macro service processing entry address and starts the macro service.

Thereafter, processing is performed according to the macro service's μ program instructions. The processing flow will be explained along the flowchart of FIG.

First, the header of the macro service using the match signal 117 as an interrupt source is read from a specific address in the data memory 213, and the position of the macro service channel is detected.

Next, the contents of 5R109 are read, and since the bit indicating baud (PO) is set to 1, word data 0 in the macro service channel corresponding to this bit and the contents of the capture register 105 are read using the ALU 201. The result is stored in the conveyor register 101.

Next, execute the left shift processing of 5R109, and
Set only the bit corresponding to .

Next, in response to a command from the μ program, the timing control unit 210 outputs an interrupt request clear signal 217 to the INTC 211, resets the interrupt request flag 215, and ends the macro service processing.

When the macro service processing is completed, the timing control unit 2
10 holds Teita Pc 207, P 5W208
Resume normal instruction processing from the value of .

After this, the match signal 111 from the conveyor register 101
The 0 generation resets the RS flip-flop of PO, and the pulse output to PO ends. At this time, no interrupt request is generated to the INTC 211 due to the coincidence signal 111.

Also, after the above macro service processing, the clear signal 130
Upon occurrence of , the event counter 106 is cleared and vectored interrupt processing occurs. Conveyor register 1 again
Lever and conveyor register 10 that match the value set in 07
7 will generate a match signal 117.

The above process is repeated in exactly the same way from PO to P3. In the macro service activated by the set timing for port P3, as in the macro service processing described above, the contents of 5R109 are first read, and since the bit indicating baud P3 is set to 1,
Word data 3 in the macro service channel corresponding to this bit and the contents of the capture register 105 are
The LU 201 is used to perform the addition and the result is stored in the conveyor register 104.

When the left shift processing of 5R109 is executed in the fourth macro service processing, a shift out from 5R109 occurs, so the timing control unit 21
0 outputs the format change signal 219 to the INTC 211 and resets the format designation flag 216.

Since the interrupt request flag 215 is set and the format designation flag 216 is reset, the INTC 211 issues a normal vector interrupt request to the CPU 200 and executes the vector interrupt processing described above.

The interrupt processing program is started when the pulse outputs of the four ports have completed one cycle, resets the SRI 09 to the initial state, and prepares for the pulse output from the port PO.

Although the pulse pattern shown in FIG. 7 has been described above, this macro service processing can be applied to any other configuration of pulse patterns.

Further, in this embodiment, after being cleared by the external clear signal 130, the event counter 106 counts a predetermined number of external pulses T1 set in the conveyor register 107, and then the conveyor register 107 receives a coincidence signal 117.
is generated and the pulse output from a predetermined port is set to high level. This is based on a certain reference signal (external clear signal 130
), the specified physical JL (value of conveyor register 107 * external pulse T) until the pulse output is set to high level.
This means that I) is being measured. On the other hand, the clock-based free-running timer 100 and conveyor registers 101, 102, 103, 104 count clocks for word data assigned to each conveyor register after the conveyor register 107 generates a match signal 117. Then, the pulse output from the port is set to four levels. This is a predetermined time in units of clocks, which is only the width of the high level of the pulse output! (War V data 0, 1.2, 3) is being measured.

Furthermore, in this embodiment, when shift out occurs as a result of shift processing from 5R109, a vector interrupt is generated and initialization is performed using the interrupt processing program. This setting was made to provide the correction timing when such correction processing becomes necessary, but in a system that does not require such correction processing, rotate processing is performed on 5R109, and the shift out from bit 3 is set. If the macro service processing is changed so that the signal is transferred to bit 0, complete pulse output control can be achieved by just the macro service processing without generating a vector interrupt.

In this embodiment, the pulse output start timing is set to T1.
We have shown a method of controlling the pulse output end timing using a clock system, but in Fig. 1,
Free running timer 100 as an event counter,
Furthermore, if the event counter 106 is set as a free running timer, the system is reversed, and selection can be made according to the application.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram of peripheral hardware of the second embodiment, and FIG. 6 is a block diagram of a pulse generator showing the second embodiment.

The pulse generator of the present invention includes a CPU 590. address bus 214. Data bus 205. INTC511, program memory 212. It is composed of a data memory 213 and peripheral hardware 521.

The CPU 590 has the ALU 201. Temporary register 2
02. General purpose register 203. Address buffer 204 (
(represented by AB in the figure), μ address generation unit 20
6. μROM209. PO207, PSW208. It is composed of a timing control section 580.

The INTC 511 also includes an interrupt request flag 215 and a format designation flag 216.
80, the interrupt request signal 218 and the mode specifying means 2
Outputs 20. The timing control section 580 is an INTC
511, outputs an interrupt request clear signal 217 and a form change signal 219.

The INTC541 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects one interrupt source with the highest priority, and interrupts that interrupt. Set the interrupt request flag 215 corresponding to the source. Although n interrupt request flags 215 and mode specification flags 216 are each set when there are n interrupt requests, only one set is shown in the figure. Further, interrupt signals from external hardware, a priority order determining section, and the like are not particularly illustrated because they are not directly related to the gist of the present invention.

Peripheral hardware 521 includes a clock-based free running timer 500 and a conveyor register 501 that performs a comparison operation with respect to the free running timer 500.
(written as COMPO in the figure) and 502 (written as COMPO in the figure)
PI), 503 (written as COMP2 in the figure), and 5
04 (written as COMP3 in the figure), capture register 505 (written as CAPA in the figure), bit selection register 509 (written as SR in the figure), event counter 506 whose count source is external pulse T1, event counter 506 Conveyor register 5 that performs comparison operation against
07 (written as COMPA, !: in the figure), a capture register 508 (written as CAPE in the figure) that stores the value of the event counter 506 at a predetermined timing, and an output register 508 (written as CAPE in the figure).
) It consists of PO to P3.

Match signals 511, 512, 513, and 514 are output from conveyor registers 501, 502, 503, and 504, respectively, and match signal 517 is output from conveyor register 507. Capture register 505 captures match signal 11
When 7 is output, the value of the free running timer 500 is stored in synchronization with this. Capture register 508
When external reference signal 535 is input, it stores the value of event counter 506 in synchronization with this. The clock input to the free running timer 500 has a resolution within the control tolerance range.

Furthermore, an external input signal T1 indicating the amount of change in an external event is inputted to the event counter 506 as a count source, and the conveyor register 507 performs a comparison operation on this event counter 506 to generate a coincidence signal 517. .

The operation of controlling the activation of the macro service and the pulse output by the coincidence signal 517 is the same as that of the coincidence signal 117 in the first embodiment.
Since this is the same as the macro service startup and pulse output control, the explanation will be omitted, and the operations among the event counter 506, conveyor register 507, capture register 508, and external reference signal 535 will be explained here.

First, the capture register 508 receives the external reference signal 535.
is input, event counter 5 is synchronized with this.
Stores the value of 06. The external reference signal 535 also serves as an interrupt request signal for requesting update of the setting data of the conveyor register 507, and is input to the NTC 511 to issue an interrupt processing request for updating the conveyor register 5070.

Assuming that the interrupt processing for this interrupt processing request is performed by vectored interrupt processing, the CPU 59
0 executes addition of the contents of the capture register 508 and predetermined pulse width data corresponding to the period from the generation of the external reference signal 5350 to the pulse output start timing,
A process of storing the addition result in the conveyor register 507 is executed.

After this, the conveyor register 507 and the event counter 5
06, the conveyor register 507 generates a match signal 517.

As described above, instead of clearing the event counter 106 by the external clear signal 130 and generating the match signal 117 in the conveyor register 107 in the first embodiment, in this embodiment, the capture register 508 is used to interrupt the conveyor register 507. A match signal 517 can be generated by updating the match signal 517, and the pulse output from the port controlled by this match signal 517 can be controlled as in the first embodiment.

Other operations are exactly the same as those in the first embodiment, so detailed explanations will be omitted.

〔Effect of the invention〕

As explained above, in the present invention, the interrupt at the pulse output start timing is processed by the macro service and no vectored interrupt request is generated.
, When saving the PSW to the stack or returning from the interrupt processing program to main processing, the contents of the stack are saved to pc, p.
Processing to return to sw does not occupy CPU time.

In addition, in recent mechanical controls that require high-speed, high-precision control, highly accurate pulse output control has become necessary.
By directly controlling the port and generating output pulses using the match signal from the conveyor register that gives the pulse output end timing, there is no time delay between the occurrence of an interrupt factor and the start of the interrupt processing program, and no delay to the port. Since the output pulse width can be controlled with a minimum error without any delay due to data writing time, the output pulse width can be adjusted with high precision.

In addition, the pulse generator of the present invention uses a dedicated event counter and a pair of compare registers to give the pulse output start timing for each cylinder, and a plurality of compare registers to give the pulse output end timing for each port. Therefore, even if the number of pulse outputs increases to 6 or 8, exactly the same control can be achieved by simply increasing the number of conveyor registers that provide pulse output end timing and the number of word buffers in the macro service channel. . Furthermore, INTC
Since the interrupt request signal for the input signal is always generated by a single conveyor register, there is no increase in hardware such as the interrupt request flag in the INTC or the wiring area between the INTC and peripheral node 1 hardware. Therefore, the pulse generator of the present invention can easily cope with an increase in the number of cylinders by adding a minimum amount of hardware, making it possible to configure an extremely economically advantageous system, and reducing the CPU and peripheral circuits. It can also be fully applied to a single chip integrated on a single substrate.

Furthermore, the pulse output start timing and pulse output end timing may be controlled by the system using T1 and the system using the clock, or by the system using the clock and the system using T1. Pulse output control is possible, and by selectively using these two control systems, pulse output control can be performed depending on the situation, allowing for great flexibility in configuring the system.

[Brief explanation of the drawing]

Figure 1 is a peripheral hardware configuration diagram in the first embodiment, Figure 2 is a system configuration diagram in the first embodiment, and Figure 3 is a system configuration diagram in the first embodiment.
Figure 4 is a macro service processing form information configuration diagram in the first embodiment, Figure 4 is a macro service processing flowchart in the first embodiment, and Figure 5 is a peripheral node diagram in the second embodiment. 6 is a system configuration diagram in the second embodiment, FIG. 7 is a pulse output pattern diagram from a port, and FIG. 8 is a system configuration diagram in a conventional example.
FIG. 9 is a diagram showing the configuration of peripheral hardware in a conventional example. 100.500...Free running timer,
106.506...Event counter, 101
．． . 102.103,104,107,501,502゜5
03.504,507...Conveyor register,
105.505,508...Capture register, 109.509...Bit selection register S
R. 11.1,112,113,114,117,511゜512.503,514,517... Match signal, 200.250,590... CPU, 201
...ALU, 202...Temporary register, 203...General-purpose register, 204...
...Address buffer, 205...Data bus, 206...μ address generation unit, 207...
...PC, 208...PSW, 209...
...μROM, 21.0,225,580...
...Timing control section, 211, 240, 511...
...INTC. 212...Program memory, 213...
...Data memory, 214...Address bus,
215... Interrupt request flag, 216...
...Format specification flag, 217...Interrupt request clear signal, 218...Interrupt request signal, 219
...Form change signal, 220... Format specifying means, 130... External clear signal, 535.
...External reference signal, 221, 251. ! Ml...
...Peripheral hardware, 901,902,903°904...Down counter, 911,912°913.914...Pollow signal, 909...
...port register.

Claims (1)

[Claims] A central processing unit that includes a program counter that holds the execution address of an instruction, a means for holding the execution state of the program, a general-purpose register as a high-speed storage means, and a microprogram ROM, and an interrupt that asynchronously issues a processing request to the central processing unit. In a data processing device including a request generation circuit, a program memory, a data memory, and a peripheral circuit, the peripheral circuit includes a first timer and a compare register that compares the first timer; a capture register that captures the value of the first timer at a predetermined timing; a second timer; a compare register that compares the second timer; a plurality of output ports for pulse generation; means for selectively generating a set pulse for a port; Processing mode information specifying a processing mode of the predetermined data processing is stored in the data memory, and a request for the predetermined data processing is generated from the interrupt request generation circuit to the central processing unit. Then, if the central processing unit detects that the format instructing means instructs the predetermined data processing, the central processing unit interrupts the instruction execution processing, and executes the first comparison according to the processing format information. A data processing device, characterized in that pulse generation from the plurality of output ports is controlled by manipulating a register, the capture register, and the data memory.