JPH02136824A - Liquid crystal panel driving circuit - Google Patents
Liquid crystal panel driving circuitInfo
- Publication number
- JPH02136824A JPH02136824A JP29151288A JP29151288A JPH02136824A JP H02136824 A JPH02136824 A JP H02136824A JP 29151288 A JP29151288 A JP 29151288A JP 29151288 A JP29151288 A JP 29151288A JP H02136824 A JPH02136824 A JP H02136824A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- gate
- voltage
- crystal panel
- positive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 43
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 2
- 206010047571 Visual impairment Diseases 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 10
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 235000021170 buffet Nutrition 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000000976 ink Substances 0.000 description 1
- AHLBNYSZXLDEJQ-FWEHEUNISA-N orlistat Chemical compound CCCCCCCCCCC[C@H](OC(=O)[C@H](CC(C)C)NC=O)C[C@@H]1OC(=O)[C@H]1CCCCCC AHLBNYSZXLDEJQ-FWEHEUNISA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上のＩｌｌ用分野１
本発明は薄ＩＩＩ トランジスタ素子を用いた、いわゆ
るアクデイプマトリックス液晶パネルの駆動回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field 1] The present invention relates to a drive circuit for a so-called ac-deep matrix liquid crystal panel using thin III transistor elements.
［従来の技術１
アクティブマトリックス方式の液晶パネルは、最初ボケ
ッｌ−Ｔ Ｖ用のデイスプレィとし７て商品イヒが図ら
れ、現在は各種計器、計１Ｉｌｌ１機器のデイスプレィ
、型番こプロジェクションＴＶ、ビューフ戸インク等へ
の幅広い応用が実施、検討されている。[Conventional technology 1] Active matrix type liquid crystal panels were first used as displays for blurry TVs, and are now used as displays for various instruments, displays for a total of 111 devices, model number 1 projection TVs, and Buffet inks. A wide range of applications are being implemented and considered.
第３図（ａ）はＮ型薄股トランジスタ素子を用いた液晶
パネルの等価回路図である。FIG. 3(a) is an equivalent circuit diagram of a liquid crystal panel using N-type thin transistor elements.
図において、３０１はゲート１忙３０２はソース領域、
３０３はドレインＧｎ域、３０４は透明画素電極、３０
５は対向基扱電陽であり基（デミ位を与＾る。３０Ｇは
液晶層である。ソース線がら入力されＩＩＩＩＩ−ラン
ジスタを介し、Ｍ記透明画累電榛３０４に印加された（
３号電圧と、ｉｉｉ記対向基板；極３０５の基４１！電
位との電圧差により液晶層３０６のオンオフを制御卸し
、光の透過量を制御卸することにより、表示を実現する
。In the figure, 301 is a gate 1 region, 302 is a source region,
303 is a drain Gn region, 304 is a transparent pixel electrode, 30
5 is an electric current handling the opposite group and gives a demi position. 30G is a liquid crystal layer. It is input from the source line and applied to the M transparent image accumulation electric field 304 via the III transistor (
No. 3 voltage and iii counter substrate; base 41 of pole 305! Display is realized by controlling the on/off state of the liquid crystal layer 306 and controlling the amount of light transmitted through the liquid crystal layer 306 based on the voltage difference between the potential and the potential.
第２図は、ｌｉｔに用いられでいる。ゲート印７１１１
電圧、及びソース印加Ｎ圧の経略変化を示すタイミンク
図である。（図は画面中央部の薄膜トランジスタの例で
ある。）液晶はその特性上、交流駆動する必要があり、
よってソース線には、対向電極電位に対し、上側のフィ
ールド（正フィールド）の電圧と下側のフィールド（負
フィールド）の電圧を交互に印加する。この切換りの周
期を液晶駆動交流化周期と呼ぶ。画素毎１引３０４には
対応する。１ＩＩｎＩ＋−ランジスタのゲート３０１の
電圧がオンレベル（選択レベル）である時のソース線信
号が印加され１次にゲートが選択レベルとなるまでの間
（ゲートが非選択レベルである間）、前記ソース領域３
０２とドレイン領域３０３が高抵抗となることにより、
信号レベルを保持し、画像情報を表示する。FIG. 2 is used for lit. Gate mark 7111
FIG. 2 is a timing diagram showing approximate changes in voltage and source applied N pressure over time. (The figure shows an example of a thin film transistor in the center of the screen.)Due to its characteristics, liquid crystals must be driven with alternating current.
Therefore, an upper field (positive field) voltage and a lower field (negative field) voltage are alternately applied to the source line with respect to the counter electrode potential. This switching period is called the liquid crystal drive alternating current period. This corresponds to the 1-pull-by-pixel 304. 1IInI+- When the voltage at the gate 301 of the transistor is on level (selection level), the source line signal is applied until the gate becomes the selection level (while the gate is at the non-selection level). Area 3
02 and the drain region 303 have high resistance,
Maintain signal level and display image information.
［発明が解決しようとする課題］
以下に従来技術の問題点を述べる。第３図（ｂ）は薄膜
トランジスタのゲート３０１、ソース領域３０２間型位
差Ｖ。、と、ソース領域３０２とドレイン領域３０３間
に一定電圧（以後ｖ０３）を印加した時、同ｆｉｌ域間
を流れる電流量の関係を示すグラフノー例である。Ｉ
ｏｓはＶａｍＯＶ−１゜Ｖの範囲で急激に上昇し、更に
高電圧側でも飽和せず徐々に増加する。又逆バイアス側
でも、その機構は明らかではないが、逆バイアスを高く
すると電流量Ｉｔ’ｓも急激に増加する。これを、実際
の駆動状態にあてはめて考えると、負フイールドゲート
オン状態でのＶ。が１６Ｖ〜２０Ｖであるのに対し、正
フイールドゲートオン状態でのＶ。ＳはｌＯ〜１４Ｖと
なる。すなわち第３図（ｂ）より、正フィールドでのソ
ースドレイン間オン抵抗が約４ＭΩ（Ｖ、、＝４Ｖ、Ｉ
。、＝ Ｉ Ｏ−’Ａ） テするのに対し、負フィー
ルドでは、約４００にΩとなる。この差は、比較的小型
の（少雨素数の）液晶パネルの場合には問題とならない
が、ゲートのぶ択期間の短かい、大型の（高精細の）液
晶パネルの場合、薄膜トランジスタを介し、画素電極３
０４に印加される電圧のソース領域３０２に加えられた
印加電圧（信号電圧）に対する割合が、負フィールドに
比べ正フィールドでは顕著に低くなってしまう０次に選
択期間に画素電極３０４に印加した電圧を保持する特性
について述べる。第２図より、負フィールドではゲート
オフ時Ｖ、、＝Ｏ〜４Ｖ、正フィールドではＶａｓ”
６〜 ＩＯＶであるので、Ｊ膜トランジスタのオフ抵
抗は、負フィールドでは４ＴΩであるのに対し、正フィ
ールドでは最高４０ＧΩとなってしまう。つまり対向電
極３０５の電位を基準電位として、正フイールド時には
負フイールド時に比べ、（８号電圧を画素毎極３０４に
印加しに＜＜、又印加した電圧をリークしやすいという
特性をもつ。結果、対向電極電位に対し、画素電極電位
は対称性を失い、液晶層３０６に直流成分が印加される
ことになる。この状態が顕著な場合、液晶パネルは残像
、表示ムラ、その他の表示不良をひき起こすことが報告
されており、この問題の解決が液晶パネルの重大な課題
の一つとなっている。[Problems to be Solved by the Invention] The problems of the prior art will be described below. FIG. 3(b) shows the potential difference V between the gate 301 and source region 302 of the thin film transistor. , is an example graph showing the relationship between the amount of current flowing between the same fil regions when a constant voltage (hereinafter referred to as v03) is applied between the source region 302 and the drain region 303. I
os increases rapidly in the range of VamOV-1°V, and gradually increases without being saturated even on the higher voltage side. Also, on the reverse bias side, although the mechanism is not clear, when the reverse bias is increased, the current amount It's also increases rapidly. Applying this to the actual driving state, V in the negative field gate on state. is 16V to 20V, while V in the positive field gate-on state. S is 10 to 14V. In other words, from FIG. 3(b), the on-resistance between the source and drain in the positive field is approximately 4MΩ (V, , = 4V, I
. , = I O-'A) te, whereas in the negative field it becomes about 400 Ω. This difference is not a problem in the case of relatively small (low rain prime) liquid crystal panels, but in the case of large (high definition) liquid crystal panels with short gate selection periods, the pixel electrode 3
The voltage applied to the pixel electrode 304 during the 0th order selection period, in which the ratio of the voltage applied to the source region 302 to the voltage applied to the source region 302 (signal voltage) is significantly lower in the positive field than in the negative field. We will discuss the characteristics that maintain this. From Figure 2, in the negative field, V when the gate is off, = O ~ 4V, and in the positive field, Vas”
6 to IOV, the off-resistance of the J film transistor is 4TΩ in the negative field, but reaches a maximum of 40GΩ in the positive field. In other words, with the potential of the counter electrode 305 as a reference potential, during a positive field, compared to a negative field, the No. 8 voltage is applied to each pixel electrode 304, and the applied voltage is more likely to leak.As a result, The pixel electrode potential loses symmetry with respect to the counter electrode potential, and a DC component is applied to the liquid crystal layer 306. If this condition is significant, the liquid crystal panel may suffer from afterimages, display unevenness, and other display defects. It has been reported that this problem occurs, and solving this problem is one of the major challenges for liquid crystal panels.
そこで本発明の目的は、第３図（ｂ）のごとくの特性を
有するａｌｌｉトランジスタを用いながら、上記問題点
（残ｆ象、表示ムラ、その他表示不良）を解決する液晶
パネルの駆動回路を提案することにある。Therefore, the purpose of the present invention is to propose a driving circuit for a liquid crystal panel that solves the above-mentioned problems (residual image, display unevenness, and other display defects) while using an ALLI transistor having the characteristics shown in FIG. 3(b). It's about doing.
［課題を解決するための手段１
本発明の液晶パネルの駆動回路は、薄膜トランジスタを
マトリックス状に配置した薄膜基板と、該薄膜基板の各
画素毎に分割形成された駆動用電極により制御される液
晶層と、ガラス基板上に透明電極層を形成した対向基板
とを、夫々積層配置した液晶パネルにおいて、液晶駆動
交流化周期に同量して、前記薄膜トランジスタのゲート
電□□□に印加する、選択電圧及び非選択電圧のいづれ
か一方、もしくは両方を変化させることを特徴とする。[Means for Solving the Problems 1] The liquid crystal panel drive circuit of the present invention includes a thin film substrate on which thin film transistors are arranged in a matrix, and a liquid crystal panel controlled by a driving electrode formed separately for each pixel of the thin film substrate. In a liquid crystal panel in which a layer and a counter substrate in which a transparent electrode layer is formed on a glass substrate are stacked, the gate voltage of the thin film transistor is applied in the same amount as the alternating current period for driving the liquid crystal. It is characterized by changing either one or both of the voltage and the non-selection voltage.
［実 施 例］
以下、実施例に基づき本発明の液晶パネルの駆動回路の
詳細な説明をする。[Example] Hereinafter, a driving circuit for a liquid crystal panel according to the present invention will be described in detail based on an example.
第１図（ａ）は本発明の液晶パネルの駆動回路のブロッ
ク図の一例である。第１図（ａ）において１１１は薄膜
トランジスタ１１８のゲート駆動ＩＣ（以後’ｌ’ −
Ｄｒｉｖｅｒ Ｉ Ｃと呼ぶ）である。ＹＤｒｉｖｅｒ
ｌ Ｃは基本的に、各ゲート線１１６の選択間開、及び
タイミングを決定するシフトレジスタ＋１２、薄膜ト・
ランジスタのゲート３０１のオンＡフを制御するアナロ
グスイッチ１１４．シフトレジスタ１１２の出力をアナ
ログスイッチｌ Ｉ 、４の駆動レベルまでも５あげる
レベルシフタ１１３（、゛よって構成される。薄膜トラ
ンジスタ１１８のゲー１−３０１は走査方向に対し、垂
直なゲート線ｌ１６に接続されゲート線１１６はＹ −
Ｄｒｉｖｅｒ Ｉ Ｃの出力端子に接続される。−・方
ソース領域３０２は走査方向に並行なソース線１１７に
図のごとく接続され、ソース線１１７はソース線駆動Ｉ
Ｃの出力端子に接続される６ソース線駆動ＩＣは本発明
には直接間係がないため、図では削除しである６又、対
向′：４極１２０には図のごとく、一定の電圧が与太ら
れている。FIG. 1(a) is an example of a block diagram of a driving circuit for a liquid crystal panel according to the present invention. In FIG. 1(a), 111 is a gate drive IC (hereinafter 'l' -
Driver IC). YDriver
lC basically consists of a shift register +12, a thin film transistor, and a thin film transistor that determine the selection and timing of each gate line 116.
An analog switch 114 that controls the on/off state of the gate 301 of the transistor. The output of the shift register 112 is increased by 5 to the drive level of the analog switch lI,4.The gate 1-301 of the thin film transistor 118 is connected to the gate line l16 perpendicular to the scanning direction. The gate line 116 is Y −
Connected to the output terminal of Driver IC. - The direction source region 302 is connected to the source line 117 parallel to the scanning direction as shown in the figure, and the source line 117 is connected to the source line driving I
The six source line drive ICs connected to the output terminals of C are not directly related to the present invention, so they are omitted from the diagram. It's given a lot of weight.
本発明の特徴は、従来固定電圧であったＹ−Ｄｒｉｖｅ
ｒＩ Ｃの駆動系の正電圧１２１、及び負電圧１２２（
ゲート３０１の退択電圧、非選択電圧に対応する６）を
、電圧制御回路＋１５により、液晶交流化周期信号（Ｆ
Ｒ）１２３に同期し、変化さゼることにある。すなわち
、■−フィールド時には、ゲート正フィールドオンレベ
ル及び、ゲート正フイールドオフレベルを、又［ｌフィ
ール１：時には、ゲーｔ−ｆ’＋フィールドオンレベル
及びゲ−ｔ−ｔ７ｔフィールドオフレベルをＹ −Ｄｒ
ｉｖｐｒ ％動糸及び液晶パネルゲート線１１６に印加
４る。The feature of the present invention is that the Y-Drive, which used to have a fixed voltage,
Positive voltage 121 and negative voltage 122 (
6) corresponding to the selection voltage and non-selection voltage of the gate 301 is controlled by the voltage control circuit +15 to a liquid crystal alternating current periodic signal (F
R) 123 and change. That is, in the case of - field, the gate positive field on level and the gate positive field off level are set to [l field 1: sometimes, the gate t-f'+field on level and the gate t7t field off level are set to Y- Dr.
ivpr% is applied to the moving thread and the liquid crystal panel gate line 116.
第１図（ｂ）は本発明の液晶パネルの駆動回路による、
ゲート印加電圧１０７、ソース印加電［「１０５の経時
変化を示すタイミング図である。図において、１０１は
正フイールドゲートオンレベル、１０２は負フィールト
ゲ−［・オンレベル＋０３は正フイールドゲートオフし
・ベル、１０４は負フィールトゲ−１−オフし・ベル、
９，１０６はりｌ面電極電位を示す。FIG. 1(b) shows a drive circuit for a liquid crystal panel according to the present invention.
This is a timing diagram showing changes over time in the gate applied voltage 107 and the source applied voltage [105. In the figure, 101 is the positive field gate on level, 102 is the negative field gate on level +03 is the positive field gate off level. , 104 is a negative field game 1-off bell,
9,106 shows the electrode potential on the l-plane.
図より明らかなとおり、本発明のｉＡ品パｔ、ルの駆動
回路を用いれば、薄膜トランジスタ１１８のテカ作状態
を決定するゲート３０１とソース領域３０２の電位差Ｖ
１３．が正フイールド負フィールドで同一となり１両フ
ィールドでのソー２．電叩印加特性、及び保持特性を同
一にすることができる９Ｊニー）てｉｉ１述した理由に
より、液晶パネルの間開【ｊｌ、残像、表示ムラ、その
他表示不良を解消することができる、
次に本発明の伯の実施例（構成例）をあげる。As is clear from the figure, if the iA product pattern drive circuit of the present invention is used, the potential difference between the gate 301 and the source region 302, which determines the shine state of the thin film transistor 118, can be
13. are the same in the positive field and the negative field, so 2. is the same in the 1 field. Due to the reasons mentioned above, it is possible to make the electric tapping characteristics and retention characteristics the same, and it is possible to eliminate gaps in the liquid crystal panel, afterimages, display unevenness, and other display defects. An example (configuration example) of the present invention will be given below.
液晶パネルの構成」二特に画禦電−３０４の信号量圧印
υ口特性が問題となる場合、第１図（ａ）、（’ ｂ
）のゲー トオフレベルは正フィールド、負フィールド
ども同一とじ、ゲー）−オンレベルのみ正フィールドと
負フィールドで変化さゼる伯の実施例１８
逆に使の実施１！’１１２として、特に信号電圧の（Ｖ
持持りが問題となる場合、ゲートオンレベルは正フィー
ルド、負フィールドとも同一とし、ゲート４フイレベル
のみ、正フィールドと負フィールドで変化させる方式。In particular, when the signal amount stamping characteristic of the LCD panel 304 is a problem, the structure of the liquid crystal panel (Fig. 1(a), ('b)
)'s gate-off level is the same for the positive field and negative field, and only the gate-off level changes between the positive field and the negative field. '112, especially the signal voltage (V
If retention is a problem, the gate-on level is the same for both the positive and negative fields, and only the gate 4 fill level is changed between the positive and negative fields.
叉、回路自体の構成例として、電圧制御回路１１５を、
’ｌ’ −ＤｒｉｖｅｒＩ Ｃ１１１内に取込み、４電
源のうちから、ｌ電源を退択する構成をとる他の実施例
３゜
そし、で、Ｙ−Ｄｒｉｖｅｒｌ Ｃ１１１のロジンタ部
シフトレジスタ１１２への入力信号ｃ ｌ ＯＣｋ乃び
・、ｔ ａ ｒ ｔ Ｐ １１１ ｓ ｅを液晶交流
化周ｉｌｌ信号（ＦＲ）１２３に同期してレベルシフト
し、Ｙ−ＤｒｉｖｅｒＩ Ｃ全体をゲート正電圧１２１
及び負電圧１２２で駆動する構成とした他の実施例４が
考えられる。Further, as an example of the configuration of the circuit itself, the voltage control circuit 115 is
Another embodiment 3 in which the l power source is taken into the 'l'-Driver I C111 and the l power source is selected from among the four power sources.And, the input signal c to the rosinter shift register 112 of the Y-Driver I C111 is The levels of l OCk and tar P 111 s are shifted in synchronization with the liquid crystal alternating current illumination signal (FR) 123, and the entire Y-Driver I C is set to the gate positive voltage 121.
Another example 4 can be considered, which is configured to drive with a negative voltage 122.
［発明の効果１
以上述べた様に１本発明は、薄ＩＩＱ ＋・ランジスタ
を用いた液晶パネルにおいて、１ｃし品駆動２流化周期
に同期して、前記薄膜トランジスタのゲート電極に印加
する、退択電圧（ゲートオンレベル）及び非選択電圧（
ゲートレベル）のいづれが一方もしくは両方を変化させ
ることにより、液晶層１１９に印加される直流成分を除
去し、結果、残像、表示ムラ、その他表示不良という、
液晶パネルの重大な問題点を解消できる。この効果は、
特（、二人り、高精細の液晶パネルに１５いて絶大であ
る。[Effects of the Invention 1] As described above, the present invention provides a liquid crystal panel using a thin IIQ + transistor, in which a voltage is applied to the gate electrode of the thin film transistor in synchronization with the 1C drive dual current cycle. Selective voltage (gate-on level) and non-selective voltage (
By changing one or both of the gate level), the DC component applied to the liquid crystal layer 119 is removed, resulting in afterimages, display unevenness, and other display defects.
This solves serious problems with LCD panels. This effect is
Especially, the two of us were on a 15-inch high-definition LCD panel, and it was amazing.
第１図（ａ）は本発明の液晶パネルの駆動回路のブロッ
ク図。
第１図（ｂ）は本発明の液晶パネルの駆動回路のタイミ
ング図。
第２図は従来の液晶パネルの駆動回路のタイミング図。
第３図（ａ）は液晶パネルの等価回路図。
第３図（ｂ）は薄膜トランジスタの１ｅａ−Ｖａｓ特性
図。
・ゲート駆動Ｉ Ｃ（Ｙ −１１ｒｉｖｅｒｌ Ｃ）・
シフトレジスフ
・レベルシフタ
・アナログスイッチ
電圧制御回路
・ゲート線
ソース線
・薄膜トランジスタ
・液晶層
対向電極FIG. 1(a) is a block diagram of a driving circuit for a liquid crystal panel according to the present invention. FIG. 1(b) is a timing diagram of a driving circuit for a liquid crystal panel according to the present invention. FIG. 2 is a timing diagram of a conventional liquid crystal panel drive circuit. FIG. 3(a) is an equivalent circuit diagram of a liquid crystal panel. FIG. 3(b) is a 1ea-Vas characteristic diagram of a thin film transistor.・Gate drive IC (Y-11riverl C)・
Shift resistor, level shifter, analog switch voltage control circuit, gate line source line, thin film transistor, liquid crystal layer counter electrode
Claims (1)
と、該薄膜基板の各画素毎に分割形成された駆動用電極
により制御される液晶層と、ガラス基板上に透明電極層
を形成した対向基板とを、夫々積層配置した液晶パネル
において、液晶駆動交流化周期に同期して、前記薄膜ト
ランジスタのゲート電極に印加する、選択電圧及び非選
択電圧のいづれか一方、もしくは両方を変化させること
を特徴とする液晶パネルの駆動回路。A thin film substrate having thin film transistors arranged in a matrix, a liquid crystal layer controlled by driving electrodes formed separately for each pixel of the thin film substrate, and a counter substrate having a transparent electrode layer formed on a glass substrate, respectively. Driving a liquid crystal panel in which one or both of a selection voltage and a non-selection voltage applied to the gate electrode of the thin film transistor is changed in synchronization with a liquid crystal drive alternating current cycle in a stacked liquid crystal panel. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29151288A JPH02136824A (en) | 1988-11-18 | 1988-11-18 | Liquid crystal panel driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29151288A JPH02136824A (en) | 1988-11-18 | 1988-11-18 | Liquid crystal panel driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02136824A true JPH02136824A (en) | 1990-05-25 |
Family
ID=17769849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29151288A Pending JPH02136824A (en) | 1988-11-18 | 1988-11-18 | Liquid crystal panel driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02136824A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04362689A (en) * | 1991-06-10 | 1992-12-15 | Sharp Corp | Driving circuit for display device |
| JP2006084617A (en) * | 2004-09-15 | 2006-03-30 | Seiko Epson Corp | Drive circuit for optoelectronic device, optoelectronic device, and electronic equipment |
| JP2009103972A (en) * | 2007-10-24 | 2009-05-14 | Seiko Epson Corp | Electrophoretic display apparatus, electronic equipment, and driving method for electrophoretic display apparatus |
| JP2009222777A (en) * | 2008-03-13 | 2009-10-01 | Toppoly Optoelectronics Corp | Display device, electronic device and system |
| JP2011043804A (en) * | 2009-07-22 | 2011-03-03 | Semiconductor Energy Lab Co Ltd | Display device, method of driving the same, and electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273235A (en) * | 1985-09-27 | 1987-04-03 | Hitachi Ltd | Driving method for display device |
-
1988
- 1988-11-18 JP JP29151288A patent/JPH02136824A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273235A (en) * | 1985-09-27 | 1987-04-03 | Hitachi Ltd | Driving method for display device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04362689A (en) * | 1991-06-10 | 1992-12-15 | Sharp Corp | Driving circuit for display device |
| JP2006084617A (en) * | 2004-09-15 | 2006-03-30 | Seiko Epson Corp | Drive circuit for optoelectronic device, optoelectronic device, and electronic equipment |
| JP2009103972A (en) * | 2007-10-24 | 2009-05-14 | Seiko Epson Corp | Electrophoretic display apparatus, electronic equipment, and driving method for electrophoretic display apparatus |
| JP2009222777A (en) * | 2008-03-13 | 2009-10-01 | Toppoly Optoelectronics Corp | Display device, electronic device and system |
| US8264444B2 (en) | 2008-03-13 | 2012-09-11 | Chimei Innolux Corporation | Low-flickering display device |
| JP2011043804A (en) * | 2009-07-22 | 2011-03-03 | Semiconductor Energy Lab Co Ltd | Display device, method of driving the same, and electronic device |
| US9070338B2 (en) | 2009-07-22 | 2015-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device, driving method of the same and electronic device |
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