JP2003295157A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems that, in a liquid crystal display device driven by a conventional capacitance coupling since signals inverted every one H (horizontal scanning period) are applied to all the source lines, in the state of the same polarity, a crosstalk has been apt to occur, and moreover, a flicker has been apt to occur due to the line inversion display. <P>SOLUTION: Pixels arranged in a matrix form corresponding to the cross- points of source lines and gate lines are constituted of TFTs (thin film transister), pixel electrodes, and storage capacitance, and the storage capacitance is connected to a different capacitance line at each adjacent pixel along a gate line. In such a manner, adjacent source lines are always supplied with signals of opposite polarities and further dot reverse display becomes possible, therefore, horizontal crosstalk and flickers are eliminated. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a liquid crystal display device using a driving method called capacitive coupling driving.

[0002]

2. Description of the Related Art A liquid crystal display device (hereinafter, abbreviated as AM-LCD) using an active matrix type, typically a three-terminal thin film transistor (TFT) as a switching element, has the essential characteristics of thinness and low power consumption. In addition, since it has high display performance in various sizes, resolutions, and finenesses, it is widely used as a leading role in display terminals such as mobile devices, display monitors, and televisions.

As a liquid crystal display mode of AM-LCD,
Conventionally, the TN (Twisted Nematic) mode has been mainly used, but in response to demands for performance improvement such as viewing angle and response speed, IPS (In Plane)
Switching) mode, OCB (Optica)
lily Self Compensated Bire
fringence) mode, VA (Vertical)
Alignment mode etc. have been proposed or put into practical use.

As shown in FIG. 27, the basic constitution of the AM-LCD to which the present application is directed is, as shown in FIG. 5, and further a phase difference compensating plate 6, a backlight system including a lamp 8 and a light guide plate 9, and a circuit block 7 including a drive circuit for driving liquid crystal, a control circuit, a backlight lighting circuit, and the like, if necessary. . And one substrate 1
As shown in FIG. 25A, a plurality of gate lines G1, G2, ... And a plurality of source lines S1, S are provided on the surface of the (active matrix array (AM) substrate) in contact with the liquid crystal layer.
.. are formed so as to be orthogonal to each other, and TFTs and pixels are arranged corresponding to the intersections. Usually, a counter electrode that is uniform over the entire surface is provided on the surface of the other substrate 2 (counter substrate) in contact with the liquid crystal layer. Each pixel is displayed as a pixel capacitance Clc in which a liquid crystal layer is sandwiched between a pixel electrode and a counter electrode. A voltage Vc is applied to the counter electrode commonly to all pixels.
Further, the counter substrate or the AM substrate is provided with a color filter layer and, if necessary, a black matrix for shielding light from a portion which adversely affects the operation. Display is performed by modulating the optical characteristics of the liquid crystal layer sandwiched between the pixel electrode and the counter electrode by the voltage applied between the electrodes. The counter electrode may be formed on the AM substrate depending on the liquid crystal display mode (for example, IPS mode).

The driving of the AM-LCD will be briefly described as follows.
During one frame period T (usually 1/60 to 1/80 seconds), all the gate lines are sequentially selected one by one, and the TFTs connected to the selected gate lines become conductive, and at that timing. The video signal supplied from the source line is TFT
The pixel electrode is charged via the. When the total number of gate lines is N, the period during which the TFT can be used for one charge is H = T /
It is N seconds (1 horizontal scanning period). The voltage charged in the pixel electrode controlled by a certain gate line is held until the gate line is selected again in the next frame (N is usually 200 or more, so for almost one frame), and the liquid crystal is Applied to the layer. Since the liquid crystal layer needs to be driven by alternating current, in the next frame, the polarity of the video signal is inverted to charge the pixel electrode. The optical properties of the liquid crystal layer are modulated in response to the effective value of the voltage thus applied. In order to accurately hold the voltage charged in the pixel electrode for one frame, normally, as shown in FIG.
st is arranged in parallel with the pixel capacitance Clc. As the other electrode for forming the storage capacitor, there is a case where a gate line in the previous stage is used and a case where an independent capacitance line is provided, but FIG.
Shows the case where independent capacitance lines CC1, CC2, ... Are provided.

Although the ideal case has been described above, in reality, the on / off characteristics of the TFT switch are different from the ideal, and the parasitic capacitance between the gate and drain of the TFT, between the source line and the counter electrode, etc. Is present, the dielectric constant of the liquid crystal layer shows a non-linear dependence on the applied voltage, or secondary factors such as the resistance of the counter electrode, source line, gate line, etc. are not sufficiently small. Display problems such as flicker and crosstalk occur.

On the other hand, there are various demands as products such as reduction of power consumption, improvement of brightness, and low cost. In consideration of these, it is necessary to optimize the liquid crystal layer (mode), the structure of the AM substrate, the driving method, etc. according to the purpose.

In order to reduce flicker, when driving a liquid crystal display device, it is usually driven so as to perform line inversion display (row inversion display), column inversion display (column inversion display), or dot inversion display, and positive and negative polarities are obtained. Pixels are spatially mixed. The line inversion display inverts the voltage polarity of the pixel electrode for each adjacent gate line, and is effective in preventing flicker due to the above secondary factor.
The dot inversion display further inverts the voltage polarity of the pixel electrode for each adjacent source line and is more effective in preventing flicker.

Further, when the connection resistance of the counter electrode is large, a display problem called lateral crosstalk caused by capacitive coupling between the source line and the counter electrode occurs, but in contrast to this, an image supplied to the source line is generated. Reversing the signal polarity for every adjacent source line is an effective solution from the driving surface.

A capacitive coupling drive method has been proposed as a drive method for reducing drive power. This method is disclosed in, for example, Japanese Patent Laid-Open No. 2-913.
A modulation voltage pulse is applied to the storage capacitor electrode to modulate the voltage of the pixel electrode via the storage capacitor (in other words, a superimposed component or bias component is added to the pixel electrode voltage).
Based on this idea, it has a feature that the amplitude of the video signal applied to the source line can be reduced to half or less. When the storage capacitor electrode is the previous stage gate line, the amplitude of the scanning voltage applied to the gate line is large, but the aperture ratio of the pixel can be kept high and the liquid crystal is overdriven by the gate selection pulse. Therefore, the response speed becomes faster. On the other hand, when an independent capacitance line is provided, it is not necessary to increase the amplitude of the scanning voltage, but the presence of the capacitance line lowers the aperture ratio of the pixel, so it is necessary to select it according to the purpose.

FIG. 26 shows drive voltage waveforms when capacitive coupling drive is applied to the AM substrate having the circuit configuration shown in FIG. 25 (a). In FIG. 26, the signal of the source line shows only the polarity of the signal in each 1H period. After the selection of the gate line G1 is finished, the voltage of the capacitance line CC1 is changed by Vcc in the positive direction, the pixel voltage of the pixel controlled by the gate line G1 is modulated, and the capacitance of the gate line G2 is finished. The voltage of the line CC2 is changed by Vcc in the negative direction and the pixel voltage of the pixel controlled by the gate line G2 is modulated. Further, FIG. 25B shows an example of the distribution of the voltage polarities of the pixels P (n, m) controlled by the gate lines Gn and the source lines Sm in that case.

[0012]

The details of the operation will be omitted here because they will be described in detail in the embodiments, but when the capacitive coupling drive is applied to the liquid crystal display device including the conventional AM substrate as described above, Horizontal scanning period t1, t
In 2, ..., All source lines must be supplied with signals of the same polarity as shown in FIG. That is, a positive polarity signal is supplied to all the source lines during the selection period of odd rows such as t1 and t3, and a negative polarity signal is supplied to all the source lines during the selection period of even rows such as t2 and t4. become. At the moment of this switching, the voltages of all the source lines move in the same direction, so that a large coupling voltage (switching noise of the source line) is superimposed on the counter electrode due to coupling with these. Further, this noise amount depends on the display pattern. For this reason, when the connection resistance of the counter electrode is large, the superimposed noise component remains without being eliminated, and there is a possibility that a lateral crosstalk problem may occur due to the coupling between the source line and the counter electrode.

Further, the polarity distribution of the pixels is line inversion display as shown in FIG. Therefore, problems may remain when flicker reduction is important.

[0014]

In order to solve the above-mentioned problem of lateral crosstalk in capacitive coupling drive, a liquid crystal display device of the present invention has a liquid crystal layer sandwiched between first and second substrates facing each other. On the surface of the first substrate facing the liquid crystal layer,
Corresponds to multiple gate lines, multiple source lines that intersect the gate lines and are supplied with video signals, capacitor lines that are paired with each gate line and that are parallel to the gate lines, and each intersection of the gate line and the source line And pixels arranged in a matrix are formed, and the pixels each include a switching element, a pixel electrode connected to the switching element, and a storage capacitor connected between the pixel electrode and the capacitor line, The capacitor is characterized in that, for each pixel adjacent to each other along the gate line, the capacitor is alternately connected to the adjacent capacitor lines with the pixel in between.

With this configuration, since signal voltages of opposite polarities are supplied to adjacent source lines and dot inversion display is possible, there is no horizontal crosstalk and there is little flicker, and a liquid crystal display with excellent display performance is provided. The device is realized.

In another liquid crystal display device of the present invention, a plurality of gate lines, a plurality of source lines, a capacitance line, and intersections of the gate lines and the source lines are formed on the surface of the first substrate which faces the liquid crystal layer. A pixel is formed corresponding to, the pixel includes a switching element controlled by a gate line, a pixel electrode connected to the switching element, and a storage capacitor connected between the pixel electrode and the capacitor line, The switching element is connected to each pixel adjacent to each other along the gate line so as to be alternately controlled by the adjacent gate lines sandwiching the pixel.

With this configuration, since signal voltages of opposite polarities are supplied to adjacent source lines, a liquid crystal display device having excellent display performance without horizontal crosstalk is realized.

In still another liquid crystal display device of the present invention, a plurality of gate lines, a plurality of source lines, a capacitance line, and a gate line and a source line are formed on a surface of the first substrate which faces the liquid crystal layer. A pixel is formed corresponding to the intersection, and the pixel includes a switching element controlled by a gate line, a pixel electrode connected to the switching element, and a storage capacitor having one terminal connected to the pixel electrode. The other terminal of the capacitance is connected to a gate line other than the gate line that controls the pixel to which the storage capacitance belongs, and for each pixel that is adjacent along the gate line, the storage capacitance belonging to that pixel is alternately assigned to a different gate line. It is characterized by being connected.

With this structure also, since signal voltages of opposite polarities are supplied to the adjacent source lines and dot inversion display is possible, there is no horizontal crosstalk and there is little flicker and the display performance is excellent. A liquid crystal display device is realized.

Further, in the driving of the liquid crystal display device having the above structure, a selection pulse is sequentially applied to the gate line during one frame to select a pixel, and the source line of the selected source pixel is switched through the switching element of the selected pixel. The video signal is written to the pixel electrode, and the voltage of the capacitance line changes in the positive or negative direction by a certain amount after the selection of the pixel to which the storage capacitance connected thereto is completed, and the voltage of the voltage of each adjacent capacitance line changes. The polarity of change is different. And, the change amount of the voltage of the capacitance line is
The change in the positive direction and the change in the negative direction can have the same size or different sizes.
When the amount of change in the voltage of the capacitance line is set to be the same for the change in the positive direction and the change in the negative direction, the output level of the drive circuit for driving the capacitance line may be binary, so that the circuit configuration is simplified. Further, if the amount of change in the voltage of the capacitance line is set to be different between the change in the positive direction and the change in the negative direction, three values are required as the output level of the drive circuit, but the DC component remaining in the liquid crystal is more completely removed. As a result, the operational reliability of the liquid crystal can be improved, and flicker or burning caused by the residual DC component can be reduced.

In the above liquid crystal display device, it is desirable that the input signal to the source side drive circuit is inverted in the positive and negative charging periods so that the gradation-signal voltage characteristics of the source side drive circuit are substantially symmetrical. . As a result, even if signals of positive and negative polarities are output from the source side drive circuit at the same timing, a positive and negative characteristic difference does not occur, and display without flicker or burn-in can be performed.

Further, in the above liquid crystal display device, one horizontal scanning period (1H period) is divided into a plurality of periods, pixels corresponding to positive and negative polarities are charged at different timings within the 1H period, and the signals of the divided periods are generated. It is desirable to switch the gradation-signal voltage characteristics according to the polarity. In this way, positive and negative polarities have the same characteristics, and good display corresponding to desired γ characteristics can be performed.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 5.

FIG. 1A shows the circuit configuration of the AM-LCD according to the first embodiment of the present invention, and FIG. 1B shows the polarity distribution of the pixel voltage. FIG. 2 shows waveforms for driving the AM substrate of FIG. Elements having the same functions as those of the conventional example shown in FIG. 25 (a) or FIG. 26 are designated by the same reference numerals or symbols.

The main difference from the conventional example shown in FIG. 25 and FIG. 26 is that in the circuit configuration, as shown in FIG. 1A, the storage capacitance Cst is different for each pixel adjacent to the pixel line along the gate line. 2 and regarding the drive waveform, the signal polarity of the source line is first inverted for each adjacent source line, and the timing of the pulse waveform of the capacitance line is added by 1H. Is delayed. As a result, as shown in FIG. 1 (b), the polarity of the pixel voltage is inverted for each adjacent pixel in the vertical and horizontal directions, and dot inversion display with a high degree of spatial mixing is realized, and strong flicker resistance is possible. There is. Further, as shown in FIG. 2, since signals of opposite polarities are always supplied to the adjacent source lines, horizontal crosstalk hardly occurs.

The AM substrate of the first embodiment has a plurality of gate lines Gn, a plurality of source lines Sm, TFTs provided corresponding to their intersections, pixel electrodes P (n, m), and storage capacitors Cst. , And a capacitance line CCn which is paired with each gate line and is provided in parallel with the gate line, and the storage capacitances of pixels adjacent to each other along the gate line are connected to different capacitance lines. n and m are arbitrary natural numbers. A pixel capacitor Clc is formed between the pixel electrode and the counter electrode (voltage Vc) with the liquid crystal layer interposed therebetween.

Video signals of opposite polarities are always supplied to the adjacent source lines, and the video signals of the respective source lines are inverted every 1H. The voltage of the capacitance line (for example, CC2) is set so as to change by the amplitude of the voltage Vcc at least 1H after the selection pulse of the corresponding gate line (for example, G2) is turned off (non-selected). To do. This is because the capacitance line CC2 is both connected to the storage capacitance of the pixel controlled by the gate line G2 and the storage capacitance of the pixel controlled by the gate line G3, and the gate lines G2 and G3 are both unselected. This is because it is necessary to change the voltage of the capacitance line CC2 later. Further, the voltage of the capacitance line is set so as to have different polarities for each adjacent capacitance line. Further, the voltage waveforms of the source line and the capacitance line are set to be inverted for each frame in order to drive the liquid crystal layer with an alternating current.

Next, the operation of the capacitive coupling drive will be described in detail. In explaining the operation specifically, the TFT
Since the presence of the parasitic capacitance Cgd between the gate and drain cannot be ignored, the circuit including this is shown in FIG. 3, and the operation will be described based on this. Further, here, for simplification of explanation, it is assumed that there is no leak current in the liquid crystal layer, leak current between the source and drain when the TFT is not selected, and no waveform distortion due to resistance of the source line or the gate line. FIG. 4 shows a drive waveform including the pixel electrode voltage Vp. The selection pulse amplitude of the gate line is Vg, the video signal voltage supplied from the source line is Vs (+) in the positive polarity, Vs (-) in the negative polarity, the amplitude of the capacitance line is Vcc, and Clc + Cst + Cgd = C.
At t, attention is paid to the pixel P (2,1) controlled by the gate line G2 and the source line S1, and the change of the pixel electrode voltage Vp is followed. First, in the period t2 in which the selection pulse is supplied to the gate line G2 in the first frame, the pixel electrode voltage Vp
Is a negative voltage Vs (-) supplied from the source line S1.
The pixel electrode voltage Vp is reduced by ΔVt = Vg · Cgd / Ct (penetration voltage) due to the presence of Cgd at the moment when the pulse of the gate line G2 is turned off at the end of the period t2. At the fall of the pulse of the capacitance line CC2 within the period of t4, the storage capacitance Cs
ΔV1 = Vcc · Cst / C due to capacitive coupling via t
Decrease by t. That is, the pixel electrode voltage Vp of the pixel P (2,1) is finally Vp (−) = Vs (−) − ΔVt.
-.DELTA.V1 and this voltage is held for almost one frame. In the next second frame, the positive voltage Vs (+) is supplied from the source line to the pixel electrode at the timing t2a, then decreases by the punch-through voltage ΔVt, and the pulse of the capacitance line CC2 rises by Vcc at t4a. In response to this, the pixel voltage finally becomes Vp (+) =
It becomes Vs (+)-ΔVt + ΔV1. Therefore, the AC amplitude of the pixel electrode voltage is {Vp (+)-Vp (-)} / 2 =
{Vs (+)-Vs (-)} / 2 + Vcc · Cst / C
t, and the average value of the pixel electrode voltage is {Vp (+) + Vp
(-)} / 2 = {Vs (+) + Vs (-)} / 2-Vg
・ It becomes Cgd / Ct. By supplying the same voltage as the average value of the pixel electrode voltage as the voltage Vc of the counter electrode, the liquid crystal layer is AC-driven and the DC component does not remain.

In FIG. 4, not only the pixel P (2,1) described above, but also the pixels P (2,2) and P (3,3) adjacent to the pixel P (2,1).
The voltage waveform of 1) is also shown together. Thus, it can be seen that voltages of opposite polarities are applied to each of the pixels adjacent to each other along the gate line and to each of the pixels adjacent to each other along the source line. As a result, the dot inversion distribution as shown in FIG. 1B is realized.

The AC amplitude of the pixel voltage is Vc · Cst rather than the amplitude of the video signal {Vs (+)-Vs (-)} / 2.
Since / Ct can be increased, the amplitude {Vs (+)-Vs (-)} of the signal on the source line can be reduced. This will be described in more detail with reference to FIGS. 5 (a) and 5 (b). The relationship between the applied voltage to the liquid crystal layer and the transmittance (in the case of normally white display) is shown in the upper part of FIG. Thus, the liquid crystal layer has a certain voltage V
There is no response up to th and the transmittance changes in the range of Vth to Vmax. In the conventional driving in order to display the entire range from white to black, the source line requires a voltage change of 2 · Vmax as shown at the bottom of FIG. ΔVt ± Δ from the capacitance line to the pixel voltage
Since the modulation (bias) of V1 is given, in the case of positive polarity, the source line may be supplied with a voltage in the range from A to B with C as a reference, and in the case of negative polarity, Aa with Ca as a reference.
It suffices to supply a voltage in the range from 1 to Ba. Figure 5
(B) illustrates this situation from another point of view, and more clearly shows the voltage change range of the source line in capacitive coupling drive. When the voltage of the source line in the capacitive coupling drive is combined with the bias of the capacitive coupling drive of ΔVt ± ΔV1, the voltage becomes the same as that in the conventional drive. In FIG. 5 (b),
The voltage change range of the source line in the capacitive coupling is (Vmax
It is shown that it is somewhat larger than −Vth), but by adjusting the size of ΔV1 (see FIG.
In terms of (b), it is possible to match the positive and negative voltage change ranges and reduce the voltage to the minimum value (Vmax-Vth) by increasing ΔV1 a little.
For that purpose, the source line voltage for displaying black (the voltage of the liquid crystal layer is Vmax) with a positive polarity and the source line voltage for displaying white (the voltage of the liquid crystal layer is -Vth) with a negative polarity. ΔV1 may be set so that the two values have the same value.
That is, ΔV1 for minimizing the voltage change range of the source line is Vmax− (ΔV1 + ΔVt) = − Vth + (ΔV1−
ΔVt), and ΔV1 = (Vmax + Vth) / 2 = Vth + (Vma
x-Vth) / 2. In this way, the amplitude of the voltage supplied to the source line can be reduced to 1/2 or less of the conventional level by the capacitive coupling drive, which is effective in reducing the power consumption of the source line drive circuit. Since the source line driving circuit has the highest operating frequency among the liquid crystal driving circuits, this power reduction effect is important.

Since a technique similar to that of the first embodiment is disclosed in Japanese Patent Laid-Open No. 10-123482, the difference will be described. FIG. 6 (a) shows Japanese Patent Laid-Open No.
The circuit configuration of the liquid crystal display device disclosed in Japanese Unexamined Patent Publication No. 0-123482, FIG. 6B shows the polarity distribution of the pixel voltage, and FIG. 7 shows the potential change of each part. In this liquid crystal display device, the gate line to be the connection destination of the TFT is different for each column, and accordingly the connection destination of the storage capacitor is also connected to the gate line at the front stage and the gate line at the rear stage. Since it is necessary to superimpose the modulation voltage (superimposed voltage) on the pixel in which the storage capacitor is connected to the subsequent gate line by capacitive coupling, the drive waveform of the gate line has a potential change for modulation even before the selection period. It is an added form. In FIG. 7, pixels P (2,1) and P (1,2) that are adjacent to each other in FIG.
The potential change of is drawn. Although the two pixels are adjacent to each other on the surface, the connection destinations of the TFTs are different, so that the pixels are charged at different timings. In addition, in the drive waveform, all source lines have positive t1 and t2.
Is negative, t3 is positive, and the like changes in-phase polarity.

Therefore, although the liquid crystal display device disclosed in this publication has high flicker resistance due to the dot inversion display, it has almost the same performance as the conventional one with respect to the horizontal crosstalk. In addition, since the left and right adjacent pixels are charged at different timings, it is necessary to rearrange the display data in advance.

The liquid crystal display device according to the first embodiment has the advantage that lateral crosstalk is unlikely to occur because a signal of opposite polarity is always supplied to the adjacent source line, in contrast to the above-mentioned one, and Since adjacent pixels are charged at the same timing, there is an advantage that display data need not be rearranged.

(Second Embodiment) FIG. 8A is a circuit configuration of an AM-LCD according to a second embodiment of the present invention, FIG.
(B) shows the polarity distribution of the pixel voltage in the pixel array.
FIG. 9 shows the drive waveform. FIG. 25 showing a conventional example.
Elements having the same functions as in (a) or FIG. 26 are designated by the same reference numerals or symbols.

The difference from FIG. 1A for explaining the first embodiment is that in pixels adjacent along the gate line,
That is, the TFTs are connected to different gate lines instead of the storage capacitors. The voltage waveforms of the source line, the gate line, and the capacitance line are the same as those in the first embodiment except that the timing of the voltage waveform of the capacitance line is advanced by 1H.

Since the operation is similar to that of the first embodiment, detailed description of the operation will be omitted, but in this case, the polarity distribution of the pixel voltage is line inversion display as shown in FIG. 8B. However, unlike FIG. 26 of the conventional example, the polarities of the signal voltages supplied to the source lines are always inverted for each adjacent source line.
Therefore, it has a feature that lateral crosstalk is unlikely to occur.

Here, the horizontal crosstalk which is a problem in the present application will be briefly described. If the voltage polarities of the adjacent source lines are the same, the voltage polarities of all the source lines repeatedly change positively and negatively every 1H. Figure 10
The electric potential of each part including the counter electrode Com at this time is shown. If the resistance between the counter electrode and the power supply that supplies the voltage Vc to the counter electrode or the internal resistance of the power supply is large, the voltage change of the source line causes the voltage of the counter electrode to transit through the parasitic capacitance between the source line and the counter electrode. Shaken for 1 hour
In the meantime, the transient phenomenon may not be fully subsided. Then, when a certain gate line is selected and the writing of the video signal to the pixel connected thereto is completed, a transient component (ΔVc in FIG. 10) remains in the counter electrode voltage, which remains as it is of the pixel electrode voltage. There will be an error. This error changes depending on the content of the video signal and is the sum of the influences from the source lines at a certain timing, and therefore differs from row to row. For example, in the case of a display content in which white is displayed only in the central part of the screen and halftone is displayed in other parts, display error in the horizontal direction of the line in which white is displayed, that is, crosstalk May occur.

When the voltages of the adjacent source lines have opposite polarities, the influence on the counter electrode is canceled by the adjacent source lines, so that this transient phenomenon does not easily occur. For example, when the display of the right and left adjacent pixels is completely equal, such as when a solid display window is arranged in the center of the screen, the positive and negative voltage couplings from the adjacent source lines to the counter electrode are balanced, and as shown in FIG. There is no fluctuation in the potential of the counter electrode. When the liquid crystal display mode is the IPS mode, the counter electrode is formed on the AM substrate side by the metal wiring having low resistance, and the area crossing the source line is small, so that the problem of such lateral crosstalk is small, but TN When the counter electrode is formed on the entire surface of the counter substrate side by the transparent electrode as in the mode or OCB mode, the resistance of the transparent electrode itself is higher than that of the metal electrode, and the entire source line faces the liquid crystal layer. The above problem becomes heavy because of the overlap with the electrodes.

Further, in the second embodiment, since the voltage polarities of the pixels adjacent to each other along the gate line are the same, the flicker may be disadvantageous, but the lateral electric field generated between the pixels is weak. Therefore, it also has the effect that the alignment disorder in the liquid crystal layer is small. For this reason, there are advantages that the contrast is high and the black matrix that shields light between adjacent pixels on the left and right can be designed to be narrow, so that the aperture ratio is improved and bright display can be performed.

In the second embodiment, since the positions of the pixels connected to the same gate line are arranged on the different sides of the adjacent pixels, it is possible to supply the video signal in consideration of this. is necessary. For example, the pixel P (2,1) in FIG. 8A is controlled by the gate line G2, and the pixel P (1,2) on the right side is selected by the gate line G1 1H earlier.
Therefore, it is necessary to supply the source line S2 with the data which should be supplied at the selection timing of the gate line G2 at the timing at which the gate line G1 is selected. Therefore, a data rearrangement circuit using a line memory or the like is required at the video signal supply circuit or in the preceding stage.

(Third Embodiment) The structure of an AM substrate in the third embodiment is shown in FIG. 1 (a) described in the first embodiment.
Alternatively, it is the same as that of FIG. 3, but the only difference is the drive waveform of the capacitance line. FIG. 12 shows drive waveforms in the third embodiment.

As shown in FIG. 12, in the third embodiment, in the drive waveforms of the capacitance lines CC1, CC2, CC3, etc., the magnitude Vcc1 of the potential change for giving a positive change to the pixel voltage and the negative magnitude Vcc1. The feature is that the magnitude Vcc2 of the potential change for giving the change in direction can be set independently. In the first embodiment, the voltage value of the capacitance line is 2
In contrast to the value, the third embodiment uses three values. By devising the drive waveform in this way, the residual DC component of the liquid crystal layer can be removed more accurately as will be described later, and therefore, the operation reliability of the liquid crystal is improved and flicker is reduced.

As in the first embodiment, the pixel P (2,1)
As can be seen from the change in the pixel electrode voltage Vp of Vp, the pixel electrode voltage in the negative polarity period is Vp (−) = Vs (−).
−ΔVt−ΔV2, the pixel voltage in the positive polarity period is Vp
(+) = Vs (+) − ΔVt + ΔV1. Here, ΔV1 = Vcc1 · Cst / Ct, ΔV2 = Vc
c2 · Cst / Ct. Therefore, the amplitude of the pixel electrode voltage is {Vs (+)-Vs (-)} / 2+ (Vcc2 + V
cc1) · Cst / Ct / 2, the average value of the pixel electrode voltage is {Vs (+) + Vs (−)} / 2−Cgd · Vg · Cg
d / Ct + (Vcc2-Vcc1) ・ Cst / Ct / 2
Becomes Here, −Cgd · Vg · Cgd / Ct + (V
cc2-Vcc1) .Cst / Ct / 2 = 0, that is, Vcc2-Vcc1 = 2.Vg.Cgd / Cst, the counter electrode voltage Vc is equal to the average value of the video signal, that is, Vc = {Vs (+) + Vs
AC driving is realized by setting (-)} / 2.

What is important here is that in the third embodiment, the DC offset of the liquid crystal layer can be set to 0 without depending on Ct, that is, the counter electrode voltage Vc can be set. As described above, in the first embodiment, the counter electrode voltage is Vc = {Vs (+) + Vs
It is determined by (−)} / 2−Vg · Cgd / Ct, but Ct is included in the formula. As is well known,
Since the dielectric constant of the liquid crystal layer strongly depends on the applied voltage,
Clc, that is, Ct, differs depending on the voltage applied to the liquid crystal layer. Therefore, in the method of setting the counter electrode voltage as in the first embodiment, even if the counter electrode voltage Vc is adjusted so that the direct current component disappears at a certain pixel voltage, a different pixel voltage is applied. Occurs that the DC component remains. Alternatively, if the liquid crystal voltage varies depending on the screen location, the problem remains that the DC component cannot always be zero over the entire screen. As a result, there is a concern about the long-term reliability of the liquid crystal, and the possibility of partial flicker on the screen or the phenomenon of burning. On the other hand, this third
When the embodiment is applied, since the counter electrode voltage in which the DC component does not remain can be set regardless of the liquid crystal voltage, such a problem does not occur.

As the drive waveform supplied to the capacitance line, as shown in FIG. 13, the waveform of CC1 (A) which is the same as CC1 of FIG. 12 or CC1 (B), CC
The waveform shown in 1 (C) may be used. Both are set so that one cycle of voltage change is completed in two frames. CC
In 1 (A), the level adjustment is performed in a period immediately before the voltage changes in the negative direction at t3a (a period including t1a and t2a) in the period in which the pixel connected to the capacitance line CC1 and related to the storage capacitor is selected. The voltage change in the negative direction at t3a is set to the desired value Vcc2. C
In C1 (B), the voltage of the capacitance line CC1 is level-adjusted so that the voltage change in the positive direction at t3 becomes Vcc1 during the period including t1 and t2. CC1 (C) is not very practical because the voltage has four values, but t1 and t
This shows that the level adjustment may be performed in both the period including 2 and the period including t1a and t2a. In short, the level adjustment is performed during the period including the selection period of the pixel to which the storage capacitor formed by the capacitance line is connected so that the positive amplitude change is Vcc1 and the negative amplitude change is Vcc2. You can do it.

Since signals of opposite polarities are always supplied to adjacent source lines, horizontal crosstalk is unlikely to occur, dot reverse display improves flicker resistance, and display data rearrangement is unnecessary. The advantage is that it is the same as that of the first embodiment.

(Fourth Embodiment) FIG. 14A shows a circuit configuration of an AM substrate in the fourth embodiment, and FIG. 15 shows drive waveforms of respective portions for driving the same.

In the first to third embodiments, the capacitance line is provided corresponding to the gate line to form the storage capacitance, but in the fourth embodiment, the capacitance line is not provided and the storage capacitance is , Connected to a gate line other than the gate line that controls the pixel to which it belongs. In this case, similar capacitive coupling drive is performed by superimposing a change corresponding to the voltage change of the capacitance line used in the previous embodiment on the gate line in addition to the gate selection pulse. The storage capacitor is connected to a different gate line for each pixel that is adjacent along the gate line. Specifically, FIG.
As shown in (a), in the pixel groups P (1,1), P (2,1), P (3,1), ... Connected to the source line S1, the storage capacitor is connected to the gate line in the previous stage. Then, pixel groups P (1,2), P (2,2), P (3,3) connected to the source line S2.
In 2), ..., Connect the storage capacitor to the gate line in the previous stage. Regarding the pixel group connected to the source line S3, the storage capacitor is connected to the gate line in the previous stage, like the pixel group connected to the source line S1.

By utilizing the gate line to form the storage capacitor in this way, the aperture ratio of the pixel is improved. In addition, with the above configuration, the polarity distribution of the pixel voltage in the pixel array is extremely strong against flicker, as shown in FIG. 14B, and dot inversion display is performed. Further, as shown in FIG. Since the signals of opposite polarities are always supplied, the excellent effect that lateral crosstalk hardly occurs is exhibited. Further, according to this configuration,
The rearrangement of the video signal supplied to the source line, which is necessary in the second embodiment, is also unnecessary.

The waveform of the gate line is, as shown in FIG.
For example, paying attention to the gate line G1, in the first frame, a selection pulse having an amplitude Vg is applied at a timing t1, and then level adjustment is performed at timings t2 and t3, and then, for capacitive coupling, an amplitude Vcc2 is negatively applied at a timing t4. Change voltage. This change in Vcc2 causes the pixel P to pass through the storage capacitor connected to the gate line G1.
Pixel voltages such as (2,1) and P (3,2) are modulated. In the second frame, the selection pulse of Vg is applied at the timing t1a, and then the level is adjusted at the timings t2a and t3a, and then the amplitude Vcc1 is changed in the positive direction at t4a for capacitive coupling. The selection pulse Vg is applied to the next gate line G2 at the timing t2, the level is adjusted at the timings t3 and t4, and then Vcc1 is changed in the positive direction at t5. In the second frame, the timing t5a is similarly set.
Changes Vcc2 in the negative direction. In the gate line G3, the waveform of the gate line G1 is applied with a delay of 2H. As described above, in this example, the polarities of the voltage changes for capacitive coupling are inverted for each adjacent gate line. In this example, the voltage change amount of the gate line used for capacitive coupling is different in the positive direction (Vcc1) and the negative direction (Vcc2).
It goes without saying that cc2 may have the same size.

By applying the gate line waveform of FIG. 15 to the array circuit of FIG. 14A, the pixel voltage becomes P of FIG.
(2,1), P (2,2), etc. are changed. Since the operation will be understood with reference to the detailed description in the previous embodiment, a detailed description will be omitted here. However, this pixel voltage waveform is affected by the gate selection pulse and The pixel voltage waveform is basically the same as that of the third embodiment except that there are two kinds of voltages (ΔVt1 and ΔVt2). Here, ΔVt1 = (Vg + Vcc1) · Cgd / Ct,
ΔVt2 = (Vg−Vcc2) · Cgd / Ct.
Therefore, although not described in detail, the formula for determining the counter electrode voltage Vc where no DC component remains will be somewhat changed from that described in the third embodiment.

Although the gate line G0 is shown in FIGS. 14A and 15, this is a kind of dummy gate which is not used for selecting the TFT but is used only for the pixel voltage modulation by capacitive coupling. It is a line. Although not shown in the drawing, another dummy gate line for this purpose is also required in the preceding stage G (-1) of G0. Total number of gate lines is N, 1H time is T / N
Then, the voltage waveforms of the dummy gate lines G0 and G (-1) may be the same as those of the gate lines of the final stage (N) and the preceding stage (N-1) when N is an odd number. N
Is an even number, the dummy gate lines G0 and G (-1)
As the voltage waveforms of the above, those obtained by shifting the gate line voltage waveforms of the final stage and the preceding stage by one frame (T) can be used.

As shown in FIG. 15, the pixel voltage behaves transiently during the 1-2H period after the period when it is selected or during the 1-2H period before it is selected. There is no practical problem because it is sufficiently shorter than one frame period and can be compensated by correcting the video signal voltage if necessary.

In the liquid crystal display device of the fourth embodiment, as in the case of the first embodiment, a signal of opposite polarity is always supplied to the adjacent source line as compared with the one disclosed in JP-A-10-123482. As a result, horizontal crosstalk is unlikely to occur, and pixels adjacent to the left and right are charged at the same timing, so that display data need not be rearranged.

(Embodiment 5) In each of the liquid crystal display devices of Embodiments 1 to 4 described above, while performing capacitive coupling drive, a signal of opposite polarity is supplied to an adjacent source line to laterally drive. Crosstalk is reduced and eliminated. In this case, it is necessary to supply positive and negative signals to the source line at the same scanning timing. The fifth embodiment shows a preferable driving method and circuit in this case.

Generally, in a display device, it is desirable that the .gamma. Characteristic between the brightness and the gradation has a relationship near the power of 2.2 as shown in FIG. Considering that the normally white liquid crystal display device has the voltage-transmittance curve shown in FIG. 5A, the source-side drive circuit is set with the gradation-signal voltage curve as shown in FIG. It is common to

In the capacitive coupling drive, the voltage change range of the source line is shared by the positive and negative pixels as shown in FIGS. 5A and 5B by superposing the modulation voltage. FIG. 18 is a gradation-signal voltage characteristic showing this state. A, Aa, B, and Ba in the figure are voltage change ranges of the source line video signal shown in FIG.

Even when capacitively coupled driving is performed, positive and negative gradation-signal voltage curves are not used simultaneously when combined with line inversion driving. In this case, as shown in FIG. 19, the gradation input of the negative pixel is set as an inverting input, and the two characteristic curves shown in FIG. 19 are switched and used for each 1H period in the positive horizontal scanning period and the negative horizontal scanning period. . Specifically, the voltage at the inflection point is set to V1 and V2 during the positive signal period, and set to V1a and V2a during the negative signal period. As an example, FIG.
The variable resistors R1, R2, and R3 of the power supply circuit 101 are switched every 1H to switch the values of V1 and V2 in the positive and negative periods, and the inflection point of the source side driving IC 102 is controlled by this voltage. In FIG. 20, reference numeral 104 denotes a liquid crystal panel, 103
Is a connection between the drive IC and the drive IC, and Sin is an input signal to the drive IC.

In the liquid crystal display device of the present invention, it is necessary to supply positive and negative signals to the source lines at the same scanning timing, and therefore the above method cannot be adopted. Therefore, in the liquid crystal display device of the fifth embodiment, as shown in FIG. 21, for example, the source-side signal circuit is configured so as to have substantially symmetrical gradation-signal voltage characteristics (γ characteristics). In FIG. 21, the characteristic which is substantially point-symmetrical about the point P is shown.
More specifically, in the power supply circuit 101 of FIG.
This characteristic is obtained by making the resistance values of R3 and R3 equal. Since it is not necessary to switch the characteristic between positive and negative, the resistance of the power supply section may be a fixed resistance. In this way, the characteristics do not change during positive and negative charging, and good display without flicker or image sticking can be obtained. Further, since no DC voltage is generated, seizure does not occur.

More preferably, as shown in FIG. 21, it is preferable to make the slopes of the characteristic curves gentle on both sides. In FIG. 21, in the positive pixel, the Q part corresponds to the gradation near black, and in the negative pixel, the Qa part corresponds to the gradation near black. Comparing this with the characteristics shown in FIG. 19, it can be seen that even if the characteristics shown in FIG. The gradation characteristics in the vicinity of black are important for producing a feeling of shading in a television or the like, and by doing so, it is possible to perform good image display rich in feeling of shading.

Further, the characteristics on the white side are improved by the following. In FIG. 21, consider the case where a positive pixel is charged. As shown in FIG. 21, the gradation levels at the end of the characteristic curve and the inflection point are L0, L1, and L in order from the darkest display.
2, L3. Between L2 and L3, the gradation-signal voltage characteristics are gentler than the original characteristics. FIG. 22 is a block diagram showing the flow of image signals in the liquid crystal display device. 1
A video signal processing circuit 07 processes a video signal input to the display device. Reference numeral 108 denotes a controller, which controls the gate-side drive IC and the source-side drive IC and gives an image signal (grayscale data) to the source-side drive IC. Reference numeral 104 is a liquid crystal panel, and 103 and 106 are connecting portions between the liquid crystal panel and the driving IC. At this time, using at least one of the video signal processing circuit or the controller,
The video signal input to the display device and the image signal Sin transmitted to the source side driving IC are set to have a relationship as shown in FIG. That is, the two are in a proportional relationship until Sin becomes L2, and a gradient is provided so that the change of Sin with respect to the change of the video signal becomes large at the portion where Sin is larger than L2. By doing so, the original display characteristics can be obtained even between L2 and L3.

When the characteristics of the Q portion and Qa portion in FIG. 21 are insufficient, the gradation characteristic between L0 and L1 may be similarly corrected to improve the characteristic on the black side.

(Sixth Embodiment) In the sixth embodiment, 1
The horizontal scanning period (1H period) is divided into a plurality of periods, pixels corresponding to positive and negative polarities are charged at different timings within the 1H period, and the gradation-signal voltage characteristics are switched according to the signal polarity of the divided period. Is.

As a concrete configuration example, as shown in FIG. 24, the output signal from the source side driving IC is switched to the switch section 11
There is a configuration in which 1 is used to distribute to two source lines. That is, in each divided period, voltages of the same polarity are output to a plurality of output terminals of the source side drive circuit, and in response to this, the connection relationship between the output of the source side drive IC and the source line is switched. Switching is performed by the unit 111. At this time, the gradation-signal voltage characteristic is also switched according to the signal polarity in the divided period. Pixels whose signals are charged in a certain divided period have the same polarity, and at least the source line for supplying a voltage to these pixels and the output of the source side driver IC are connected. In addition, 112 represents a pixel electrode and 113 represents a switching element (TFT).

Consider a case where the gate line G2 on the second row in FIG. 24 is in the selected state. This selection period (1H period)
In the first half, the source line for supplying the signal voltage to the TFT of the pixel which is positively charged and the output of the source side driving IC are connected using the switch section 111 in the first half. For example, drive IC
The outputs D1 and D2 are connected to the source line S1. Figure 2
4 shows the connection state in the first half. During this period, since only a positive signal is output from the drive IC, the gradation-
For the signal voltage characteristics, a portion (solid line portion) corresponding to the positive pixel of the one shown in FIG. 19 is used. In the latter half, the connection destination of the switch unit is changed to connect the source line that supplies the signal voltage to the TFT of the negatively charged pixel and the output of the source side drive IC. D1 and D2 are in turn connected to the source line S2. For the gradation-signal voltage characteristics, the portion (broken line portion) corresponding to the negative pixel in FIG. 19 is used. The gradation-signal voltage characteristics are switched by switching the variable resistance in the power supply circuit 101 in FIG.

In this way, the switching time of the positive and negative gradation characteristics is halved, but the characteristics are the same for positive and negative polarities, and good display corresponding to the desired γ characteristic can be performed.
Although not particularly limited, if the above switch part is made in the liquid crystal panel part by polysilicon or the like,
This is preferable because the effect of the sixth embodiment can be obtained without greatly expanding the frame.

It is not necessary to divide the gate line selection period into two equal parts in the first half and the second half. Furthermore, it is not always necessary for the switch section to select only the source line that supplies the voltage to the pixel to be charged in the divided period. In the above example, the source line to be selected later can be left connected. Both S1 and S2 are connected to D1 and D2 in the first half when a positive polarity signal is input, and S1 is disconnected and only S2 is connected in the second half when a negative polarity signal is input. It is also possible to configure the switch part as if it were called. Since the signal of the opposite polarity charged in the first half of the pixel belonging to S2 is immediately overwritten with the signal of the original polarity in the latter half, practical problems hardly occur. To realize the configuration of FIG. 24, D1, S2 and S
Since switches are formed at two positions between 1 and between D1, 2 and S2 and these are turned on and off, the configuration in which one of them is left connected is advantageous in that the number of switches is small. There is. To extend this idea to three or more source lines, the source lines to which the charged pixels belong may be separated in order.

The number of source lines for one output of the source side driving IC is not limited to two, and may be three or more. If the number is even, the positive and negative gradation characteristics are switched as well as the switching of the switch section as described above, but if the number is odd, the following measures are required. When the number of source lines for one output of the driver IC on the source side is three, the 1H period is divided into three, a certain switching block changes the charging polarity in the order of positive / negative / positive, and a switching block adjacent to it has a negative charging polarity.・ Charge polarity changes in the order of positive and negative. Therefore, the positive and negative source wirings are charged at the same timing. In such a case, a dummy period is provided to divide the 1H period into four, and a certain switching block is in the order of positive / negative / positive / dummy.
In the switching block adjacent to it, the charging polarity may be switched in the order of dummy, negative, positive, negative. During the dummy period, the output of the source side driving IC is not connected to anything.

In the sixth embodiment, the switch section is formed on the liquid crystal panel, but this may be formed by using a separate member on the outside of the liquid crystal panel.
In some cases, the switch unit may be incorporated in the drive IC.

The method described in the fifth embodiment can be applied even when there is a switch section, and exhibits the same effect.
In the case where it is difficult to control the liquid crystal display device due to the use of the dummy period, or when the 1H period is divided due to the frequency characteristic of the power switch unit and the grayscale-signal voltage characteristic cannot be sufficiently switched, the embodiment is described. The method shown in 5 may be used.

In the fifth and sixth embodiments, the signal voltage is supplied to each pixel by using the source side driving IC provided outside the liquid crystal panel, but this is as described above. The source-side drive circuit is not limited to this, and may be another source-side drive circuit. For example, it may be a drive circuit made of polysilicon or the like on a substrate forming a liquid crystal panel, or may be a voltage supply means different from the IC.

The terms "polarity" and "signal polarity" in the text do not indicate whether the signal voltage itself is positive or negative, but whether the voltage applied to the liquid crystal layer shown in FIG. 5A is positive or negative. Corresponding. As can be understood from FIG. 5 (b),
The source line voltage can be negative even when the signal polarity is positive, and vice versa.

[0073]

As described above, according to the present invention, by devising the circuit configuration of the active matrix array, it is possible to always supply signals of opposite polarities to adjacent source lines in capacitive coupling drive. As a result, dot inversion display is possible. As a result, it is possible to realize a liquid crystal display device with low power consumption of the source line drive circuit and high display quality without lateral crosstalk or flicker.

[Brief description of drawings]

FIG. 1A is a circuit configuration diagram of an array substrate of an active matrix liquid crystal display device according to a first embodiment of the present invention, and FIG. 1B is a polarity distribution diagram of pixel voltages of the liquid crystal display device.

FIG. 2 is a drive waveform diagram when capacitively coupling driving the active matrix liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a detailed circuit configuration diagram of an array substrate of the active matrix liquid crystal display device according to the first embodiment of the present invention.

FIG. 4 is a drive waveform diagram including a pixel voltage when the active matrix liquid crystal display device according to the first embodiment of the present invention is capacitively coupled and driven.

FIG. 5 is a diagram for explaining the characteristics of capacitive coupling drive.

FIG. 6A is a circuit configuration diagram of an array substrate of an active matrix liquid crystal display device in a comparative example, and FIG. 6B is a polarity distribution diagram of pixel voltages of the liquid crystal display device.

FIG. 7 is a drive waveform diagram when capacitively coupling driving an active matrix liquid crystal display device in a comparative example.

FIG. 8A is a circuit configuration diagram of an array substrate of an active matrix liquid crystal display device according to a second embodiment of the present invention, and FIG. 8B is a polarity distribution diagram of pixel voltages of the liquid crystal display device.

FIG. 9 is a drive waveform diagram when capacitively coupling driving the active matrix liquid crystal display device according to the second embodiment of the present invention.

FIG. 10 is a potential waveform diagram for explaining horizontal crosstalk.

FIG. 11 is a potential waveform diagram according to the second embodiment of the present invention.

FIG. 12 is a drive waveform diagram including a pixel voltage when the active matrix liquid crystal display device according to the third embodiment of the present invention is driven by capacitive coupling.

FIG. 13 is a diagram showing an example of a voltage waveform applied to a capacitance line in the third embodiment of the invention.

FIG. 14A is a circuit configuration diagram of an array substrate of an active matrix liquid crystal display device according to a fourth embodiment of the present invention, and FIG. 14B is a polarity distribution diagram of pixel voltages of the liquid crystal display device.

FIG. 15 is a drive waveform diagram when capacitively coupling driving the active matrix liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 16 is a gradation-luminance diagram of a display device in a conventional example.

FIG. 17 is a gradation-source voltage characteristic diagram in a conventional example.

FIG. 18 is a gradation-source voltage characteristic diagram in the conventional capacitive coupling drive.

FIG. 19 is a gradation-source voltage characteristic diagram in the conventional capacitive coupling drive.

FIG. 20 is a circuit configuration diagram of a conventional liquid crystal display device in capacitive coupling drive.

FIG. 21 is a gradation-source voltage characteristic diagram in the fifth embodiment of the invention.

FIG. 22 is a circuit configuration diagram of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 23 is a video signal according to the fifth embodiment of the present invention.
Characteristic diagram showing the relationship of the gradation data sent to the source side

FIG. 24 is a circuit configuration diagram of a liquid crystal display device according to a sixth embodiment of the present invention.

25A is a circuit configuration diagram of an array substrate of a conventional capacitive coupling driving liquid crystal display device, and FIG. 25B is a polarity distribution diagram of pixel voltages of a conventional liquid crystal display device.

FIG. 26 is a drive waveform diagram when a conventional liquid crystal display device is driven by capacitive coupling.

FIG. 27 is an overall configuration diagram of a liquid crystal display device to which the present application is applied.

[Explanation of symbols]

1 Active Matrix Array Substrate 2 Counter Substrate 3 Liquid Crystal Layers 4, 5 Polarizing Plate 6 Phase Difference Compensating Plate 7 Circuit Block 8 Lamp 9 Light Guide Plate 101 Power Supply Circuit 102 Source Side Driving IC 103, 106 Connection Section 104 Liquid Crystal Panel 107 Video Signal Processing Circuit 108 controller 111 switch part 112 pixel electrode 113 switching element (TFT) G1, G2, ... Gate line S1, S2, ... Source line CC1, CC2, ... Capacitance line P (n, m) nth gate line Pixels Vs (+), Vs (-) controlled by the m-th source line Vp (+), Vp (-) applied to the source line Pc electrode voltage Vc Counter electrode voltage Vg Gate line selection pulse voltage Vcc Amount of voltage change of capacitance line Clc Pixel capacitance Cst Storage capacitance Cgd Gate-drain parasitic capacitance of TFT

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 621 G09G 3/20 621B 624 624C 3/36 3/36 (72) Inventor Takahiro Kobayashi Osaka Prefecture 1006 Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Inventor, Tetsuya Kawamura, 1006 Kadoma, Kadoma-shi, Osaka F-term, Matsushita Electric Industrial Co., Ltd. (reference) 2H092 GA32 GA40 GA50 JA24 JA34 JA37 JA41 JB22 JB31 JB69 NA28 NA29 QA07 2H093 NA16 NA33 NA43 NA51 NC03 ND04 ND10 ND15 ND54 NF05 5C006 AC25 AC26 AF43 AF44 BB16 BF37 FA23 FA36 FA47 5C080 AA10 BB05 DD06 DD10 DD26 FF11 JJ02 JJ04 JJ06

Claims (16)

[Claims] 1. A plurality of gate lines on a surface of a first substrate facing a liquid crystal layer of a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween, and a video signal intersecting with the gate lines. Of the plurality of source lines, the capacitance lines that are paired with the gate lines and are arranged in parallel with the gate lines, and the pixels arranged in a matrix corresponding to the intersections of the gate lines and the source lines. The pixel includes a switching element, a pixel electrode connected to the switching element, and a storage capacitor connected between the pixel electrode and the capacitance line. A liquid crystal display device characterized in that adjacent pixels are alternately connected to adjacent capacitance lines with the pixels interposed therebetween. 2. A selection pulse is sequentially applied to the gate line during one frame to select the pixel, and a video signal of the source line is written to the pixel electrode via a switching element of the selected pixel. The voltage of the capacitance line changes by a certain amount in the positive or negative direction after the selection of the pixel to which the storage capacitance connected to the capacitance line belongs is completed, and the polarity of the change in the voltage is different between adjacent capacitance lines. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. 3. The liquid crystal display device according to claim 2, wherein the change amount of the voltage of the capacitance line is the same in the change in the positive direction and the change in the negative direction. 4. The liquid crystal display device according to claim 2, wherein the change amount of the voltage of the capacitance line has different magnitudes in the change in the positive direction and the change in the negative direction. 5. A plurality of gate lines on a surface of the first and second substrates facing each other with a liquid crystal layer sandwiched between them and a video signal crossing the gate lines on a surface of the first substrate facing the liquid crystal layer. Of the plurality of source lines, the capacitance lines that are paired with the gate lines and are arranged in parallel with the gate lines, and the pixels arranged in a matrix corresponding to the intersections of the gate lines and the source lines. The pixel is formed, and the pixel includes a switching element controlled by the gate line, a pixel electrode connected to the switching element, and a storage capacitor connected between the pixel electrode and the capacitance line, The liquid crystal display device is characterized in that the switching elements are connected to adjacent pixels along a gate line so as to be alternately controlled by the adjacent gate lines with the pixel interposed therebetween. 6. A selection pulse is sequentially applied to the gate line during one frame to select the pixel, and a video signal of the source line is written to the pixel electrode via a switching element of the selected pixel. The voltage of the capacitance line changes by a certain amount in the positive or negative direction after the selection of the pixel to which the storage capacitance connected to the capacitance line belongs is completed, and the polarity of the change in the voltage is different between adjacent capacitance lines. The liquid crystal display device according to claim 5, wherein: 7. The liquid crystal display device according to claim 6, wherein the change amount of the voltage of the capacitance line is the same in the change in the positive direction and the change in the negative direction. 8. The liquid crystal display device according to claim 6, wherein the amount of change in the voltage of the capacitance line is different in the change in the positive direction and the change in the negative direction. 9. A plurality of gate lines on a surface of the first and second substrates facing each other with a liquid crystal layer sandwiched between them and a video signal crossing the gate lines on a surface of the first substrate facing the liquid crystal layer. A plurality of source lines to which is supplied, and pixels arranged in a matrix corresponding to the respective intersections of the gate lines and the source lines are formed, and the pixels are switching elements controlled by the gate lines, A pixel electrode connected to the switching element, and a storage capacitor having one terminal connected to the pixel electrode, and the other terminal of the storage capacitor is a gate line other than the gate line for controlling the pixel to which the storage capacitor belongs. The liquid crystal display device is characterized in that, for each pixel adjacent to each other along the gate line, the storage capacitors belonging to the pixel are alternately connected to different gate lines. 10. A selection pulse is sequentially applied to the gate line during one frame to select the pixel, and a video signal of the source line is written to the pixel electrode via a switching element of the selected pixel. The voltage of the gate line includes a voltage for capacitive coupling that changes a certain amount in the positive or negative direction after the selection of the pixel to which the storage capacitor connected to the gate line belongs is completed. 10. The liquid crystal according to claim 9, wherein the storage capacitors belonging to the pixels adjacent to each other along the gate line with different polarities are alternately connected to the gate line in the previous stage and the gate line in the previous stage. Display device. 11. The liquid crystal display device according to claim 10, wherein the amount of change in the voltage for capacitive coupling of the gate line is the same in the change in the positive direction and the change in the negative direction. 12. The liquid crystal display device according to claim 10, wherein the amount of change in the voltage for capacitive coupling of the gate line has different magnitudes in the change in the positive direction and the change in the negative direction. 13. A liquid crystal layer for applying a voltage between the pixel electrode and a surface of the two substrates facing each other with the liquid crystal layer sandwiched therebetween. The liquid crystal display device according to claim 1, wherein a counter electrode is formed. 14. For applying a voltage to the liquid crystal layer between the pixel electrode and a surface of the two substrates facing each other with the liquid crystal layer interposed therebetween, the second substrate facing the liquid crystal layer. The liquid crystal display device according to claim 1, wherein a counter electrode is formed. 15. A source-side drive circuit is provided, and an input signal to the source-side drive circuit is inverted in positive and negative charging periods, and gradation-signal voltage characteristics of the source-side drive circuit are substantially symmetrical. 15. The liquid crystal display device according to claim 1, wherein the liquid crystal display device has the following characteristics. 16. One horizontal scanning period is divided into a plurality of periods, pixels corresponding to positive and negative signal polarities are charged in different periods within the horizontal scanning period, and the pixels of the signal polarities of the divided periods are charged. Gradation of the source side drive circuit according to positive or negative −
15. The liquid crystal display device according to claim 1, wherein the signal voltage characteristics are switched.