JPH02136083A - Motor speed controller using microcomputer - Google Patents

Abstract

PURPOSE:To prevent runaway of program by prohibiting interruption processing when the frequency of a frequency generator(FG) signal increases abnormally due to noise and the like. CONSTITUTION:Upon start of main processing, a RAM9 is cleared and an initial value is set. Then a mode command signal 15 fed from a system control circuit 13 is decoded and a speed reference is selected and stored in the RAM9. Thereafter, it is judged whether interruption is allowable and a program is executed only when an interruption request flag is set. It is judged whether interruption is allowed by inspecting the interruption allowing pulse. If interruption is not allowed, abnormal rotation of a motor 1 is alarmed to the system control circuit 13, which then stops operation of the system entirely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a motor speed control device using a microcomputer.

BACKGROUND ART In recent years, motor rotational speed control technology has shifted from analog control technology to digital control technology, and has further evolved to control technology using microcomputers (hereinafter simply referred to as microcomputers).

A normal motor speed control device uses a pulse signal with a period corresponding to the motor's rotation speed obtained from a frequency generator (FG) attached to the motor (to keep the period of the FG multiplied signal constant). A method of controlling the rotational speed is used.

Conventional speed control devices using a microcomputer measure the FG double signal period, calculate the difference from the reference period using the microcomputer to obtain a speed error amount, and then adjust the motor rotation speed based on this speed error amount. is under control. The method for measuring the FG double signal period is to latch the value of the cyclic counter every time an FG double signal edge is detected, and also generate an interrupt pulse to the microcomputer. An operation was performed to measure the period of the pulse signal based on the value of the cyclic counter that was lied within the processing loop. This interrupt processing loop is performed as an interrupt processing loop with a relatively high priority. This is because when controlling the motor rotation speed, the higher the FG multiplier signal frequency, the higher the control response frequency.
The G-fold signal frequency is set as high as possible. and F
In order to perform calculations such as period measurement within one period of the G times signal,
This is because if the calculation is not performed immediately when the FG double signal edge is detected, the calculation processing time will not be enough.

Problems to be Solved by the Invention However, in the conventional configuration described above, when the FG double signal frequency becomes abnormally high, the calculation time of the interrupt processing loop, which has a relatively high priority, cannot keep up, and only interrupt processing is continuously performed. This may result in a state in which various other computations with relatively low priority are not performed. This state will be referred to as a runaway state here. A phenomenon in which the FG double signal frequency becomes abnormally high occurs when the motor runs out of control for some reason or when FG double signal noise is superimposed. Equipment that requires motor rotation speed control,
For example, in a magnetic recording/reproducing device, one microcomputer controls the rotational speed of several motors. For example, it controls the rotation speed of a drum motor, capstan motor, reel motor, etc. At this time, if the speed processing loop of the motor with the highest FG double signal frequency, such as the capstan motor, goes out of control, the coordination between the capstan motor and reel motor will not work properly, and abnormal tension will be applied to the magnetic tape, or the There is a problem in that the tape becomes slack and damages the magnetic tape.

Furthermore, in devices where a single microcomputer is used as a system control unit that controls each motor and the operation of the entire device, there is a problem that the device cannot be operated in a runaway state.

Conventional motor speed control devices using microcomputers have no measures against this type of runaway.

The present invention provides a motor control device using a microcomputer that detects runaway when the FG double signal frequency becomes abnormally high and avoids a runaway state in which calculations are performed only within a specific loop. purpose.

Means for Solving the Problem In order to achieve this object, a motor speed control device using a microcomputer according to the present invention includes a pulse signal generating means for generating a pulse signal according to the rotation speed of the motor;
Interrupt signal generation means for generating an interrupt pulse at the rising edge or falling edge of this pulse signal; latch means for overwriting the value of a cyclic counter each time the interrupt pulse is generated; a first microcomputer that performs arithmetic processing such as the amount of rotational speed error of the motor; and a motor drive circuit that drives the motor according to the amount of rotational speed error, and that performs various calculations when the interrupt signal arrives. arithmetic loop,
a second calculation loop that performs various calculations with a lower priority than the first calculation loop, and an interrupt count measuring means that is incremented each time the first calculation is performed in the first calculation loop; , means for inhibiting each operation of the first calculation loop when the measured value of the interrupt count measurement unit exceeds a certain value, and the second calculation loop includes a unit for measuring the number of interruptions. What is the configuration that includes means for setting the measured value of the means to a constant value?

Effect The present invention has the above-described configuration, so that each process of the first calculation loop and the second calculation loop is executed during normal operation.
The value of the interrupt count measuring means that is incremented in the first calculation loop is always reset to a constant value in the second calculation loop. Therefore, the value of the interrupt count measuring means never exceeds a certain value. Moreover, since only the processing within the first calculation loop is performed during abnormal operation, the value of the interrupt count measuring means increases. Therefore, if the value of the interrupt count measurement means exceeds a certain value, each process in the first calculation loop is prohibited, and this is detected in the second calculation loop to bring the operation of the device in a safe direction. be able to.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a specific embodiment of the present invention.

In the figure, 1 is a motor, and 2 is a frequency generator (FG) that generates a signal with a frequency corresponding to the number of rotations of the motor. The signal is taken out from the FG, is amplified by the FG double signal amplification circuit 3, and is input to the microcomputer 4. The microcomputer 4 includes a latch circuit 5, a cyclic counter 6, and a central processing unit (CPU).
) 7, ROM 8, RAM 9, and D/A converter 10. The cyclic counter 6 receives the clock signal 11
It is a counter that counts , and starts counting again from zero if it overflows. The launch circuit 5 latches the count value of the cyclic counter 6 at the rising edge of the FG multiplied signal, for example. Further, the rising edge of the FG double signal is used as an interrupt signal 12 for the CPU. Reference numeral 13 denotes a system control circuit, which determines the current operating mode from a key input signal inputted from a terminal 14 and supplies a mode command signal 15 to the microcomputer 14.

The microcomputer 14 creates a speed reference value based on this mode command signal, and outputs a speed error signal 16 via the D/A converter 10 so that the FG multiplied signal period is equal to the speed reference value. 17 is a motor drive circuit, and speed error signal 1
Motor 1 is driven based on 6. Further, the microcomputer 4 supplies a signal 18 indicating that the rotation speed of the motor is abnormal to the system control circuit 13.

Although the system control circuit 13 is shown as a separate route in this example, the system control circuit 13 may be built into the microcomputer 4 if the ROM capacity and calculation speed of the microcomputer 4 are sufficient.

Next, the processing procedure of the microcomputer 4 will be explained using FIGS. 2 and 3.

FIG. 2 is a flowchart of the main processing.

This main processing is a relatively low priority processing routine that starts processing when the power is turned on.

In the figure, 21 is a symbol indicating the start of main processing. 22 is a process for clearing the RAM, and 23 is a process for setting initial values. 24 is a process for decoding the mode command signal 15 supplied from the system control circuit 13, and 25 is a process for selecting a speed reference value according to the decoded mode and storing the speed reference value in the RAM (VS). It is. The symbol with 0 is a symbol indicating the address of the RAM, and RAM (VS) will hereinafter be simply written as (vS). 26 is a process for determining whether or not interrupts are permitted. Interrupt processing is first performed when an interrupt permission flag is set and an interrupt request flag, which is set by the arrival of an interrupt pulse, is set.

Therefore, unless either one of the flags is set to "Say", the interrupt processing will not be executed. Furthermore, the interrupt permission flag can be set by a program, and the current state of the interrupt permission flag can also be known. The determination process 26 checks this interrupt permission flag to
It is possible to determine whether or not interrupts are permitted. If interrupts are permitted, process 27 is executed.

27 stores the number of interrupt processing to be described later (CTI
), and this example shows an example in which a value of zero is stored. If interrupts are not permitted, process 28 is executed. Step 28 is a process for notifying the system control circuit 13 that the rotation of the motor is abnormal.

When the system control circuit 13 receives this abnormality signal, it takes measures such as stopping the operation of the entire device.

Reference numeral 29 denotes a safety process, in which, for example, a process such as stopping the rotation of the motor 1 is performed. The main process executes each process from 24 onwards until the interrupt process is performed.

FIG. 3 is a flowchart showing the procedure of interrupt processing. Interrupt processing is performed by interrupting main processing when an interrupt pulse arrives with the interrupt permission flag set.

In the figure, 31 is a symbol indicating the start of interrupt processing. 32 measures the number of interrupt processing (CT I
) is the process of incrementing the value. (CTI
) is set to zero in the process 27 performed in the main process as described above, so it will never exceed a certain value as long as the main process is executed. However, when the FG double signal frequency becomes abnormally high due to noise or the like, only interrupt processing with relatively high priority is executed, and the value stored in (CTI) increases. 33 is a process of determining whether the value of (CT I ) is smaller than a constant value N or not.

The value of N is set to a value somewhat larger than the value at which interrupt processing is performed most frequently in each operation mode.

When the value of (CT I ) is smaller than N, 34
Execute the following processing. 34 is a process of storing the count value latched by the latch circuit 5 in (CTN).

35 subtracts the last latched count value stored in (CTO) from the value of (CTN), and converts the subtraction result to (
CT). In 36, the value of (CT) is subtracted from the speed reference value stored in (VS), and (vE
). 37 sets (CTo) to (CTo) in order to set the current count value to the previous count value during the next interrupt processing.
This is the process of storing the value of CTN).

38 is a process for calculating a digital filter based on the value of (VE), and 39 is a process for outputting the result of this calculation as a motor drive voltage value.

Note that the processes 38 and 39 do not necessarily need to be performed in the interrupt process shown in FIG. 3, and may be performed in a timer interrupt process, etc., which has a lower priority than this interrupt process. 40 is a process of setting an interrupt enable flag in order to re-enable interrupts. In a normal microcontroller, −
When an interrupt occurs, the interrupt processing permission flag is automatically reset, so it is necessary to reset the interrupt permission flag every time an interrupt is processed. 41 is a symbol for ending interrupt processing.

If the value of (CT I ) is greater than or equal to N, the process branches to process 41 in determination process 33, and the interrupt process ends. At this time, since the interrupt permission flag is not set again, the interrupt processing shown in FIG. 3 will not be performed from now on.

Effects of the Invention As is clear from the above explanation, according to the present invention, there is provided a means for measuring the number of interrupts that is incremented each time an interrupt process is performed, and a means for measuring the number of interrupts that is incremented each time an interrupt process is performed, and stopping the interrupt process when this measured value exceeds a certain value. In order to perform processing to reset the number of interrupts to a constant value in the main processing, when the FG double signal frequency becomes abnormally high due to noise etc. , prevent the program from running out of control by disabling interrupt processing,
This has the effect of changing the entire device to a safe operating mode.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific embodiment of the present invention, FIG. 2 is a flowchart showing a main processing procedure according to the invention, and FIG. 3 is a flowchart showing an interrupt processing procedure according to the invention. 2... Frequency generator, 4... Microcomputer, 5
... Latch circuit, 7 ... Central processing unit FfU device, (VS) ... R A Ml (for storing speed reference value)
CTI)...RAM that stores the number of interrupt processing, (
CTN)...RAM that stores the current count value. (CTO)...RAM that stores the previous count value. (CT)...R A Ml that stores the difference value between the current count value and the previous count value. (VE)...R A M that stores the speed error m. Name of agent: Patent attorney Shigetaka Awano (No. 1)

Claims (1)

[Claims] pulse signal generating means for generating a pulse signal according to the rotational speed of the motor; interrupt signal generating means for generating an interrupt pulse at the rising edge or falling edge of this pulse signal; and a cyclic counter each time the interrupt pulse is generated. , a microcomputer that performs arithmetic processing such as a rotational speed error amount of the motor based on the latched value, and a motor drive circuit that drives the motor in accordance with the rotational speed error amount. a first calculation loop that performs various calculations when the interrupt signal arrives; and a second calculation loop that performs various calculations with a lower priority than the first calculation loop; The arithmetic loop includes an interrupt count measuring means that is incremented each time a first arithmetic operation is performed, and each arithmetic operation of the first arithmetic loop is prohibited when the measured value of the interrupt count measuring means exceeds a certain value. A motor speed control device using a microcomputer, characterized in that the second calculation loop includes means for setting the measured value of the interrupt count measuring means to a constant value. .