JPH02136029A - Current limiter circuit - Google Patents

Abstract

PURPOSE:To limit a current supplied to a load from a transistor by placing a determined constant-current source of the two constant-current sources in an off-condition by decreasing an output current of a current mirror circuit smaller than in the past, when load terminal voltage is decreased to not more than a predetermined value with a load resistance value decreased. CONSTITUTION:When electric potential Vo of an output terminal 3 reaches a point P1 obtaining a relation where Vo=VrefXR7+R8/R8 (where, R7: resistance value of resistor 7, R8: resistance value of resistor 8), a contact opening control output is obtained from a comparator 9, and by this output, a normally- closed contact 5 is switched to an off-condition. Consequently, a current mirror circuit 1 generates only a flow of fine constant current Iidle by the second constant current source CS2, and current supplying capacity to an external load 4 by an NPN transistor Q3 is decreased by that amount. Accordingly, the potential Vo of the output terminal 3 is dropped approaching a zero level, and a load current Io is limited to a microcurrent of Ioff, that is, to an off-current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current limiting circuit for limiting a load current to a current value within a predetermined range.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional configuration of this type of current limiting circuit. In the figure, the current mirror circuit 1 consists of two )) N P transistors Q1. One PNP transistor Q1 has its base and collector connected to function as a diode, its emitter is connected to the power supply vC6, and its collector is connected to a constant current ■
is connected to one terminal of a constant current source O8 that flows, and the other terminal of the constant current source O8 is grounded. The base of the PNP transistor Q1 is connected to the base of the other PNPt-transistor Q2, and the emitter of the PNP transistor Q2 is connected to the power supply ■. 0 and the collector is connected to N
Connected to the base of P N h range star Q3. The collector of the NPN transistor Q3 is connected to the power supply CC through the resistor 2, and the emitter is connected to the output terminal 3. The base of a PNP transistor Q4 is connected to the collector of this NPN transistor Q3, and its P
The emitter of the NP transistor Q4 is connected to the power supply VCC, and the collector is connected to the two P N of the current 1-mirror circuit 1.
P) - transistor Q1. Connected to the base of Q2.

An external load 4 is connected between the output terminal 3 and ground.

Next, the operation of the current limiting circuit will be explained.

The collector current flowing through the PNPI transistor Q2 of the current mirror circuit 1 is given as a base current to the NPNI transistor Q3, and the current I flows through the NPN transistor Q3. flows. This current I.゛ is the load current supplied from the output terminal 3 to the external load 4. Now, hypothetically, resistance 2
Assuming that there is no PNPI transistor Q4,
The constant current I flowing through the constant current ics and the current R1 are connected to the output side of the current mirror circuit 1, that is, the PNP transistor Q2.
is supplied to the base of NPN transistor Q3 from the collector of
load current I of fo. It will have the ability to flow. Therefore, when the resistance value R4 of the external load 4 becomes extremely small, or when the output terminal 3 is grounded, the load current becomes ■. Since h<the maximum value, a large amount of power will be consumed. Particularly, when this current limiting circuit is incorporated into an integrated circuit, the package of the integrated circuit cannot withstand the heat generated by the power consumption, resulting in destruction of the integrated circuit. However, in reality, the load current■. When becomes more than a certain value, resistance 2 (the resistance value is R2)
Voltage drop due to I. XR2 is PNP transistor Q4
becomes larger than the base-emitter voltage vBE of
This PNPi-transistor Q4 starts to turn on, and as a result, the current mirror circuit 1 turns off and the load current I.

is limited.

FIG. 4 shows the voltage V at the output terminal 3 and the load current I as the resistance value R4 of the external load 4 changes. This is a characteristic diagram showing the relationship, that is, the load characteristics. In the figure, the arrow △ at d3 indicates the direction in which the resistance value R4 of the external load 4 decreases, and the arrow B indicates the direction in which the resistance value R4 of the external load 4 increases. In the figure, as the resistance value R4 of the external load 4 becomes smaller, the characteristic curve changes as shown by the solid line O-+P, and the load current I changes.

If the circuit shown in Fig. 3 does not include the circuit section consisting of resistor 2 and PNP transistor Q4, the characteristic curve will change as shown by the dotted line 20M, and the load current 1 will increase.
reaches I and becomes o max . 1) However, in reality, the above-mentioned resistor 2 and PNP
Due to the function of the circuit section consisting of I-Landisk Q4, the zero charge current l becomes. At the moment when the load current I is about to flow, the characteristic curve changes as shown by the solid line P → N, and eventually
. is suppressed from ■th to a minute current Δ■ (off current).

(Problems to be Solved by the Invention) In the conventional current limiting circuit described above, the boundary point between starting and stopping the current limiting operation is set when the load current IO satisfies the condition 1oXR2=V8[-(2). Therefore, the accuracy of the resistance value R2 of the resistor 2 directly influences the accuracy of the current limiting operation.

In actual circuits, a value of several 10 to 100 ohms is usually used as the resistance value R2 that satisfies the above conditions, but it is generally difficult to achieve such a resistance value with high precision in semiconductor integrated circuits. Therefore, when the above-described conventional current limiting circuit is incorporated into an integrated circuit, there is a problem that highly accurate operation cannot be expected.

Also, the load current I. When is near the current value that satisfies the condition of equation (2), the moment the PNPI transistor Q4 turns on, the current limiting operation is performed and the voltage drop due to the resistor 2 instantly becomes zero. PNP transistor Q4 returns to the OFF state, and the next current limiting operation begins immediately after returning to the OFF state. This has a serious problem in that it exhibits the R1 state in which the on/off state is repeated, and the current does not reach a minute current Δ■ (off current) forever.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a current limiting circuit that can perform accurate current limiting operations and stabilize off-state current during current limiting operations.

[Means to solve the problem]

The Ti current limiting circuit according to the present invention includes a current mirror circuit, two constant current sources connected in parallel to each other on the diode side of the current mirror circuit, and a control electrode receiving the output current of the current mirror circuit to load the Ti current. The device is provided with a transistor for supplying current to the load, and means for turning off one of the two constant current sources when the voltage between the terminals of the load is below a predetermined value.

[Effect]

In this invention, when the resistance value of the load decreases and the voltage between the terminals of the load becomes equal to or less than a predetermined value, one of the two constant current sources is turned off. Therefore, the output current of the current mirror circuit becomes smaller than before, and accordingly, the current supplied from the transistor to the load is limited.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the current limiting circuit according to the present invention, and 1, 3.4. Ql to Q3°Voo are the same as in the above conventional circuit. That is, the Karen Mill-mirror circuit 1 includes two PNPt-transistors Q1. One PNP transistor Q1 has its base and collector connected to function as a diode, its emitter is connected to the power supply V, and its base is connected to the base of the PNP transistor Q2 of C2. The emitter of the PNPt transistor Q2 is connected to the power supply vco, and the collector is connected to the base of the NPN transistor Q3. The emitter of this NPN transistor Q3 is connected to an output terminal 3, and an external load 4 is connected between this output terminal 3 and ground.

Further, in the case of this current limiting circuit, two constant current sources C81 and C32 are connected in parallel to the diode side of the Karen Mill mirror circuit 1, that is, the collector of the PNPI transistor Q1. That is, one terminal of the first constant current source C31 through which a constant current I flows is connected to the collector of the PNP transistor Q1, and the other terminal is grounded via the normally open contact 5. In addition, a second constant current ICSD that flows a constant current ■ which is smaller than the constant current ■ mentioned above
One terminal of le2 is connected to the collector of the PNP transistor Q1, and the other terminal is grounded.

On the other hand, the collector of the NPN transistor Q3 is connected to the power supply V through a resistor 6. Connected to 0. Also, this NPNI
- Two dividing resistors 7, 8 are connected in series between the emitter of transistor Q3 and the ground, and these dividing resistors 7, 8 are connected in series.
The dividing point S is connected to one input terminal of a comparator 9, and the other input terminal of this comparator 9 is connected to a predetermined reference voltage Vre.
A reference voltage source 10 that generates f is connected. The output of the comparator 9 is configured to turn off the normally closed contact 5 described above. That is, base T?
−Voltage■,. , is the load current I supplied to the external load 4
is set to be equal to the 0[1 m potential V1 of the dividing point S when is a predetermined current value I.

FIG. 2 is a characteristic diagram showing the relationship between the voltage vO of the output terminal 3 and the load current IO as the resistance value R4 of the external load 4 changes. In the figure, arrow A indicates a small resistance value R4 of the external load 4. The arrow B indicates the resistance value R of the external load 4.
4 indicates the direction in which it becomes larger.

Next, the operation of the current limiting circuit will be explained with reference to the characteristic diagram shown in FIG.

The output current of the current mirror circuit 1, that is, the collector current flowing through the PNP transistor Q2, is given to the NPNI transistor Q3 as a current, and the current flows through the NPN transistor Q3. . flows. This current I. is the load current supplied from the output terminal 3 to the external load 4. When the resistance value R4 of the external load 4 is sufficiently large and the potential V1 of the dividing point S obtained by dividing the potential (IoxR4) of the output terminal 3 by the dividing resistor 7.8 is greater than the reference voltage Vrof, the comparator 9 releases the contact. Control output is not taken out,
The normally closed contact 5 is kept in the on state, and the two constant current sources C31
, C82 are both turned on.

When the resistance value R4 of the external load 4 decreases, the characteristic curve changes from 01 to P1, as shown by the solid line in FIG. 2, and the load current becomes ■. As increases, the potential of output terminal 3 ■
. gradually decreases. And the potential ■ of output terminal 3. is R7+R8 V0=v゛°fxR8...(3) However, R7: resistance value of resistor 7 R8: resistance value of resistor 8 Pl in Fig. 2 (load current 11 at this time,
tl), a contact-to-contact OLim number control output is obtained from the comparator 9, and this output switches the normally closed contact 5 to the OFF state. Therefore, the current mirror circuit 1 is supplied with a minute constant current I from the second constant current source C82.
Therefore, the ability of the NPNdle 1 helang transistor Q3 to supply current to the external load 4 becomes correspondingly smaller. Therefore, the characteristic curve changes as shown by the solid line in FIG. 2 from P1 to N1, and the output terminal 3
potential V. drops to near zero level, and the load current I. ■. 7. Therefore, the current is limited to a very small current, that is, a re-off current.

- After transitioning to current limiting operation, the minute constant current 1
Therefore, in order to return to the original state, it is necessary to increase the resistance value R4 of the external load 4 by a considerable amount, and therefore, the oscillation state does not occur.
Stable current limiting operation. In addition, the critical point at which the current limit operation shifts is determined by the reference voltage ■
and the resistance ratio (R7+R8)ef/R8, which can be set relatively freely and accurately. Therefore, by using a differential amplifier type comparator with high operating accuracy as the comparator 9, accuracy can be achieved. This enables efficient current limiting operation.

The potential V of the output terminal 3 due to the minute constant current I.

dle is V,. If the constant current source C82 is set so that r As shown by the solid line in the figure, N1
→P1, the potential vo of the output terminal 3 gradually rises, and the comparator 9 operates so as to return the constant current IC 81 to the on state again.

In the absence of the control 11 function by the comparator 9, as the resistance value R4 of the external load 4 increases, the characteristic curve changes to 219M1 as shown by the broken line in FIG. 2, and the load current
is the maximum value .Omax is the same as explained in the conventional circuit. In this case, the output current of the mirror circuit 1 to the current 1 is l-1-I
Therefore, the dlc current amplification factor of NPNI transistor Q3 is: Then, the above load current I. The maximum value I of is h(1+■).

maxfc 1dle Note that in the above actual f fan example, each P N Ph transistor Q1 .L of the current mirror circuit 1. An emitter resistor may be inserted into Q2 to arbitrarily change the current mirror ratio. In this case, the degree of freedom in setting the values of the constant currents I and I of the two constant current sources C81 and C32 increases, so the load current I. each value 1
, r , 1 are changed and set to max.
Iim off , the current limiting circuit can be widely used.

〔Effect of the invention〕

As described above, according to the present invention, when the resistance value of the load decreases and the voltage between its terminals becomes less than a predetermined value, one of the two constant current sources is turned off, thereby causing the current Since the output current of the mirror is made small and the load current is limited, the current limiting operation becomes accurate and the off-state current during the current limiting operation is stabilized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the current limiting circuit according to the present invention, FIG. 2 is a characteristic diagram showing the load characteristics of the circuit, FIG. 3 is a circuit diagram showing a conventional current limiting circuit, and FIG. is a characteristic diagram showing the load characteristics of the circuit. In the figure, 1 is a current mirror circuit, 3 is an output terminal,
4 is an external load, 5 is a normally closed contact, 7 and 8 are dividing resistors, 9 is a comparator, 10 is a base F\voltage source, C81 and C82 are constant current sources, and Q3 is an N P N transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Diagram Current Mirror Circuit ヱ fJ Tachiaki) Kuto Makoto @ 1 Disclaimer NPN) Ransisk'Lim Imax=hfe(1+[;d+e) Page Chuden Asa■.

Claims (1)

[Claims] (1) A current mirror circuit, two constant current sources connected in parallel to each other on the diode side of the current mirror circuit, and a transistor that receives the output current of the current mirror circuit at its control electrode and supplies the current to the load. , means for turning off a predetermined one of the two constant current sources when the voltage across the terminals of the load is below a predetermined value.