JPS6156529B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit for a processing device, such as a microcomputer, which resets the processing device when its energizing voltage drops to prevent it from running out of control.

A microcomputer may run out of control when its energizing voltage abnormally drops below a specified value, and therefore, in such a case, it is necessary to return to the initial step of the program and be reset.

An object of the present invention is to provide a circuit for resetting a processing device when the energizing voltage of the processing device drops abnormally.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. The voltage from the DC power supply 1 is given to a processing device 3 such as a microcomputer through a line 2,
As a result, the processing device 3 is energized. The processing device 3 has a reset input terminal 4, and when a low level signal is applied to the reset input terminal 4, a reset operation is performed by returning to the initial step of the program. A resistor R6 and a switching transistor Q8 are connected in series between line 2 and ground. The connection point 5 between the resistor R6 and the switching transistor Q8 is connected via a line 6 to the reset input terminal 4 of the processing device 3. The respective collectors of multi-collector transistors Q3 and Q4 in the current control circuit 7 including multi-collector transistors Q3 and Q4 are connected to lines 8 and 9.
is applied to the diode Q6 of the current mirror circuit 10 and the collector of the transistor Q7. Line 9 is also connected to the base of switching transistor Q8. Lines 11,1 connected to the bases of multi-collector transistors Q3, Q4
2 is connected to a temperature compensated reference voltage generation circuit 13.

Assuming that the currents flowing in lines 11 and 12 of the current control circuit 7 are Ic1 and Ic2, and the currents flowing in lines 8 and 9 as Ic3 and Ic4, the multi-collector transistors Q3,
Q4 collector ratio is selected.

Ic1=Ic3...(1) Ic2=Ic4...(2) In the current mirror circuit 10, a current control operation is performed so that the current IQ7 flowing to the collector of the transistor Q7 and the current Ic3 become equal as shown in the third equation. will be carried out.

IQ7=Ic3 (3) The temperature compensated reference voltage generation circuit 13 includes transistors Q1 and Q2 whose collectors are connected to lines 11 and 12, respectively, a first resistor R3 connected in series with the transistor Q2, and a first resistor R3 connected in series to the transistor Q2. 1 resistor R3 and second resistors R4 and R5 connected in series to a connection point 16 between the first resistor R3 and the emitter of the transistor Q1. The bases of transistors Q1 and Q2 are connected to resistors R1 and R
It is connected to the connection point 15 of No. 2 via the line 14. Resistors R1 and R2 divide the power supply voltage via line 2.

A hysteresis generating transistor Q5 is connected in parallel to the resistor R5, and the base of the hysteresis generating transistor Q5 is connected to the connection point 5.

Assuming that the voltage at the connection point 15 is V15 and the voltage between the base and emitter of the transistor Q1 is VBE2, the fourth equation holds true when the hysteresis generating transistor Q5 is cut off.

V15=VBE2+(Ic1+Ic2)(R4+R5)...(4) In order to obtain a reference voltage having an extremely low temperature coefficient, Ic1=Ic2 is set, and the fifth equation holds true. Here, k is Boltzmann's constant, q is the electron charge, and n is the electron density.

Therefore, the reference voltage V15 is obtained from the fourth equation and the fifth equation as shown in the sixth equation.

If the reference voltage V15 is selected to be 1.20V, which is equal to the energy gap voltage of silicon, by setting the value of (R4+R5)/R3 and the emitter area ratio of transistors Q1 and Q2, the temperature coefficient can be made almost zero. can. The first term of the sixth equation is approximately −
It has a negative temperature characteristic of 2mV/℃, and the second term is approximately +
It has a positive temperature characteristic of 2mV/℃. In this way, it is possible to maintain the reference voltage V15 at a constant voltage that is independent of temperature. In this way, V15 is 1.20V
By selecting Ic2=Ic1. Resistors R1 and R2 are determined so that V15 is 1.20V or more when the power supply voltage is normal.

The operation will be explained with reference to FIG. line 2
Switching transistor Q8 is cut off in the range from point o where the power supply voltage is zero to point a, so the voltage at connection point 5 increases as the power supply voltage rises as shown in Figure 2. do. When the power supply voltage reaches voltage Vb, switching transistor Q8 becomes conductive, so that connection point 5 becomes low level. This leaves the processing device 3 in a reset state. When the power supply voltage further increases and reaches voltage Vc at point c, voltage V at connection point 15
15 is higher than 1.20V, so Ic3>Ic4 (7). Therefore, the transistor Q7 of the current mirror circuit 10 becomes conductive, thereby the switching transistor Q8 is cut off, and the hysteresis generating transistor Q5 becomes conductive. By blocking switching transistor Q8, connection point 5
And the reset input terminal 4 changes from low level to high level. In this way, the state moves to points c and d, and after this point d, the voltage at the reset input terminal 4 increases as the power supply voltage increases. The voltage Vg at the connection point 15 at which Ic1 = Ic2 in the reference voltage generation circuit 13 due to conduction of the hysteresis generation transistor Q5 is the voltage Vg at the connection point 15 at which Ic1 = Ic2 due to the disconnection of the hysteresis generation transistor Q5. Voltage V15 compared to voltage Vc of 15
It will be lower by 1.

V151 = Vc - Vg = (Ic11 + Ic21) R5 - VCE5 ... (8) Here, let the saturation voltage between the collector and emitter of the hysteresis generating transistor Q5 be VCE51, and Ic1 when Ic1 = Ic2 when the transistor Q5 is cut off. , Ic2 as Ic11, Ic21
It is expressed as

Next, assume that the power supply voltage decreases and the voltage at the reset input terminal 4 changes from point e to point d in FIG. 2 and reaches point f. At point f, Ic1=Ic2.

As the voltage V15 further decreases from the value at point f, Ic3<Ic4 (9), which makes the switching transistor Q8 conductive and resets the reset input terminal 4 of the processing device 3.
becomes a low level, resulting in a reset state, that is, point g in FIG.

When the power supply voltage further decreases and reaches point b, the hysteresis generating transistor Q5 is cut off, and as the power supply voltage becomes lower than after point a, the voltage at the reset input terminal 4 decreases.

In another embodiment of the present invention, the hysteresis generating transistor Q5 may be omitted. At that time, as the power supply voltage increases, o
→a→b→c→d→e, and when the power supply voltage decreases, e→d→c→b→a→
Follow the progress of o.

The embodiments described above can be implemented by integrated circuits and occupy a small footprint;
The number of components is small, the power supply voltage at which the reset is performed can be set accurately, the hysteresis voltage (=Vc - Vg) can be set accurately, and the minimum operating voltage is, for example, approximately
It has the advantage of being low at 2V and having good temperature characteristics.

If the processing device 3 is configured to reset when the reset input terminal becomes high level, an inverting circuit may be provided in the line 6.

As described above, according to the present invention, when the energizing voltage of a processing device drops abnormally, the voltage applied to the reset input terminal of the processing device drops rapidly, so that it is possible to reliably prevent the processing device from running out of control. It can be prevented. When the processing equipment is operating normally and the power supply voltage decreases, the processing equipment continues to operate normally until the power supply voltage immediately before runaway occurs due to conduction of the hysteresis generation transistor. Therefore, the processing device will not be reset unnecessarily when the power supply voltage drops.

[Brief explanation of the drawing]

Fig. 1 is an electrical circuit diagram of an embodiment of the present invention;
The figure is a graph for explaining the operation. 1...Power source, 3...Processing device, 4...Reset input terminal, 7...Current control circuit, 10...Current mirror circuit, 13...Reference voltage generation circuit, Q1-Q
8...Transistor, R1-R6...Resistor.

Claims (1)

[Claims] 1. The processing device has a reset input terminal, and when a predetermined level signal is applied to the reset input terminal, it performs a reset operation, and changes to a switching mode in which a signal at the level is given to the reset input terminal. a current mirror circuit 10 that operates so that the supplied currents are equal; and a reference voltage generation circuit 13 that includes first and second transistors Q1 and Q2 whose bases are commonly connected. The emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 via the first resistor R3, and the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 via the first resistor R3. In such a reference voltage generation circuit 13, the emitter of the transistor Q1 is grounded via the second resistors R4 and R5.
supplying a current to the collector of the first transistor Q1, supplying a current Ic3 equal to the current Ic1 supplied to the first transistor Q1 to one input of the current mirror circuit 10, and supplying a current Ic3 to one input of the current mirror circuit 10;
2 and a current Ic4 equal to the current Ic2 supplied to the second transistor Q2.
1. A reset circuit for a processing device, comprising a current control circuit 7 which supplies a current to the base of a switching transistor Q8 and the other input of a current mirror circuit. 2. The processing device has a reset input terminal, and when a predetermined level signal is applied to the reset input terminal, a switching transistor Q8 that performs a reset operation and changes its switching mode to provide a signal of the level to the reset input terminal. , a current mirror circuit 10 that operates so that the supplied currents are equal; a reference voltage generation circuit 13 including first and second transistors Q1 and Q2 whose bases are commonly connected; and a first resistor R3. and second resistors R4 and R5, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2 via the first resistor R3, and the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2. Such a reference voltage generation circuit 13 is configured by being grounded via two resistors R4 and R5.
supplying a current to the collector of the first transistor Q1, supplying a current Ic3 equal to the current Ic1 supplied to the first transistor Q1 to one input of the current mirror circuit 10, and supplying a current Ic3 to one input of the current mirror circuit 10;
2 and a current Ic4 equal to the current Ic2 supplied to the second transistor Q2.
a current control circuit 7 that supplies the current to the base of the switching transistor Q8 and the other input of the current mirror circuit; and a hysteresis generating transistor Q5 connected in parallel to the second resistor R5. Q5 is
A reset circuit for a processing device, characterized in that an output voltage of a switching transistor Q8 is applied to its base, thereby cutting off when the switching transistor Q8 is turned on, and turning on when the switching transistor Q8 is turned off.