JPH02134915A - Flip flop circuit - Google Patents

Abstract

PURPOSE:To obviate a potential setting circuit to improve the degree of integration by providing a master flip flop and a slave flip flop constituting an ECLs. CONSTITUTION:A master flip flop SF which constitutes an ECL and forms a differential pair between a first transistor TR Q2 and second and third TRs Q3 and Q4 and a slave flip flop SF which constitutes an ECL and forms a differential pair between a fourth TR Q13 and fifth and sixth TRs Q9 and Q10 are provided. High levels and low levels of the signal obtained from a data line and an output signal setting signal are set to the same potentials, respectively, and the voltage of a reference signal is fixed to the middle potential. Thus, at least one of second and third TRs Q3 and Q4 is certainly turned on and the first TR Q2 is certainly turned off when the high level of the output signal setting signal is inputted to the base of the third TR Q4, and the potential setting circuit is unnecessary to improve the degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ECLI master-slave type flip-flop circuit provided with at least one of a set function and a reset function.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional master-slave flip-flop circuit with a reset function.

As shown in the figure, the flip-flop circuit consists of a master 7 flip-flop MF and a slave flip-flop S.
It is composed of F. Master 7 Lip Flop M
F is a differential circuit 1 that receives an input signal D, a differential circuit 2 is connected in cascade to the differential circuit 1 as an input stage of a clock T, and a data line L1. It consists of a potential setting circuit 3 that determines the 11H11 level of L2. On the other hand, the slave flip-flop SF is a differential circuit 4. which receives signals obtained from data lines L1 and L12. It consists of a differential circuit 5 which is cascade-connected to a differential circuit 4 and serves as an input stage for a clock T, and a potential setting circuit 6 which determines the "H"H" level of the output signals Q and Q.

Transistor Q2 of differential circuit 1. Q3. Q4 (all transistors described here are npn type) are transistors Q6. ECL for Q7 collector
and each base has a data line.2. Data line L1. Reset signal R1 is connected. In addition, the bases of transistors Q1 and Q5 each receive an input signal,
D is applied.

Transistors 06 to Q8 of differential circuit 2 are transistors Q
[)C1- is configured for the collector of transistor Q17, and a relet signal R2, a clock '', and a constant voltage v81 are applied to the bases of each.Furthermore, the emitter is connected to the base of a transistor Q17 whose emitter is grounded via a resistor. is constant voltage V,
. f is applied, and the transistor Q17 is always on.

Transistor Q9 of differential circuit 4. QIO, Q13 are transistors Q14.Q13 of the differential circuit 5. Configure the ECL for the [Q15] director, and connect the data line 1 to each base.
．． Reset signal R1 and data line L2 are connected. Furthermore, output signals Q and Q are taken out from the bases of transistors Q11 and Q12, respectively.

Transistors 014 to Q16 of the differential circuit 5 form an ECL with respect to the collector of the transistor Q18, and each base receives a reset signal R2°, a clock T, and a constant voltage V.
B1 is applied. Furthermore, a constant voltage Vro is applied to the base of the transistor Q18 whose emitter is grounded via a resistor.
[ is applied, and the transistor 018 is always on.

FIG. 4 shows "H" and "L" level data lines L1. of reset signals R1 and R2. L2' (output signal Q.

11 is a waveform diagram showing the "l Hll and "L II levels of Q), the II HII and 11 L I+ levels of the clock signal T, and the constant voltage V81. As shown in the figure, each potential level is in descending order: "("'" level of the reset signal R1, the "H"H" level of the data line L1 (L2), the II L II level of the reset signal R1, the data line Ll (1,
2>"'[Norbel, reset signal R2 and clock signal T'""H" level constant voltage V, 1, reset signal R
2 and the "L" level of the clock signal T.

The operation of the flip-flop circuit having such a configuration will be explained. First, we will explain the normal operation when the reset signals R1 and R2 are set to L''. In this case, when the clock signal T goes to the L I+ level and the transistor Q8 turns on, the input signal Due to the potential difference, one of the transistors Ql and Q5 of the differential circuit 1 whose emitters are connected to the ground level side is turned on, and the other is turned off. Accordingly, the transistor Q19 of the potential setting circuit 3. One of Q20 is turned on and the other is turned off.

As a result, data line L1. One of L2 becomes "H" level and the other becomes "L" level (for example, when D>D,
L2 becomes "H" and 11 becomes °"L"').

Next, when the clock signal T becomes HI+ level and the transistor Q15 is turned on, the potential difference between the data lines L1 and 12 causes one of the transistors Q9 and Q13 of the differential circuit 4 whose emitters are connected to the ground level side. is turned on and the other is turned off.Accordingly, one of the transistors Q21 and Q22 of the potential setting circuit 6 is turned on and the other is turned off.As a result, one of the output signals Q and Q becomes "lH".
II, the other is set to 111 II (e.g. L2
When is H''L1 is L'', Q is 'H'' L2 is L''L
When 1 is H'', Q becomes ``['']. In this way, during normal operation, the output signals Q and Q are determined according to the human input signal D.

Next, a description will be given of the hit operation when the reset signals R1 and R2 are set to the '1-1' level.

At this time, EC is applied to the collector of transistor Q17.
Among the transistors 06 to Q8 constituting L-, the transistor 1 to transistor with the highest base potential, that is, Q 6 i1
At least one of 3 and Ql is turned on. and,
PCI to the collectors of transistors Q6 and Ql
Among the 1-herald transistors 02 to Q4 forming the transistor Q4, the transistor Q4 having the highest base potential is turned on. Accordingly, transistors 1 to Q19 are turned on and Q20 is turned off. As a result, the pig wire L1 is at the i+ +'' IT level, and the L2 is at the “
It becomes 'L' level.

On the other hand, ECL is connected to the collector of transistor Q18.
Among the transistors 014 to 16 forming the transistors, the transistors with the highest base potential, that is, Ql4 and Ql5
At least one of them is turned on.

Then, transistors Q9゜Q10 constitute 13 CL@ for the collectors of transistors Q1/I and Ql5.
．． Among Ql3, the transistor Q with the highest base potential
10 turns on. Accordingly, transistor Q22 is turned on and transistor Q21 is turned off. As a result, the output signal Q becomes II
l II , Q becomes "H" level.

In this way, the reset signals R1 and R2 are '+-+'
When the level is reached, the data lines Ll and L2 are ``''L''
Regardless of the level, a reset is applied and the output j signal Q is set to "L". As mentioned in ``1'', the reset 1~ operation can be performed only when the ``l-1'' level of the reset signal R1 is set higher than the ``l-1'' level of the data line L1 (12) d3. Signal R1 is "' l
This is because when the level reaches -1'' level, the transistor Q4 (Q10) is always turned on among the transistors 02 to Q4 (Ql 0 - Ql 2>) forming E Cl-.

[Problem to be solved by the invention]

The conventional Noritsubu flop circuit with a reset function is configured as described above, and the '' of the data lines L1 and L2 is
It was necessary to set the l-1'' level lower than the l-1'' level of the reset signal R1.

For this reason, a potential setting circuit 3 is separately provided, and the power supply V is set by the resistor R of this potential setting circuit 3. . The level is divided into voltages, and the data line L1. The "H" level of L2 is lowered to below VCC, while the reset signal R1's internal level is set to VC. (Actually, there is also a voltage drop due to the voltage between the base and emitter of the transistor, but we will ignore it here.

).

In addition, the "H" and "L" level data lines L1 . In order to match the '+-+' and 't' levels of L2, a potential setting circuit 6 is separately provided. The "H" level of was also lower than V.0.

As a result, the number of elements required to form the potential setting circuits 3 and 6 increases, resulting in a problem that the degree of integration deteriorates.

The present invention was made to solve the above-mentioned problems, and therefore, it is an object of the present invention to obtain a Noritsu flop circuit with an improved degree of integration.

(Means for Solving the Problems) A flip-flop circuit according to the present invention is of a master-slave type in which at least one output signal setting function of a reset function and a set function is right-handed.
and has first to third 1-transistors to which a reference signal obtained from the outside, a signal obtained from an internal data line, and an output signal setting signal obtained from the outside are respectively applied to each base, A master flip 70 block forming a differential pair between the first transistor and the second and third transistors constitutes EC1-, and the reference signal and the data line J signal are obtained at each base.

4th to 6th to which the output signal setting signal is respectively applied;
and a slave flip-flop in which a differential pair is formed between the fourth transistor and the fifth and sixth transistors; The "111 I+ level" and the "11 I" III L I+ level of the output signal setting signal are set to the same potential, respectively, and the voltage of the reference signal is fixed at an intermediate potential between the "H" and "L" levels. .

[Effect]

In this invention, the first transistor has a base to which a constant voltage reference signal is input, and the second and third transistors have bases to which a signal obtained from a data line and a setting signal are respectively input.
Since a differential pair is formed between the transistors of the third transistor and At least one of them is always turned on, and the first transistor is always turned off.

〔Example〕

FIG. 1 is a circuit diagram showing a master-slave type flip-flop circuit which is an embodiment of the present invention. As shown in the figure, the potential setting circuit 3.6 and the data line L2 have been removed. Also, unlike the conventional case, a constant voltage V82 is applied to the base of the transistor Q2 in the differential circuit 1, and the base of the transistor Q3 is applied to the base of the transistor Q1. Connected to the collector of Q2.

On the other hand, a constant voltage V82 is applied to the base of the transistor Q13 in the differential circuit 4. In addition, the transistor Q11
The base of transistor Q12. The base of transistor Q12 is connected to the collector of transistor Q13, and the base of transistor Q12 is connected to the collector of transistor Q13.
9. Ql 0. Connected to the collector of Ql 1. The other configurations are the same as the conventional one, so explanations will be omitted. Note that the [first to sixth transistors] in this invention refer to the first to sixth transistors.
In the circuit shown in the figure, Q2 to Q4 respectively. Ql3. Q9. Q1
Corresponds to 0.

Figure 2 shows 1181111 L of reset signals R1 and R2.
II level, l H11 of data line L1, 111I+
level, the level of the clock signal T and the constant voltage VB1. FIG. 3 is a waveform diagram showing VB2. As shown in the figure, each potential level is, in descending order, the "H" level of the reset signal R1 and the data line L1, the constant voltage V82, the 11111 level of the reset signal R1 and the data line L1, and the "H" level of the reset signal R1 and the data line L1, and the 11111 level of the reset signal R2 and the clock signal T. "H" level,
The constant voltage VBl, the reset signal R2, and the "L" level of the clock signal are set in this order.

In this way, the 'H' and 'L' levels of the reset signal R1 and the data line L1 are set to the same potential, and the constant voltage V82 is set between them.

The operation of the flip-flop circuit having such a configuration will be explained. First, a normal operation in which the reset signals R1 and R2 are set to L'' will be explained. In this case, when the clock signal [-] goes to the L II level and the transistor Q8 is turned on, the potential difference between the input signal R and D causes , one of the transistors Q1 to Q5 of the differential circuit 1 whose emitters are connected to the ground level side is turned on, and the other is turned on. As a result, the potential of the data line L1 becomes the "H" level or the "L" level.

Next, when the clock signal T becomes "H" level and the transistor Q15 is turned on, the potential difference between the data line L1 and the constant voltage VB2 causes the transistor Q9. Ql
After 3, one is turned on and the other is turned off. As a result, one of the output signals Q and Q is set to "H" and the other is set to "L I+" (when Ll is it Hu, Q is set to 'L' and 11 is set to L).
”, Q becomes “HI+”). In this way, during normal operation, the output signals Q and Q are determined according to the human input signal D.

Next, the reset operation when the reset signals R1 and R2 are set to the "H" level will be described.

At this time, EC is applied to the collector of transistor Q17.
Among the transistors 06 to Q8 forming L, the transistor with the highest base potential, that is, at least one of Q6 and Ql is turned on. Then, among the transistors 02 to Q4 forming the ECL for the collectors of the transistors Q6 and Ql, at least one of the transistors having the highest base potential, that is, Q3 and Q4 is turned on. As a result, the data line L1 becomes "H11 level."

On the other hand, among the transistors 014 to 16 forming the ECL with respect to the collector of the transistor 018, the transistors with the highest base potential, that is, Ql4 and Ql5
At least one of them is turned on.

Transistors Q9, Q10 . Q
Among l3, the transistor with the highest base potential, that is, at least one of Q9 and Q10 is turned on. As a result, the output signal Q becomes L'' and Q becomes II H++ level.

In this way, when the reset signals R1 and R2 reach the "I" level, the data line L1's
Regardless of the I+ level, a reset is applied and the output signal Q is set to l L ++.

Furthermore, there is no need to set a potential difference between the data line 1-1 and the reset signal R1 at the "1-BIZllll+ level."
6 is not required, the number of elements can be reduced and the degree of integration can be improved.

In this embodiment, a master-slave type flip 70 block circuit with a reset function was described, but by reversing the polarities of the input signals D and output signals Q and Q, a master-slave circuit with a set function can be created. Needless to say, a type flip-flop circuit can be constructed.

〔Effect of the invention〕

As explained above, according to the present invention, there is a first transistor to which a constant voltage reference signal is inputted to the base, and a second transistor to which a signal obtained from the data line and an output signal setting signal are input manually to the base. Since a differential pair is formed between the second and third transistors, when the "H" level of the output signal setting signal, which has a higher potential than the reference signal, is input to the base of the third transistor, the second and third transistors form a differential pair. At least one of the third transistors is always on, and the first transistor is always off. Similarly, at least one of the fifth and sixth transistors is always on, and the fourth transistor is off. As a result, at least one of the fifth and sixth transistors is always on, and the fourth transistor is always off. , data line and output signal setting signal r
H++, 111 Even if the IT level is set to the same potential, set or reset operation is possible,
There is an effect that a circuit that generates a potential difference between the it H++ and rr LI+ levels is not required, and the degree of integration can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a flip-flop circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the potential level of each signal of the flip-flop circuit shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a Noritsubu flop circuit. FIG. 4 is a waveform diagram showing the potential level of each signal of the flip-flop circuit shown in FIG. 3. In the figure, MF is a master flip-flop, SF is a slave flip-flop, 1.2, 4°5 is a differential circuit, 01 to Q"18 are npnt-transistors, VBl"B
2 is constant voltage, 1 is 1. R2 is a reset signal, and Ll is a data line. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Yuko Procedural amendment (voluntary) 15/8 - 1999 Name of the invention Flip-flop circuit 3, relationship to the case of the person making the amendment Patent applicant address 2-2 Marunouchi, Chiyoda-ku, Tokyo No. 3 Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, "Detailed Description of the Invention" in the Specification Subject to Amendment 3 and 6 of the drawings, contents of amendment (1) In the second line of page 3 of the specification, the ``H'' level of l'L2 is corrected to ``'' and the level of rL2 is corrected to ``. (2) On page 3, line 7 of the specification, the ")" levels of IQ and Q are corrected to "" and the levels of rQ and Q are corrected to "." (3) Delete "The emitter is connected to the ground level side" from lines 16 to 17 on page 5 and lines 7 to 8 on page 6 of the specification. (4) rQ19. from page 5, line 20 to page 6, line 1 of the specification. One of Q20 is turned on and the other is turned off. ”, rQ19. One of the base potentials of Q20 is at the ``H'' level, and the other is at the II L II level.
Correct. (5) “When D>D” on page 6, line 3 of the specification,
[When D is “H” and D is “SH””. (6) IQ on page 6, line 10 to line 11 of the specification
One of 21.022 is turned on and the other is turned off. ”, rQ21. One of the base potentials of Q22 is “HI+”
level, and the other is L II level. ” is corrected. (7) [Q19 on page 7, line 7 to line 8 of the specification]
turns on and Q20 turns off. " is corrected to "The base potential of rQ19 is at the "H" level and the base potential of Q20 is at the "L"level." (8) “Q22 is turned on,” on page 7, line 19 of the specification.
Q21 turns off. ”, [The base potential of Q22 is “H”
++ level, the base potential of Q21 becomes L T level. ” is corrected. (9) "Setting signal" on page 11, line 1 of the specification,
[, and output signal setting signal]. (10) Delete 1 in lines 6 and 7 of page 13 of the specification where 1 emitter is connected to the ground level side. (11) "One side is turned on and the other side is turned on." on page 13, line 8 of the specification is changed to ``One side is turned on and the other side is turned off.'' Correct to 1. (12) Figure 3 of the drawings will be corrected as shown in the attached sheet. that's all

Claims (1)

[Claims] (1) A master-slave type flip-flop circuit having an output signal setting function of at least one of a reset function and a set function, which constitutes an ECL, and has a reference signal obtained from the outside for each base and a reference signal obtained from an internal data line. the first to third transistors to which a signal obtained from the outside and an output signal setting signal obtained from the outside are respectively applied, and a differential pair is formed between the first transistor and the second and third transistors. a master flip-flop, and fourth to sixth transistors constituting an ECL, to which the reference signal, the signal obtained from the data line, and the output signal setting signal are applied, respectively, to each base, and
and a slave flip-flop forming a differential pair between the fifth and sixth transistors; A flip-flop circuit characterized in that the "H" and "L" levels of the reference signal are set to the same potential, and the voltage of the reference signal is fixed to an intermediate potential between the "H" and "L" levels.