GB2245793A - Controlling or deriving direct current level of video signals - Google Patents

Abstract

A video signal is applied via a storage capacitor C to a comparator comprising long tailed pair of transistors T1, T2. A comparison is made with a black level reference VR and as a result transistors T1, T2 are switched to cause current mirrors IM1, IM2, IM3 to be operative or not for supplying current to or from the storage capacitor C. In the balanced condition when the current mirrors IM1, IM2 supply substantially zero current, current for the collectors of transistors T1, T2 are supplied by further current mirrors IM4, IM5. <IMAGE>

Description

DESCRIPTION CONTROLLING OR DERIVING DIRECT CURRENT LEVELS The present invention relates to a circuit arrangement for controlling a direct current level in a composite alternating signal or deriving a direct current level therefrom, said arrangement comprising a comparator, in the form of a first and a second transistor connected as a long tailed pair, which compares the instantaneous level of the composite signal with a further level and switches into operation either a first or a second current supply means for providing a charge/discharge of a storage means to produce said direct current level, A circuit arrangement of the above type is disclosed in European Patent Specification No. 0064316 B1.A problem can exist at balance with certain configurations of the above arrangement whereby the currents in the collector circuits of the two transistors cannot be made equal to each other.

It is an object of the invention to provide a circuit arrangement of the type described in the opening paragraph in that the above problem can be overcome.

The present invention provides a circuit arrangement for controlling a direct current level in a composite alternating signal or deriving a direct current level therefrom, said arrangement comprising a comparator, in the form of a first and a second transistor connected as a long tailed pair, which compares the instantaneous level of the composite signal with a further level and switches into operation either a first or a second current supply means for providing a charge/discharge of a storage means to produce said direct current level, characterised in that said first and second current supply means, in addition, respectively supply current for said first and said second transistors at times other than when said circuit arrangement is in a balanced condition in which condition current for said first and said second transistors are respectively supplied by a third and a fourth current supply means.

The above arrangement has the advantage that by supplying the currents in the balanced condition for the collectors of the first and second transistors from the third and fourth current supply means, the currents of the fist and second current supply means may be reduced to zero or substantially zero and the direct current level will not vary from its required level.

The invention may further be characterised in that said first current supply means may comprise a first and a second current mirror each having an input current path and an output current path, the input current path of said first current mirror being connected to the collector of the first transistor whilst its output current path is connected to the input current path of the second current mirror whose output current path is connected to said storage means, said second current supply means comprising a third current source whose input current path is connected to the collector of said second transistor whilst its output current path is connected to said storage means.

An additional characteristic of the invention may be that said third and fourth current supply means may respectively comprises a fourth and a fifth current mirror whose output current paths are respectively connected to the collectors of said first and second transistors whilst their input current paths are connected to a current source providing current of the same magnitude as a further current source in the commoned emitter circuit of said first and second transistors. The output current paths of said first, third, fourth and fifth current mirrors may then all be able to convey a maximum current of substantially the same magnitude. In such a situation the output current path of said second current mirror may be able to convey a maximum current that is one fifth of the maximum current that can be conveyed in the corresponding path of the remaining current mirror.

The above and other features of the invention will now be described, by way of example, in relation to the accompanying drawings, in which, Figure 1 is a diagram of a circuit arrangement according to the invention, and Figure 2 is a more detailed circuit of that shown in Figure 1.

In Figure 1 a video voltage signal source S having a sync.

pulse portion, a black level reference, and a picture content portion which is positive going is applied to an input terminal 1 through a resistor R1 which represents the internal resistance of the source S. The signal at terminal 1 is applied through a storage capacitor C, which removes the d.c. component of the signal, to an output terminal 2 to which a high impedance load R2 is connected.

Capacitor C is also connected to one input of a comparator circuit comprising two transistors T1 and T2 connected as a long tailed pair arrangement with their commoned emitters being connected to a current source IS1. The base of transistor T1 forms the input to which the capacitor C is connected whilst the base of transistor T2 is connected to a voltage reference source VR whose voltage corresponds to the desired black level in the video signal appearing at output terminal 2.The collectors of transistors T1 and T2 are each connected to the input current path II1, II2 of a respective current mirror circuit IM1 and IM2, energised from a supply rail B+, whose respective output current paths I01, I02 are able to convey a maximum current corresponding to its input current. The output current path I01 of current mirror IM1 forms the input current path II3 for a further current mirror circuit IM3 whose output current path I03 is able to convey a maximum current which corresponds to one-fifth of its input current.The output paths I02 and I03 of the current mirrors IM2 and IM3 are each connected to the side of capacitor C remote from terminal 1. During times when the signal voltage at the base of transistor T1 is above that of the reference voltage VR transistor T1 conducts whilst transistor T2 is non-conducting. Current mirror IM1 is then operative to supply current to current mirror IM3 which in turn draws current from the capacitor C. When the signal voltage is below the reference voltage VR transistor T2 conducts whilst transistor T1 is non-conducting. This results in current mirror 1M2 being operative to supply current to the capacitor C.Capacitor C serves as a storage means which balances the applied and discharged currents so as to carry a mean current which corresponds to a mean value which provides the required black level in the signal at output terminal 2.

With the circuit of Figure 1 as so far described in the balanced state the currents I02 and I03 supplied by the current mirrors IM2 and IM3 are equal and equate to zero with no signal input. This results in: i/s 111 = 112.

As (II1 + II2) is equal to the current supplied by current source IS1 the long tailed pair is not in balance producing a differential voltage level (of the order of 300mv) between the bases of transistors T1 and T2 so that the black level in the signal at the output terminal 2 does not correspond to the reference provided by voltage reference source VR. This problem is overcome by the addition of two additional current mirror circuits IM4 and IM5 also energised from supply rail B+.The input current paths II4 and II5 of these two additional current mirror circuits are connected to a second current source IS2 of the same current value as current source IS1. The output current paths I04 and I05 of current mirror circuits IM4 and IM5 are respectively connected to the collectors of transistors T1 and T2. In the balanced condition previously referred to the tail current for current source IS1 is equally supplied from I04 and I05 allowing the input paths II1 and II2 of current mirror circuits IM1 and IM2 to be equal and substantially zero.

Figure 2 is a more detailed circuit of that shown in Figure 1 and corresponding references between the two drawings indicate like components. In Figure 2 signal source S and its internal resistance R1 have been omitted as has the load impedance R2.

Capacitor C is connected to transistor T1 base by way of an emitter follower buffer amplifier transistor T3 whose emitter is connected to a current source IS3, comprising a transistor T4 and an emitter resistor R3, and a low pass filter LPF which removes the colour burst. The emitter of transistor T3 also forms the output of the circuit and is connected to terminal 2. Current source IS1 is formed by a transistor T5 and an emitter resistor R4 whilst current source IS2 is similarly formed by a transistor T6 and an emitter resistor R5.Current mirror circuits IM1, IM2, IM4 and IM5 are each formed by a diode connected transistor, namely T7, T9, T11, T13, and further common emitter transistor, namely T8, T10, T12, T14,.each pair of transistors forming a current mirror circuit being connected in the manner shown. The remaining current mirror circuit IM3 is formed by five diode connected transistors T15, T16, T17, T18, T19 and a common emitter transistor T20, the transistors T15 to T20 being connected in the manner shown.The bases of the current source transistors T4, T5 and T6 are each connected to a further voltage reference source VB which keeps the currents supplied by each current source constant with temperature and supply voltage.

Other connections to earth and to a supply rail B+ are not described in detail as they are self evident from Figure 2.

It will be seen that the transistors T1 to T6 and T15 to T20 are all of the npn type whilst the remaining transistors T7 to T14 are all of the pnp type.

The circuit of Figure 2, with the exception of capacitor C, is suited to be manufactured as an integrated circuit in which case transistors T1 and T2 will be of a first same structure, transistors T3 to T6 and T15 to T20 will be of a second same structure and transistors T7 to T14 will be of a third same structure.

In the above description the circuit arrangement is employed to keep the black level constant in the output present at terminal 2. It may also be used to keep some other level in the video signal constant or indeed used to keep a level constant in some other form of composite alternating signal. If it is desired to keep the sync. tip level constant in a video signal then current mirror circuit IM3 will be arranged such that its output current path I03 will convey a maximum current which is one thirtieth of the current in its input current path II3.

The invention has so far been described in relation to controlling a direct current level of an applied composite alternating signal such as a video signal. It may however be used in circuit arrangements where it is desired to derive a direct current level from such a composite signal and such an arrangement is shown in Figure 3 which is a modification of Figure 1 and where like references between these two figures indicate like components. Only the differences between the two figures will be described.

In Figure 3 the input terminal 1 is connected directly to the base of transistor T1, capacitor C being omitted, so that video signal at that base is not floating but has a relationship to earth. The black level reference source VR is also omitted and the storage capacitor C is connected in its place between the base of transistor T2 and earth, the value of this capacitor being sufficiently large, in the case of a video signal, that it will substantially retain its charge from line to line.The connections of current mirror circuits IM1, IM2 and IM3 are re-arranged compared with those in Figure 1, the output current path I01 of current mirror circuit IM1 now being connected to the junction of capacitor C with transistor T1 base as is the output current path I03 of current mirror circuit IM3 whilst the output current path I02 of current mirror circuit IM2 is connected to the input current path II3 of current mirror circuit IM3.

There is now no need to derive a composite video signal output at terminal 2 and instead an output terminal 3 is connected to the junction of capacitor C with transistor T2 base to which externally there is connected a high impedance load R6 and across which a voltage, corresponding inthis case to the black level, is provided.

The operation of the circuit of Figure 3 is similar to that of Figure 1 with a comparison being made between the input signal at transistor T1 base with the level present at transistor T2 base, resulting in a charge/discharge of current at capacitor C with the switching of current mirror circuits IM1, IM2 and IM3.

In the balanced condition current for the collectors of transistors T1 and T2 are again respectively provided by current mirror circuits IM4 and IM5.

If Figure 3 is used to obtain a black level reference then the current mirror circuits would provide the same maximum currents as the corresponding current mirror circuits in Figures 1 and 2 and if used to obtain a sync. tip reference the current mirror circuit IM3 would provide the same maximum current previously proposed for that condition. As with Figures 1 and 2, the circuit arrangement of Figure 3 may be used not only for composite video signals but for other forms of composite alternating signal.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (6)

CLAIM(S)

1. A circuit arrangement for controlling a direct current level in a composite alternating signal or deriving a direct current level therefrom, said arrangement comprising a comparator, in the form of a first and a second transistor connected as a long tailed pair, which compares the instantaneous level of the composite signal with a further level and switches into operation either a first or a second current supply means for providing a charge/discharge of a storage means to produce said direct current level? characterised in that said first and second current supply means, in addition, respectively supply current for said first and said second transistors at times other than when said circuit arrangement is in a balanced condition in which condition current for said first and said second transistors are respectively supplied by a third and a fourth current supply means.

2. A circuit arrangement as claimed in Claim 1, characterised in that said first current supply means comprises a first and a second current mirror each having an input current path and an output current path, the input current path of said first current mirror being connected to the collector of the first transistor whilst its output current path is connected to the input current path of the second current mirror whose output current path is connected to said storage means, said second current supply means comprising a third current source whose input current path is connected to the collector of said second transistor whilst its output current path is connected to said storage means.

3. A circuit arrangement as claimed in Claim 2, characterised in that said third and fourth current supply means respectively comprises a fourth and a fifth current mirror whose output current paths are respectively connected to the collectors of said first and second transistors whilst their input current paths are connected to a current source providing current of the same magnitude as a further current source in the commoned emitter circuit of said first and second transistors.

4. A circuit arrangement as claimed in Claim 3, characterised in that the output current paths of said first, third, fourth and fifth current mirrors are all able to convey a maximum current of substantially the same magnitude.

5. A circuit arrangement as claimed in Claim 4, characterised in that the output current path of said second current mirror is able to convey a maximum current that is one fifth of the maximum current that can be conveyed in the corresponding path of the remaining current mirror.

6. A circuit arrangement substantially as herein described with reference to Figure 1 or Figure 2 of the accompanying drawings.