JPH02134621A - Thin-film transistor matrix - Google Patents

Abstract

PURPOSE:To eliminate defects, such as disconnections, by forming a gate electrode of a metallic material having hydrofluoric acid resistance and interposing an etching preventive film consisting of the same material as that of the gate electrode between a transparent insulating substrate in the lower layer of a drain pass line and a gate insulating film. CONSTITUTION:The gate electrode G is formed of a film consisting of a material which is not attacked by hydrofluoric acid and the etching preventive film 50 consisting of the same material as the material of the gate electrode G is interposed between the transparent insulating substrate 1 in the lower layer of the drain balance forming region and the gate insulating film 2. Even if, therefore, there is a pinhole on the etching preventive film 50, the etching by the etching liquid arising from the penetration of the hydrofluoric acid liquid through the pinhole is stopped by the etching preventive film 50 and the erosion of the transparent insulating substrate 1, such as glass substrate, does not arise. The generation of the disconnection in the drain bus line DB is, therefore, prevented.

Description

[Detailed Description of the Invention] [Previous Remarks] The purpose of this invention is to prevent defects such as disconnection even if there are pinholes or cracks in the gate insulating film or the active semiconductor layer with respect to the thin film transistor matrix. Inverted staggered thin film transistors each consisting of a laminate of a gate electrode, an active semiconductor layer, and source and drain electrodes are arranged in a matrix on the substrate. , and in a configuration in which a plurality of drain bus lines are formed in a layer above the gate insulating film in correspondence with the columns of the matrix, the gate electrode is formed of a metal material having hydrofluoric acid resistance. Additionally, an etching prevention film made of the same material as the gate electrode is interposed between the transparent insulating substrate and the gate insulating slit below the drain bus line.

[Industrial application field]

The present invention is a thin film transistor (TFT) 7 used for pixel driving of liquid crystal displays, electroluminescence, etc.
Regarding the trix.

In a thin film transistor matrix, each part of the drain lot line, gate lot line, and TPT must have high reliability.

The reason for this is that, for example, if a disconnection occurs in the drain bus line, normal voltage cannot be applied to all TPTs connected to it, resulting in a serious line defect.

[Conventional technology]

Conventional 1. IJ Amorphous silicon (
Figure 3 (a) to (k), (a'l to [l/l
and shown in FIG. Note that [a') to (l/1 in the same figure is (
It is a figure which shows the AA arrow cross section of a)-(k).

[See Figure 3(a), (a)] A gate electrode G made of a Ti film and a gate lotus line CB connected thereto are formed on the glass substrate 1. Both are integrated into one pattern. Therefore, hereinafter, the gate electrode G and gate pass line GB will be abbreviated as a gate pattern.

(See Figures 3(b) and (5)) Next, on this upper layer, a SiN film 2 is used as a gate insulating film, 3 is an a-3i layer as an active semiconductor layer, and 5i is a protective insulating film.
n2 membrane 4. An a-3i layer 5 is continuously formed as an adhesion layer by plasma vapor phase chemical deposition (P-CVD).

[See Figure 3 (C), [C'l] A photoresist is applied to this upper part, and ultraviolet rays are irradiated onto this from the back side of the glass substrate 1, and then the hatched part in (C) is removed by a mask exposure method. By exposing the area,
A resist film 6 that is self-aligned to the gate pattern is formed.

[See FIG. 3(d), Ull. Using the resist film 6 as a mask, the aSiSbO2 exposed portion was etched using a reactive ion etching (RIE) method, and then the exposed portion of the SiO□ film 4 was etched using a hydrofluoric acid-based etching solution. Remove by etching.

[See FIGS. 3(e) and 3(pi)] Next, while leaving the resist film 6, an n''a-3i layer 7 is formed by the P-CVD method, and a Ti film 8 is vacuum-deposited thereon. The film is formed using the method.

[See FIGS. 3(f), ff")] By removing the resist film 6 with acetone, the n.a-3i layer 7 and the Ti film 8 deposited thereon are lifted off.

[See FIG. 3 ((a), +g')] Next, a resist film 9 for the element Eft is formed.

[See FIG. 3(h), (translation)] By plasma etching using this resist film 9 as a mask, the Ti film 8. n″a-3t layer 7, a-3i
After removing the exposed portion of layer 3 and separating each element, resist film 9 is removed. With the above steps, the source electrode S and the drain electrode are formed.

[See FIG. 3(i), fl.] Next, a polyimide film 10 is formed as an interlayer insulating film on the gate lot line CB.

[See FIG. 3(j), g)] Next, a drain bus line DB is formed from a laminated film of Cr film 1/Aff film 2.

[Fig. 3(k), (see bulletin board)] Next, after forming a resist film (not shown) having an opening in the area where the pixel electrode is to be formed, an ITO film is formed, and the ITO film is deposited on top of the above resist film. The ITO film adhering to the substrate is removed to form the pixel electrode E. This completes the basic steps for manufacturing the TPT matrix.

[Problems to be Solved by the Invention] In the conventional TPT matrix structure, as shown in FIG. 4, an active semiconductor layer (a-3i layer 3) and a gate layer 8 (film ( SiNllQ2)
If there are defects such as pinholes or cracks in the glass substrate 1, the glass substrate 1 is etched by the hydrofluoric acid etching solution that has seeped through the pinholes 21 and cracks in the step shown in FIG. 3(d). Therefore, the bottom of the gate insulating film 2 is undercut and the gate insulating film etc. is lifted, and as a result, the SiN film (gate insulating film) 2 may peel off during the manufacturing process, or a step may occur, causing disconnection. resulting in defects that may cause

If this defect occurs below the drain bus line DB, it is particularly serious because it will cause a disconnection of the drain bus line DB.

An object of the present invention is to prevent defects such as disconnection of drain bus lines from occurring even if there are pinholes or cracks in the gate insulating film or the active semiconductor layer.

[Means to solve the problem]

The present invention is as shown in FIG.
An etching prevention film 50 made of the same material as the gate electrode G is interposed between the gate electrode G and the gate electrode G.

[For production]

With the above configuration, as seen in Figure 1,
Even if there is a pinhole on the etching prevention film 50, the etching by the etching solution into which hydrofluoric acid has penetrated will stop at the etching prevention film 50 and will not attack the transparent insulating substrate 1 such as a glass substrate. There isn't. Therefore,
By providing the etching prevention film 50 in the drain bus line formation region, disconnection of the drain bus line DB can be prevented from occurring.

Note that the etching prevention film 50 can be formed by only partially changing the pattern of the photomask used when forming the gate pattern, and since the same material as the gate electrode G is used, The obtained membrane can be used as is.

Therefore, there is no need to make any changes to the manufacturing process and operations in implementing the present invention.

Furthermore, by using the same material as the gate electrode G for the etching prevention film 50, there is an advantage that there is no risk of adversely affecting the characteristics of the thin film transistor.

〔Example〕

Hereinafter, one embodiment of the present invention, together with its manufacturing process, will be explained.
This will be explained with reference to figures (a) to (k). Note that, as in the case of Fig. 3 above, (a) ((a) in Fig. 2 is (a) ~ (
It is a figure which shows the BB arrow cross section of k).

[See Figure 2(a), (a'l)] First, hydrofluoric acid (H
F) Membrane 2 made of material that is not attacked by Ni (for example, Ni) 80
% and 20% Cr (chromium) is formed, and this is patterned using a mask exposure method to form the gate electrode G.
, a gate pass line CB, and an anti-etching film (hereinafter simply referred to as a preventive film) 50.

As the material that is not attacked by hydrofluoric acid, St (silicon) alloy 9M0 (molybdenum), W (tungsten), etc. can also be used.

The preventive film 50 is provided in a region where a drain bus line is provided. Moreover, patterning of the prevention film 50 only requires changing a part of the pattern of the photomask for forming the gate pattern, and there is no need to change the operation at all.

[See Figure 2 (b) and (5)] There is no need to change the subsequent steps from the conventional ones.

That is, the SiN film 2. is used as the gate insulating film. m) A-3i layer as J-made semiconductor layer 3. SiO□ film 4 as a protective insulating film
．． An a-3i layer 5 is continuously formed as an adhesion layer by the P-CVD method.

(See Figure 2 (C), (C'l)) Next, a photoresist is coated on the upper layer and exposed from the back side of the glass substrate 1, and then a mask exposure method is applied to the area excluding the hatched part in Figure 2 (C). UV rays are irradiated to form a resist film 6 that is self-aligned to the gate pattern.The photomask used for mask exposure in this step has the same pattern as the conventional one.

[See FIG. 2(d), 1] Using the resist film 6 as a mask, the a-3i layer 5 is exposed by the reactive ion etching method, and the SiO□ film 4 is exposed using a hydrofluoric acid-based etching solution. remove part.

Even if pinholes 50 as shown in FIG. 1 are present on the preventive film 50, the preventive film 50 is not attacked by the hydrofluoric acid-based etching solution that has soaked through the pinholes 50, so that undesirable etching can be avoided here. When the process stops, the underlying glass substrate 1 will not be damaged, and therefore, the drain bus line DB, which will be formed in a subsequent process, will not be disconnected.

[See Figures 2(e) and (e'l)] Next, with the resist film 6 left, an n''a-3i layer 7 is formed by the P-CVD method, and a Ti film is formed on top of it in a vacuum. The film is formed using a vapor deposition method.

[FIG. 2(f), (see f)] By removing the resist film 6 with acetone,
The n'a-3i layer 7 and the Ti film deposited thereon are lifted off.

[See Figure 2 ((to), (α))] Next, a resist film 9 for element isolation is formed.

[Mount in Figure 2], (l (see l) Using this resist film 9 as a mask, the exposed portions of the Ti film, the n''a-3i layer 7, and the a-3i layer 3 are removed by plasma etching. After separating each element, the resist film 9 is removed.The source electrode S and the drain electrode are thus formed.

[See FIGS. 2(i) and (i') 3 Next, a polyimide film 10 is formed as an interlayer insulating film on the gate pass line GB.

[See FIG. 3(j), ridge)] Next, a drain bus line DB consisting of a laminated film of Cr film 1/AI film 12 is formed.

[See Figure 3 (tentative), (k')] Next, after forming a resist film (not shown) with an opening in the area where the pixel electrode is to be formed, an ITO film is formed, and the ITO film is coated with the resist film. The ITO film attached thereon is removed to form a pixel electrode E. This completes the basic steps of this embodiment.

FIG. 2(d) shows the manufacturing process of this embodiment as described above.

In the UL process, even if there are pinholes or cracks in the gate insulating film 2 or the active semiconductor layer 3, undesirable etching can be prevented by the etching prevention film 50 provided in this embodiment.
The glass substrate 1 is not damaged. Therefore, in this embodiment, the occurrence of disconnection of the drain lot line D13 is effectively prevented.

Moreover, as is clear from the above description, in order to realize the configuration of this embodiment, it is necessary to simply change the pattern of the photomask used to form the gate pattern in the steps of FIGS. There is no need to change the manufacturing process or operation in any way from the conventional one.Therefore, there is no problem in implementing the present invention.

Furthermore, the drain bus line DB and the anti-etching film 50
If you connect them by a method such as laser beam irradiation,
It is also possible to lower the resistance of the drain bus line DB,
Furthermore, if the drain bus line DB is disconnected on the etching prevention film 50 for some reason, the drain bus line DB and the etching prevention film 5 are disconnected on both sides of the disconnection point.
By connecting the etching prevention film 50 to the drain lot line DB, disconnection relief is also possible.
It can also be used as a redundant configuration means. The etching prevention film can also be used as a means for lowering the resistance of the drain bus line.

(Effects of the Invention) As explained above, according to the present invention, it is possible to easily obtain a highly reliable panel that does not cause disconnection defects in the pass line, improve manufacturing yield, and reduce manufacturing costs. There is.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 (a) to Fig. 2 are explanatory diagrams of an embodiment of the present invention, and Fig. 3 (a)
) ~ ((a) is a diagram explaining the conventional problem, Figure 4 is the conventional T
It is a structural explanatory diagram of PT. In the figure, 1 is a transparent insulating substrate (glass substrate), 2 is a gate insulating film (SiN film), and 3 is an active semiconductor layer (a-3
i layer), 4 is a protective insulating film (Sin film), 5 is an adhesion layer (a-3i film), 6 and 9 are resist films, 7 is a contact layer (n" a-3i layer), 8 is a metal film (Ti film), 10 is a polyimide film, 11 is a Cr film,
12 is an Affi film, G is a gate electrode, S is a source electrode,
D is a drain electrode, CB is a gate pass line, and DB is a drain bus line. +Hatsurou -da ('P1 噸といく・J名ξMAR明をん】Figure 2 ("i/II)・J Explanation Diagram Diagram 2 (Su/+2) Honkicho - Tsukuban Example Dimeim Diagram 2 (Uno 3) e1 B (e'n (f') Subordinate rli1R Notes - Diagram No. Diagram (t02) 8th jump 〃musical drum H must be shown in Figure 3 (preliminary)) Figure 3 ('(t+3n))

Claims (1)

[Claims] Lamination of a gate electrode (G), a gate insulating film (2), an active semiconductor layer (3), and source and drain electrodes (S, D) on a transparent insulating substrate (1). Inverted staggered thin film transistors are arranged in a matrix, and a plurality of drain bus lines (DB) are arranged in a layer above the gate insulating film (2) corresponding to the columns of the matrix. In the formed configuration, the gate electrode (G) is formed of a metal material having hydrofluoric acid resistance, and the transparent insulating substrate (1) and the gate insulating film (2) below the drain bus line (DB) are formed. A thin film transistor matrix characterized in that an etching prevention film (50) made of the same material as the gate electrode is interposed therebetween.