JPH02132699A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the delay of an access time and the generation of a malfunction even when a power source potential drop is caused during an operation by providing a potential detection circuit to detect the potential of a data line and to control the conducting state of a data line load circuit. CONSTITUTION:A potential detection circuit 1 detects the potential of data lines DB and the inverse of DB to which a sense amplifier 5 is connected. When the potential of the data lines DB and the inverse of DB are slipped off out of a potential range set in a potential detection circuit 1, a data line load circuit 2 connected to the slipped potential side and inverse potential side is conducted, and an operation to put the potential of the data lines DB and the inverse of DB within a prescribed potential range is executed. Thus, even when the fluctuation of the power source voltage is generated during the operation, the data lines DB and the inverse of DB are no longer slipped off from the amplificable input potential range of the sense amplifier 5 and the delay of the access time and the output of the error data can be prevented.

Description

[Detailed description of the invention]

[Industrial Application Field 1] The present invention relates to a semiconductor device, and particularly to a data line portion that is an input to a sense amplifier.

[Conventional technology]

A conventional semiconductor device of this type is shown in FIG. Figure 7 shows a circuit from memory cells to sense amplifiers used in random access memory. In FIG. 7, 3 is a memory cell, and the memory cell selected by the word line WL at the time of reading is connected to the bit line BL-BL.
Send data to L. Column selection gates 41 and 42 transfer data on a bit line selected by a column selection signal CT to data lines DB-DB. Here, the seventh
In the figure, only one pair of bit lines is connected to the data line DB-DB, but two or more pairs may be connected. 5 is a sense amplifier, to which the data line DB-DB is input, and the D
Amplify the minute potential difference between B-DB. 2 is a data line load circuit, which includes Nchh transistors 27 and 29 whose source electrode is connected to the data line DB-DB, and whose gate and drain electrodes are connected to the power supply line, respectively; It is composed of Nch transistors 28 and 210 whose electrodes are connected to the ground line and whose gate electrodes are connected to the signal φA. The data line load circuit 2' is connected to the data line DB- which is the input of the sense amplifier 5.
It is used for the purpose of setting the potential of DB within the amplifiable input range of the sense amplifier 5, and when the signal φA becomes High, N
Ch transistors 28 and 210 are conductive, and the data line DB
- DB becomes an intermediate potential determined by the size ratio of the Nch transistors 27 and 29 and the Nch transistors 28 and 210 that constitute the data line load circuit 2'. usually,
This intermediate potential is set so as to be the input potential at which the sense amplifier 5 has the highest amplification degree. Here, when the signal φA becomes High, the Nch transistors 27, 29 and .
Nch}-A direct current flows through the grounding wire through the transistors 28 and 210. Therefore, a block signal for selecting the memory cell array corresponding to the address input from among the plurality of memory cell arrays is used as the signal φA, and 9 indicates that the potential of the data line DB-DB is connected to the Nch from the power supply line. When the threshold voltage Vth of the transistor 27.29 plus the back gate effect voltage VIO rises above the pull potential, it will no longer conduct, so even when the signal φA is Low, the data line DB-DB is at a potential lower than the power supply potential by the above Vth+Vsa. This ensures that the input range that can be amplified by sense amplifier 5 is not exceeded. In the conventional semiconductor device configured as described above, the power supply potential V1 is as shown in FIG. 0 starts to fall from time tl' and reaches V2 at time t2', then at time t3'
The operation of the device when the address input changes is as follows. Before time tl', the signal φA is Low, and the data line D
As mentioned above, B-DB is at a potential that is lower than the power supply potential ■1 by Vth+Vao of the Nch transistors 27 and 29. N source potential V from time tl' to t2'. . falls and becomes ■2, but at this time, none of the transistors that make up the data line load circuit conduct, and the data #IDB
-DB holds the potential after time tl', regardless of the amount of drop in the power supply potential. After that, the address input changes and time t3
Assuming that memory cell 3, column selection gates 41 and 42, and sense amplifier 5 are selected by the address after '',
At time t4', φA goes High, at time t5' the word line WL and column selection signal CT go High, and at time t
At 6', the sense amplifier control signal φSA becomes }Ihigh, and the sense amplifier 5 amplifies the data of the memory cell 3 output to the data lines DB and DB. Data line DB-D
B is V0 as described above until φA becomes High at time t4'. It is at a potential of 1 (V th + Vsa),
The amount of drop in power supply potential V1-V2 is Vth + V+
If it is larger than +a, the power supply potential V2 after time t2'
It has a higher potential. φA7 at time t4'! l5
When it becomes High, the Nch transistors 28 and 210 become conductive, and the potential of the data line DB-DB begins to drop. After that, at time t5', WL. CT becomes High, but
NCh transistors 41 and 42 which are column selection gates
The data line DB − DB which is the source potential of each of
The potential difference between and CT is the threshold voltage v of the Nch transistor
The column selection gates 4l and 42 do not become conductive unless the voltage exceeds the sum of th' and the back gate effect voltage V sa', that is, after time t7', and the data in the memory cell 3 is transferred to the data line DB - after time t7'. Output to DB. On the other hand, the sense amplifier control signal φSA goes High at time t6'.
h, and the sense amplifier 5 starts amplifying operation, but the data of the memory cell 3 is not output to the data line DB-DB until time t7', and the potential is high, so the input range in which the sense amplifier can amplify is exceeded. Sense Ambu 5 is now in a very unstable state. [Problem to be Solved by the Invention 1] Since the conventional semiconductor device as described above is configured as described above, when a drop in the power supply potential occurs during operation, the data line that is the input of the sense amplifier is The output of memory cell data is delayed, and the high potential of the data line is outside the sense amplifier's amplifiable input range, making the sense amplifier more likely to malfunction, causing delays in access time and errors. There was a problem with the data being output. Also, as shown in FIG. 8 after time t8', the memory cell data output to the data line DB-DB is determined,
Even after the data is output to the outside, the signal φA remains High.
h, there was a problem in that a DC current was flowing through the data line load circuit. The present invention has been made to solve these problems, and provides a semiconductor device that does not cause access time delays or malfunctions even when the power supply potential drops during operation, and can achieve low current consumption. The purpose is to obtain. [Means for Solving the Problems] A semiconductor device according to the present invention includes at least a data line through which read data is output, and a sense amplifier connected to the data line and amplifying a minute amplitude signal of the data line. In the apparatus, a data line load circuit comprising a circuit connected from the data line to a power line, a circuit connected from the data line to a ground line, and at least an input to the data line and an output to the data line load circuit. The semiconductor device is characterized in that it has a potential detection circuit that is connected to the data line, detects the potential of the data line, and controls the conduction state of the data line load circuit. [Function 1] According to the above configuration of the present invention, when the data line that is the input of the sense amplifier is on the higher potential side than the potential range set in the potential detection circuit, the circuit constituting the data line load circuit The circuit connected to the ground line becomes conductive, lowering the potential of the data line. Thereafter, when the data line enters the potential range set in the potential detection circuit, the circuit connected to the ground line becomes non-conductive. At this time, the circuit connected to the power supply line among the circuits forming the data line load circuit is in a non-conductive state. Conversely, if the data line is at a lower potential than the potential range set in the potential detection circuit, the circuit connected to the power supply line in the data line load circuit becomes conductive, and the data line potential is kept within the predetermined potential range. . [Embodiment] FIG. 1 is a diagram showing an embodiment of the present invention, in which a memory cell 3, a column selection gate 1-41, 42, a sense amplifier 5
is exactly the same as the conventional device described above. 1 is a potential detection circuit, and an inverter 11 receives the data line DB as an input.
．． 13, inverters 12 and 14, inverters 15 and 17 whose input is the data line DB, and inverters 16 and 1.
Consists of 8. 2 is a data line load circuit, which includes Pch transistors 2l and 23 whose source electrodes are connected to the power supply line, whose drain electrodes are connected to the data lines DB and DB, and whose gate electrodes are connected to the outputs of inverters 12 and 16, respectively; The ground line is connected to the drain electrode, and the drain electrode is connected to the data line DB-DB.
It consists of Nch transistors 22 and 24 whose gate electrodes are connected to the outputs of inverters 14 and 18, respectively.
Here, the logic level of the inverters 11 and 15 of the potential detection circuit 1 is set to V L O l +inverter l3,? 7
Let the logic level of +VLaV be VL62. 2 and power supply potential V. . , the relationship between the ground potential V and the ground potential V is shown in Figure 2.
Set ss < V LQI < V Lax < V no. The VLa+. VL6g can be set arbitrarily by adjusting the transistor size and threshold voltage of the Pch transistor and Nch transistor that constitute each inverter. In Figure 2, data 4! When the potential of DB-DB is in range A from Voo to VLO2, inverters l1, 15 and 13.
17 recognizes the data line DB-DB as 1{right,
Outputs N1, N5 and N3, N7 of each inverter are low
Therefore, the outputs N2, N6, N4, and N8 of each inverter of inverters l2, l6, l4, and l8 become High6.
The potential of the data line DB-DB changes from V L6■ to V L
If in range B up to QI, inverter 11.15
recognizes the data line DB-DB as High, and the Nl. N5
becomes Low, and the outputs N2 and N6 of inverters l2 and l6 become High. Meanwhile, at this time, inverter 13-. 17
recognizes data line DB-DB as Low, and N3. N
7 is High, and the outputs N4 and N of inverters 14 and l8
8 becomes Low. Also, the potential of the data line DB-DB is ■,. , to Vis, the inverters 11, 15 and 13, l7 are connected to the data line DB -
DB is recognized as Low, and the output Nl. N
5 and N3. N7 becomes Hfgh, and inverter 12.
16, l4, l8 inverter output N2. N6. N
4. N8 becomes Low. In the semiconductor device of the present invention configured as described above,
As shown in FIG. 3, the power supply potential V0 was at the potential v1. The operation of the device when the address input changes at time t5 after V2 starts to fall from time tl and reaches V2 at time t2 is as follows. Before time tl, data line DB-D
B is in the range B from VLO2 to Vta+ shown in Figure 2, and at this time, as mentioned above, the outputs N2 and N6 of the invert 12.16 become High, and the outputs N4 and N8 of the inverters 14 and 18 become Low. Therefore, the Nch transistors 2l and 23 and the Pch transistors 22 and 24 of the data line load circuit are in a non-conductive state. Power supply potential V0 from time tl to time t2. falls from Vl to v2, the data line DB-DB in range B becomes the power supply potential V. 0, and at time t2, it crosses the logic level VL62 of the inverter 13.17 of the potential detection circuit 1 and moves further to the higher potential side. After time t2, the data line DB-DB has a higher potential than the logic V Lax of the inverters l3 and 17, so the outputs N3 and N7 of the inverters l3 and l7 are High.
to Low, and with this change, inverter l4,
l8 output N4. N8 changes from Low to High. At time t3, the gate-source potential of the Nchh transistors 22 and 24 of the data load circuit 2 becomes higher than the threshold voltage of the Nchh transistors 22 and 24;
The Nchh transistors 22 and 24 become conductive, and the potential of the data line DB-DB begins to drop. Thereafter, at time t6, the dropped potential of the data line DB-DB crosses the logic level VL(12) of the inverter 13 and 17 of the potential detection circuit l and moves to the low potential side.
Outputs N3 and N7 of inverters l3 and l7 that matched the level
changes to High level, and with this change, the outputs N4 and N8 of inverter 14.18 change from High to Low. Due to this change of N4 and N8 to Low, at time t7, the Nch} transistors 22 and 24, which had been in a conductive state until then, become non-conductive, and the data line DB-D
The potential drop at B stops. Data line DB − at this time
The potential of DB is within the potential range B shown in Figure 2, and the potential of PC
Since the h transistors 2l and 23 are also in a non-conductive state, the data line DB-DB retains the potential at time t7. Then, due to the change in the address input at time t5, the word line WL and column selection signal CT rise at time t8, but the potential of the data lines DB and DB is lower than the logic level V Lat of inverters l3 and l7 of the potential detection circuit 1. Therefore, the relationship between the sum of the threshold voltage vth' of the Nch transistors 41 and 42 which are column selection gates and the back gate effect voltage V@a' and the above-mentioned VLaz is V. . −
By setting V1.62≧Vth'+VB+1', the column selection signal CT is set to V. . become the level. That is, immediately after time t8, the column selection gates 4l, 42
becomes conductive, and the data of the memory cell 3 outputted to the input line BL-BL is outputted to the data line DB-DB via the column selection gate. After that, at time t9, the sense amplifier control signal φSA rises, and the sense amplifier 5
starts the amplification operation, but at this time the data line DB -
The potential of DB is within the range that can be amplified by the sense amplifier 5,
Also, since the data in memory cell 3 is fully represented,
To perform an amplification operation without delay or malfunction. After that, the data of the memory cell is output and the data line DB -
Even after time t10 when DB stabilizes at a constant potential difference, DB
- DB is in the potential range B shown in Figure 2, and Pch
Transistors 2l, 23 and Nch transistor 22
, 24 are in a non-conductive state, so no current flows through the data line load circuit 2. FIG. 4 is a diagram showing another embodiment of the present invention, in which a gate receiving data kM D B in the potential detection circuit 1 is composed of a NOR circuit 19 and a NAND circuit 110, each of which controls the This embodiment differs from the embodiment shown in FIG. 1 in that it is controlled by signals φ and φ. Here, the logic level of the NOR circuit 19 is set to VLot, and the logic level of the NAND circuit 110 is set to VLG2, so as to satisfy the voltage relationship shown in FIG. 2. In FIG. 4, the control signal φ goes low,
When φ is High, the NOR circuit 19 is connected to the inverter 1l of the embodiment in FIG. 1, and the NAND circuit 110 is connected to the inverter 13.
Therefore, even if a drop in the power supply potential occurs during operation, the operation is similar to that of the embodiment f5+1 in FIG. 1 described above. On the other hand, when the control signal φ is High and φ is Low, the operation of the potential detection circuit 1 is prohibited, and the gate potential of the Pch transistor of the data line load circuit is High.
In addition, since the gate potential of the Nch transistor 22 is fixed to Low, each transistor is connected to the data line DB.
It becomes non-conductive regardless of the potential. That is, the embodiment shown in FIG. 4 allows the operation of the potential detection circuit of the embodiment shown in FIG. 1 to be controlled by control signals φ and φ. The embodiment shown in FIG. 4 uses an internal write control signal for the control signals φ and φ when using a configuration in which a write gate for writing data to a memory cell is connected to the data line DB. This is designed to prevent a through current from flowing between the data line load circuit and the write gate during a write operation. FIG. 5 is a diagram showing another embodiment of the present invention, in which the Pch transistor 2 in the data line load circuit 2 of the embodiment of FIG.
1 to Nchh transistor 25, Nch transistor 2
2 is replaced with a Pch transistor 26,
Accordingly, the potential detection circuit is composed of inverters l1l and 112 that receive data 4i D B. By setting the logic levels of the inverters 111 and 112 to VLot ) VLO2 shown in FIG. 2, the same operation as in the embodiment of FIG. 1 becomes possible. Further, FIG. 6 is a diagram showing another embodiment of the present invention,
The embodiment of FIG. 5 can be controlled by control signals ψ and φ, and operates in the same way as the embodiment of FIG. 4. In the embodiment of the present invention, an Nch transistor or a Pch transistor is used in the circuit connected between the data line and the power supply line in the data line load circuit, and the circuit connected between the data line and the ground line.
Although the explanation has been made using a single transistor, a combination of a resistor and a transistor may be used, or a series connection circuit of transistors may be used. Furthermore, in the embodiments of the present invention, the data line DB - DB has been described using a signal line from the column selection gate to the sense amplifier input, but the data line DB - DB is not necessarily connected to the data line DB - DB.
There is no need for the column selection gate to be connected to the DB.
The present invention may be applied to input signal lines of sense amplifiers, such as input signal lines of second and subsequent sense amplifiers in a cascade-connected sense amplifier configuration of two or more stages. [Effects of the Invention] As described above, according to the present invention, the potential detection circuit detects the potential of the data line to which the sense amplifier is connected, and when the potential of the data line is outside the potential range set in the potential detection circuit. When the potential is shifted to the opposite potential, the data line load circuit connected to the shifted potential side and the opposite potential side becomes conductive and operates to keep the potential of the data line within a predetermined potential range, so fluctuations in the power supply voltage are prevented during operation. Even if this occurs, the data line will not go out of the amplifiable input potential range of the sense amplifier, and it is possible to prevent delays in access time and output of erroneous data due to delay or malfunction of the sense amplifier. Furthermore, when the data line is within a predetermined potential range set in the potential detection circuit, no direct current flows through the data line load circuit, so low current consumption can be achieved. Furthermore, since the specified potential range mentioned in @ can be set arbitrarily by changing the circuit constants or threshold voltages of the circuits that constitute the potential detection circuit, it is possible to design according to the circuit system and circuit characteristics of the sense amplifier circuit. ．．

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor device showing an embodiment of the present invention;
FIG. 2 is a potential diagram for explaining the operating potential of the potential detection circuit 1, FIG. 3 is a timing diagram showing operating waveforms of the semiconductor device of the present invention, and FIGS. 4, 5, and 6 are diagrams of the present invention. FIG. 2 is a circuit diagram of a semiconductor device showing another embodiment of the present invention. Figure 7 is a circuit diagram showing a conventional semiconductor device, and Figure 8 is a circuit diagram showing a conventional semiconductor device.
FIG. 2 is a timing diagram showing operating waveforms of the conventional semiconductor device shown in FIG. Note that the same reference numerals in the figures indicate the same or equivalent parts. 1 ・ ・ ・ ・ ・ 2 ・ ・ ・ ・ ・ 3 ・ ・ ・ ・ ・ 41. 42 ・ ・ 5 ・ ・ ・ ・ ・ Potential detection circuit Data line load circuit Memory cell column selection gate Sense amplifier or higher

Claims (1)

[Claims] (1) In a semiconductor device having at least a data line through which read data is output, and a sense amplifier connected to the data line and amplifying a minute amplitude signal of the data line, the semiconductor device is connected between the data line and a power supply line. a data line load circuit including a circuit connected between the data line and a ground line; and a data line load circuit having at least an input connected to the data line and an output connected to the data line load circuit, and detecting the potential of the data line. , and a potential detection circuit that controls the conduction state of the data line load circuit.