JPH02132323A - Signal processing circuit for minimum value detection - Google Patents

Abstract

PURPOSE:To easily perform a signal processing for minimum value detection by providing a circuit which substrates a reference signal from a detection signal and then inverts its sign in front of a maximum value detecting and holding circuit for a DC signal and a circuit which subtracts the reference signal from a maximum value and then inverts its sign behind the detecting and holding circuit. CONSTITUTION:The detection signal Vin is inputted to the subtracting and inverting circuit 2, the reference voltage Vref is subtracted, and the sign is inverted. Its output signal is detected and held by a peak holding circuit 3. The maximum value S1max of the held S1 when the Vin is a minimum value (Vin)min is -((Vin)min-Vref). Therefore, the output signal Vout =-(-((Vin)min-Vref)-Vref)=(Vin)min of the 2nd subtracting and inverting circuit is detected. In this constitution, the peak holding circuit for maximum value detection for the DC signal is diverted to easily obtain a signal processing circuit for minimum value detection.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing circuit used for measurement, control, etc., and in particular, the present invention relates to a signal processing circuit used for measurement, control, etc. The present invention relates to a minimum value detection signal processing circuit that detects a minimum value.

[Conventional technology]

FIG. 10 shows a conventional minimum value detection circuit.

The minimum value detection circuit 200 forms a voltage follower by first and second differential amplifiers 201 and 202 with a gain of 1.
A diode D1 is connected in series with the output terminal of the differential amplifier 201 in the opposite direction, and one side of the diode D1 is connected to the non-inverting input terminal of the second differential amplifier 202.

Further, a hold capacitor Cl and a reset switch RS are connected to the non-inverting input terminal of the second differential amplifier 202. The other end of the reset switch RS is connected to the positive side of the power supply circuit, and upon resetting, the hold capacitor Cl is charged to the power supply voltage +VS.

Next, the operation will be explained.

First, when the reset switch RS is connected, the hold capacitor C1 is charged to +vS, and the second differential amplifier 2
The signal is fed back to the inverting input terminal of the first differential amplifier 201 via the voltage follower 02. When the input voltage Vin is lower than this feedback voltage Vf, the output voltage Vdl of the first differential amplifier 201 becomes a negative voltage and the diode D
Since i is in the forward direction, the charge in the hold capacitor C1 is discharged. When the discharge further progresses and the charging voltage of the hold capacitor C1 becomes low and the feedback voltage vf becomes below the human power voltage, the output voltage V of the first differential amplifier 201
Since dl becomes a positive voltage and the diode D1 goes in the opposite direction, the discharge of the hold capacitor C1 is stopped. As described above, the minimum value of the manually applied voltage is detected and held until a lower voltage is applied manually or until it is reset by the reset switch RS.

[Problem to be solved by the invention]

Conventionally, when detecting the minimum value, it was necessary to configure and use a minimum value detection module or minimum value detection circuit, and it was not possible to use a more general maximum value detection and holding circuit (peak hold circuit). There wasn't.

In view of the above points, an object of the present invention is to provide a minimum value detection circuit using a general-purpose peak hold circuit.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a peak hold circuit that is carried by a signal processing circuit and detects the maximum value of a DC signal;
a first subtraction and inversion circuit that is provided before the peak hold circuit and inverts the sign after subtracting the reference signal from the detection signal;
A signal processing circuit for minimum value detection is configured to include a second subtracting and inverting circuit that is provided after the peak hold circuit and subtracts a reference signal from the detected maximum value and then inverts it.

[Effect]

The minimum value detection signal processing circuit of the present invention having the above configuration operates as follows.

The reference signal is subtracted from the detected DC signal before the peak hold circuit, the sign is inverted, the minimum value is detected and held as the maximum value by the peak hold circuit, the reference signal is subtracted again, and the sign is inverted. value can be detected.

In this way, the minimum value can be detected by using the peak hold circuit without newly providing a minimum value detection circuit component.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1 to 9.

FIG. 1 is a diagram explaining the principle of the present invention.

The minimum value detection signal processing circuit 1 includes a first subtracting and inverting circuit 2 that outputs a signal S1 having a value obtained by subtracting a reference voltage V ref' from the human input signal Vin and then inverting its sign. A peak hold circuit 3 and an output signal S detect and hold the maximum value of the output signal S1 of the subtraction inversion circuit 2 and output the output signal S2.
The second subtracting and inverting circuit 4 outputs an output signal V out having a value obtained by subtracting the reference voltage V rer from 2 and inverting the sign thereof.

Next, the operation will be explained.

The detection signal Vin is input to the first subtracting and inverting circuit 2, and after subtracting the reference voltage Vrer, the sign is inverted, so that the first
The output signal S1 of the subtracting and inverting circuit 2 is as follows.

SL=-(Vin-Vrer) Next, the peak hold circuit 3 detects and holds the maximum value of the output signal S1. Here, the maximum value Slmax of S1 held by the peak hold circuit 3 is the signal when the input signal Vin is the minimum value (Vin) m]n, and SL+++ax= - ((Vin) min -V
ref ), and the signal Vout output from the second subtracting and inverting circuit 4 is Vout − − (S1.max−Vrer) −
1(- ((Vin) min -Vref'
)=Vrer)−(Vin)ynin, and the minimum value (Vjn)min is detected.

Next, an embodiment will be described in which the minimum value detection signal processing circuit of the present invention is applied to a wall thickness inspection apparatus for synthetic resin containers.

Figure 2 shows an overview of the wall thickness inspection device.

The wall thickness inspection device 5 includes a control calculation unit 7 that performs overall control and data calculation processing, and an inspection unit 8 that inspects wall thickness.

The inspection section 8 includes an insertion tube 12 inserted into the PET container, an insertion tube elevation control section 13 that inserts the insertion tube 12 into the PET container 18 and takes it out from the PET container, and a light source section that generates infrared rays 19 for measurement. 16.Insert the infrared rays for measurement into the tube 12
A light emitting part 14 that emits light to the PET container 18, a sensor light receiving part 15 that converts the amount of transmitted infrared rays transmitted through the insertion tube 12 and the body wall of the PET container 18 into an electrical signal by a sensor, and the PET container 18 from the conveyor to the inspection position. P during transportation and measurement
It consists of a container transport rotating section 17 that rotates the ET container 18 in the circumferential direction of the PET container.

The control calculation section 7 consists of a main control section 9 that controls the entire device, an interface control section (IF control section) 101 that controls data exchange with the inspection section 8, etc., and an arithmetic processing section 11 that performs data calculation processing. ing.

FIG. 3 shows an explanatory diagram of the principle of the arithmetic processing section 11.

The arithmetic processing unit 11 includes a wall thickness calculation circuit 101 that calculates a sensor output signal to generate a wall thickness signal, a maximum value detection circuit 102 that detects and holds the maximum value of the wall thickness signal, and a maximum value detection circuit 102 that detects and holds the minimum value of the wall thickness signal. It consists of a minimum value detection circuit 103, a difference detection circuit 104 that detects the difference between the maximum value and the minimum value, and an average value calculation circuit 105 that calculates the average value of the wall thickness signal.

First, the sensor output signal B is calculated by the wall thickness calculation circuit 101, converted into a wall thickness signal TPET, and output.

Next, the output wall thickness signal T PET is processed by a maximum value detection circuit 102 that detects the maximum value of the wall thickness of the container to be measured, a minimum value detection circuit 103 that detects the minimum value of the wall thickness, and an average value of the wall thickness. It is output to the average value calculation circuit 119 for calculation.

FIG. 4 shows a diagram explaining the principles of the maximum value detection circuit, minimum value detection circuit, and difference detection circuit.

Incidentally, gain adjustment amplifiers GA, GA for input adjustment are connected upstream of the maximum value detection circuit and the minimum value detection circuit.

The maximum value detection circuit 102 includes a peak hold circuit 113 that detects and holds the maximum value.

FIG. 5 schematically shows the maximum value detection output signal T max and the wall thickness signal T PET at that time.

The minimum value detection circuit 103 receives an external reference voltage signal Vre.
A first subtraction inversion circuit 114 that subtracts 'f and the thickness signal T PET and inverts the sign, a peak hold circuit 115 that holds the maximum value T lmax of the output signal Tl of the first subtraction inversion circuit 114, and a peak hold circuit The second subtracting and inverting circuit 116 subtracts the output signal T lmax of the circuit 115 from the reference voltage signal V rer and inverts the sign thereof.

In this case, the peak hold circuit 115 is the same as the peak hold circuit 113 of the maximum value detection circuit 102.

In this embodiment, the thickness signal T PET is a DC signal having a positive value, and the reference voltage signal V ref is a DC signal that is positive and larger than the maximum value that the thickness signal T PET can take.

The output signal T1 from the first subtraction inversion circuit 114 is Tl
--(TPET-Vref').

Here, the maximum value Tlmax of T1 held by the peak hold circuit 115 is the wall thickness signal T, and the minimum value Tm
It is the voltage at the time of in, and T Lmax − − (T min − V re
f), and the signal T2 output by the second subtracting and inverting circuit is T2 = − (Tlmax−Vref)=
- (1 (Tmjn -Vref')
-Vrer)=Tmin, and the minimum value T i+in is detected.

FIG. 6 schematically shows the minimum value detection output signal T min and the wall thickness signal T PET at that time.

The difference detection circuit 104 receives the output signal T of the maximum value detection circuit 102.
Inverting circuit 1 which inverts the sign of max] 7 and inverting circuit 1
17 and the output of the minimum value detection circuit and inverts the sign thereof, the addition/inversion circuit 118 detects and outputs the difference T dif' between the maximum value and the minimum value.

FIG. 7 schematically shows the difference detection output signal T dir and the thickness signal T PET at that time.

FIG. 8 shows a diagram explaining the principle of the average value calculation circuit.

The average value calculation circuit 119 includes a gain adjustment circuit 120 that adjusts the gain so that the integral value becomes exactly the average value of the thickness at the end of the integration, an integration circuit 121 that integrates the output signal of the gain adjustment circuit 120, and an integration circuit 121 that integrates the output signal of the integration circuit. It consists of an adjustment circuit that performs input adjustment for inputting the integrated value into the peak hold circuit 123, and a peak hold circuit 123 that holds the integrated value.

Thickness signal T PET output from the thickness calculation circuit 101
is input to the gain adjustment circuit, gain adjusted, and input to the integration circuit. The output signal T ave integrated and outputted by the integrating circuit is adjusted so as to indicate the average wall thickness value at the end of the measurement, and is held by the peak hold circuit 123 in order to make a judgment after the measurement.

Figure 9 shows the average value signal Ta've and the wall thickness signal T at that time.
PET is shown schematically.

In the figure, the slope portion of the average value signal T ave is the portion where integration is performed, and the value after the integration is completed indicates the average value.

〔Effect of the invention〕

The present invention provides a peak hold circuit that detects the maximum value of a DC signal in a signal processing circuit, a first subtraction inversion circuit that is provided before the peak hold circuit and that inverts the sign after subtracting a reference signal from the detection signal, and a peak hold circuit that detects the maximum value of a DC signal. Since we have configured a signal processing circuit for minimum value detection consisting of a second subtracting and inverting circuit that is installed after the hold circuit and subtracts the reference signal from the detected maximum value and then inverts it, we can configure a new minimum value detection module. By reusing a peak hold circuit that detects the maximum value of a DC signal, it is possible to easily configure a signal processing circuit for detecting a minimum value.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the signal processing circuit of the present invention, Fig. 2 is a schematic diagram of the wall thickness inspection device, Fig. 3 is an explanatory diagram of the principle of the arithmetic processing section, and Fig. 4 is a maximum value detection circuit and a minimum value detection circuit. A diagram explaining the principles of the detection circuit and the difference detection circuit. Figure 5 is a schematic diagram of the output of the maximum value signal, Figure 6 is a diagram of the output of the minimum value signal, Figure 7 is a diagram of the output of the difference signal, and Figure 8 is a diagram of the output of the difference signal. Explanatory diagram of average value detection circuit, No. 9
The figure is a schematic diagram of the output of the average value signal, and FIG. 10 is an explanatory diagram of a conventional minimum value detection circuit. DESCRIPTION OF SYMBOLS 1... Signal processing circuit for minimum value detection, 2... First subtraction inversion circuit, 3... Peak hold circuit, 4... Second
Subtraction inversion circuit, 5... Thickness inspection device, 7... Control calculation section, 8... Inspection section, 9... Main control section, 10...
Interface control unit, 11... Arithmetic processing unit, 12.
... Insertion inspection section, 13... Insertion inspection section elevation control device,
14... Light projecting section, 15... Sensor light receiving section, 16...
- Light source section, 17... Container transport rotation section, 18... PE
T container, 19...Infrared ray for measurement, 101...Thickness calculation circuit, 102...Maximum value detection circuit, 103...Minimum value detection circuit, 104...Difference detection circuit, 105...
Average value calculation circuit, 113...Peak hold circuit, 1
14... First subtraction inversion circuit, 115... Peak hold circuit, 116... Second subtraction inversion circuit, 117...
・Inversion circuit, 118... Addition inversion circuit, 119...
Average value calculation circuit, 120... Gain adjustment circuit, 121
...Integrator circuit, 122...Adjustment circuit, 123...
peak hold circuit.

Claims (1)

[Claims] A peak hold circuit that detects the maximum value of the DC signal, a first subtraction and inversion circuit that is provided before the peak hold circuit and inverts the sign after subtracting the reference signal from the detection signal, and a first subtraction and inversion circuit that is provided after the peak hold circuit and detects the and a second subtracting and inverting circuit that subtracts a reference signal from the maximum value and then inverts the signal.