JPS61173507A - Automatic level control circuit - Google Patents

Abstract

PURPOSE:To control output electric power accurately even when the output electric power is intermitted by constituting a digital sample and hold circuit and holding the counted value of a counting means. CONSTITUTION:When the output electric power of a power amplifier 1 is on, a detector 4 extracts and converts part of its output electric power into a DC voltage, which is applied to an amplifier 5. A decision making circuit 10, on the other hand, detects the on state of the output electric power to input its output to one input terminal of an AND circuit 11 and also input a clock pulse from a clock pulse generator 9 to a counter 8. When the output electric power of the power amplifier 1 turns off, the clock pulse input to the counter 8 is ceased, so the counter 8 holds its counted value right before stopping counting and indicates the constant value. This constant value is held by a D/A converter 12, so the output of the D/A converter 12 becomes constant and the quantity of attenuation of a PIN attenuator 13 is fixed until a next clock pulse is inputted to the counter 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides automatic level control (Autoa+atic Level Control) for minimizing output power fluctuations of power amplifiers, etc.
C.

The present invention relates to an automatic level control circuit for minimizing output power fluctuations in a system in which the output power is periodically or non-periodically interrupted.

[Conventional technology]

According to the conventional technology, the output power is turned on temporarily.

In the ALC circuit of the OFF system, a part of the output power is extracted, detected and amplified, and the analog signal is sampled only during the period when the output power is ON, and when the output power is OFF.
In this case, an analog sample-and-hold circuit was used to hold the analog signal in a capacitor or the like.

[Problem that the invention seeks to solve]

According to such conventional analog type sample and hold circuits, the time constant of the holding circuit is a finite value, so if the output power is off for a long time, it will discharge and the held voltage will drop. Then, the output power becomes O
When the N state is reached, an error occurs in the output power. If the time constant is made longer to reduce this, the charging time constant during sampling will also be longer (this has the disadvantage that when sending a signal with a narrow pulse width, it will not be able to charge sufficiently, causing an error in the output power. .

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to provide an ALC circuit that eliminates the above-mentioned drawbacks and can accurately control output power.

For this reason, the present invention provides an automatic level control circuit for minimizing output power fluctuations in a system in which output power is periodically or non-periodically intermittent. a detection means for generating the voltage, and a comparison means for comparing the output voltage of the detection means with a reference voltage;
A counting means that counts up or down according to the output of the comparison means, a clock pulse input means that inputs a clock pulse to the counting means only when the output power is present, and a digital output of the counting means to an analog output. and means for controlling the attenuation means provided in the system, and these means constitute a negative feedback loop so that the output level becomes constant.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 shows an embodiment of an ALC circuit according to the present invention.

According to this ALC circuit, a detector 4 that extracts a part of the output power of the power amplifier 1 and converts it into a DC voltage is provided on the output terminal 2 side of the power amplifier 1 that is to perform level control. It is connected to one input terminal of a comparator 6 via an amplifier 5. A reference voltage source 7 that generates a reference voltage corresponding to the required output power of the power amplifier 1 is connected to the other input terminal of this comparator. Comparator 6 is digital counter 8
is connected to the up-count or down-count terminal.

The ALC circuit of this embodiment further includes a circuit for supplying clock pulses to operate the counter 8, and this circuit is connected to the clock noise generator 9 and the output power or input power of the power amplifier 1. It consists of a determination circuit 10 that determines the presence or absence of output power or input power and generates an output when there is output power or input power, and an AND circuit 11 that takes the logical product of the outputs of the clock pulse generator 9 and the determination circuit 10. has been done. The AND circuit 11 is connected to the clock input terminal of the counter 8.

According to this embodiment, the digital sample and hold circuit is configured as described above.

The counter 8 is connected to a D/A converter 12, which is provided on the input terminal 3 side of the power amplifier 1 and connected to an attenuator such as a PIN attenuator 13.

Next, the operation of the ALC circuit of this embodiment will be explained.

When the output power of the power amplifier 1 is ON, the detector 4 extracts a part of the output power and converts it into a DC voltage, which is then applied to the amplifier 5.
Enter. On the other hand, the determination circuit 10 detects ON of the output power and inputs the output to one input terminal of the AND circuit 11, thereby inputting the clock pulse from the clock pulse generator 9 to the counter 8.

The amplifier 5 amplifies the DC voltage input from the detection s4 and inputs it to one input terminal of the comparator 6. The comparator 6 compares the output voltage from the amplifier 5 with the reference voltage from the reference voltage source 7, and generates an output when the output voltage is higher than the reference voltage, and outputs an output when the output voltage is lower than the reference voltage. does not occur. That is, comparator 6
turns the output voltage ON and OFF at the set reference voltage.
F. The output voltage of the comparator 6 is input to the up/down count terminal of the counter 8 as a control signal. As mentioned above, the counter has an AND circuit 11.
Since more clock pulses are input, it counts up or down. The counter 8 is configured to count up when the output voltage of the amplifier 5 is higher than the reference voltage and count down when it is lower, or vice versa.

The digital output of the counter 8 is sampled and held in a D/A converter 12 and converted into an analog signal, which controls the amount of attenuation of the PIN attenuator. In other words, the amplifier 5 is activated only during the period when the counter 8 receives a clock pulse, and therefore when the output power or input power is present.
The output of the counter 8 changes so that the output voltage of the D/A converter 1 becomes the same as the reference voltage of the reference voltage source 7.
2 controls the amount of attenuation of the PIN attenuator 13.

When the output power of power amplifier 1 turns OFF, counter 8
Since there is no longer a clock pulse input to the counter 8, the counter 8 maintains a constant value while storing the count value immediately before it stopped counting. Since the D/A converter 12 holds this constant value, the output of the D/A converter 12 becomes constant and the attenuation amount of the PIN attenuator 13 is fixed until the next clock pulse is input to the counter 8. Therefore, even if the output power is turned off for a long period of time, the PIN
Since there is no variation in the amount of attenuation of the attenuator 13, the error in the output power is extremely small.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and it goes without saying that various modifications and changes can be made within the scope of the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, a digital sample and hold circuit is configured to hold the count value of the counting means, so that output power can be accurately controlled even when output power is intermittent. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1...Power amplifier 4...Detector 5...Amplifier 6...Comparator 7...Reference voltage source 8...Counter

Claims (1)

[Claims] (1) In an automatic level control circuit for minimizing output power fluctuations in systems where output power is periodically or non-periodically intermittent, the output power is detected and a DC voltage is generated according to the output level. a detecting means, a comparing means for comparing the output voltage of the detecting means with a reference voltage, a counting means for counting up/down according to the output of the comparing means, and a clock for the counting means only when the output power is present. comprising clock pulse input means for inputting pulses, and means for converting the digital output of the counting means into an analog output and controlling the attenuation means provided in the system, and these means constitute a negative feedback loop, An automatic level control circuit characterized in that the output level is constant.