JPH02131025A - Data interpolation device - Google Patents

Abstract

PURPOSE:To attain interpolation with less error and no production of high frequency component by selecting a polynomial and a coefficient in use and applying interpolation in response to an error pattern. CONSTITUTION:The flags of latches 27-31 and 33-36 are inputted to an error pattern detector 25, coefficients are outputted to multipliers 15-20 and 21-24 in response to the pattern of each flag and multiplied with the outputs of latches 2-7 and 9-12 respectively and outputted to an adder 20. The adder 20 adds all outputs of the multipliers 15-20 and 21-24 and sends the result to one input of a selector 8. The selector 8 selects a data from the adder 20 when the output of the latch 32, that is, the flag of the output data of the latch 7 is logic 1 and outputs the result to the latch 9. When the output of the latch 32 is 0, that is, the output data of the latch 7 is correct on the contrary, the selector 8 selects the output of the latch 7 and outputs the result to the latch 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data interpolation method for interpolating erroneous data in digital audio and the like.

[Conventional technology]

Conventionally, a combination of an average value interpolation method and a previous value hold method is well known as a method for interpolating erroneous data.

FIG. 3 is a diagram showing a conventional data interpolation device.
is a latch that latches data sent from the data input terminal (b), 翰 is a latch that latches data sent from the latch (to), and (to) is the output of the latch, latch 翰. A selector that selects the output of ) and the output of ) to the divider, (goods) a latch that latches the output of ) to the selector, ■ an adder that adds the outputs of latch (to) and latch (2), and warm is a constant A constant generator that generates 4) is a divider that divides the output of the adder by the output of the constant generator 4)
is a latch that latches the flag sent from the flag input terminal I4η, 01 is a latch that latches the output of the latch, (b) is a data input terminal, (b) is a clock input terminal, 67) is a flag input terminal, (6) is a data output terminal.

Next, the operation will be explained using FIGS. 3 and 4.

In FIG. 4, time Tl + ++1 r Tl+
2... data is Di, Di+l + D
I+2... Bind. When the data is correct, mark Q, and when the data is incorrect, mark . That is, in FIG. 4, Di
+2. Di+3. Di-h is incorrect data,
Dl+DI+I+DI+5 is correct data.

The erroneous data is held until the correct data Di+3, which is two data before the correct data Di+s, and the previous correct data Di+t (C previous value hold). That is, Di+1
Di+2, so that =Di+2=Di+3
Di issue is interpolated. Then, the data Di-h immediately before the correct data Di+s is the interpolated value of Di+3,
The data is interpolated using the average value of the positive data Di+5.

Next, explanation will be given using FIG. The following values of S are given to the selector according to the contents of the flags latched in the latches and latches.

(Here, the "value of S" is a condition for selecting a signal that is given for convenience in explaining the operation.) Now, the latch (to), the latch handle, and the latch (weigh) are each given as a condition for selecting a signal. Data DI+3 and DI+2 + ”+1 are latched, and the flag “111” is set in latch (G) and latch 0I, respectively.
+, 1 "1" (flag "1" indicates that the data is incorrect) is set in latch table 1 (x mark indicates that the flag can be either 0.1), selector ( ) is given S=1, and with a new lock input, the latch 0 sword is
Data Di+ of the latch is latched as an interpolated value of data Di+2. (Previous price hold) At this point,
Data DI+4 + DI+3 + Di+2 is latched in the latch (to), latch handle, and latch (2), and a flag “1” is set in the latch (7) and latch (to), respectively.
“°゛1” is latched. Then, with the next clock input, the latch 0 sword is latched (6) as before.
Data Di+2 is latched as an interpolated value of data Di+3. (Previous price hold) Furthermore, at this point, data Dl+5+ DI+4+ DI is stored in latch (to), latch (2), and latch (wealth), respectively.
+3 is latched, and flags "0" and "1" are latched in latch (7) and latch (2), respectively. The selector (to) is given s-3, and with a new lock input, the latch G11l receives Di+3, which was latched by the latch (9), and Di, which was latched by the latch (to).
The average value of +s is calculated using an adder color, a constant generator (c), and a divider), and is latched as an interpolated value of data Di+i.

Data interpolation was performed in the conventional data interpolation method as described above.

Now, let's consider a sine wave with a sampling frequency of 48 KHz and a quantization bit count of 16, in which 3 consecutive erroneous data out of every 10 data, and examine the maximum value of the interpolation error when interpolating the erroneous data, as shown in Figure 5. , it looks like an x mark. The detection limit for interpolation error is 102. lt(=316'
) step ("Error Interpolation Method in PCM Magnetic Recorders" Sony Institute of Technology, Acoustical Society of Japan Lecture Proceedings, May 1978), so with the conventional interpolation method, the interpolation error is It can be seen that the maximum value of is beyond the detection limit.

Similarly, the maximum value of interpolation error when there is only one piece of error data is represented by an x mark in FIG. Similarly, it can be seen that the detection limit is around 1 KHz.

[Problem to be solved by the invention]

In conventional data interpolation methods, when data is incorrect continuously, the previous value is held, which increases interpolation errors and generates high-frequency components, resulting in abnormal noise.

The present invention has been made to solve the above-mentioned problems, and aims to provide a data interpolation method in which interpolation errors are extremely small and high frequency components are not generated.

[Means to solve the problem]

The data interpolation method according to the present invention selects a polynomial and coefficients to be used according to the pattern of error data, and interpolates data using the polynomial and coefficients.

[Effect]

The data interpolation method according to the present invention performs interpolation with less error by selecting the polynomial and coefficients to be used according to the pattern of error data.

[Embodiments of the invention]

As a method of interpolating error data with less error, there is a method of using a high-order polynomial, which will be explained with reference to FIG. For example, if data Dn is incorrect and is interpolated using a 5th order polynomial, six data items before and after Dn(7), ie, Dn-3 to Dn-1.

and a quintic equation passing through Dn+1 to DIl+3. Since the time axis interval is constant depending on the sampling frequency, the value of Dn is determined by the following formula.

Dn = kl(Dn-, +Dn+3)+k2
(Dn-2+I)n+2)+k3 (Dn-1+D
n + t) This invention selects a polynomial and coefficients according to the pattern of error data and performs interpolation.

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a data input terminal, (2) to f61
．． +81~(2), 翰~(7) are latches, (8) is a selector for switching between data and interpolated data,
(To) is a data output terminal, C4 is a clock input terminal that inputs a clock for latching data to each latch, (To) to α and 3D- (To) are multipliers, (A) is an adder, (b) is an error pattern detector that inputs error flags and outputs coefficients to each multiplier according to the pattern;
) is a flag input terminal into which an error flag is input.

In addition, latch +21
The error flags of the data latched in latches (9) to (7) and latches (9) to (2) are latched.

Next, the operation will be explained. The data input to the data input terminal (1) is latched (2), latch (3), etc. by the clock input from the clock input terminal α4.
The latch data is shifted one after another and output from the data output terminal (to). Similarly to the data, the flag input from the flag input terminal (to) is also shifted one after another by the clock input from the clock input terminal α from latch to latch to latch to latch. be done.

On the other hand, the error pattern detector (4) has a latch
D and latch flags are input, and multipliers (G) to (E) and r2D are input according to the pattern of each flag.
- Output the coefficients to C24, respectively, and output the coefficients to the latches (2) to (7).
) and the outputs of (9) to (a) and output to the adder. In the adder, the multiplier αQ~0 and 2
]) to (to) are all added and the result is sent to one input of the selector (8). In the selector (8), when the output of the latch (to), that is, the flag of the output data of the latch (7) is "'1" (indicating a data error), the data from the adder is selected and the data from the latch (to) is selected. 9). Conversely, when the output of the latch Q is "0", that is, the output data of the latch (7) is correct, the selector (8) selects the output of the latch (7) and outputs it to the latch (9).

Next, the operation of the error pattern detector @ will be explained. FIG. 2 shows an example of an error pattern. In the figure, a circle mark indicates a state in which the flag is not set, and a mark indicates a state in which a flag is set, that is, a state in which the data at that position is incorrect.

And the X mark indicates not to see the flag at that position, ◎
The mark indicates that the flag at that position is not seen, but the data at that position has already been interpolated or is data that is originally correct, so this data is used for interpolation.

Error pattern detection is performed using PATI, 2°... shown in the figure.
If the patterns match, the coefficients shown in Table 2 are output to multipliers (a) to αq and 311-(to). (All denominators are 2048) In Figure 2 and Table 2, PATl is a 7th degree polynomial, F
AT2 uses a fifth-order polynomial, FATs 3 to 8 use a fourth-order polynomial, FATs 9 to 17 use a third-order polynomial, and FATs 18 to 22 use a second-order polynomial. Also, FAT2
3 is a previous value hold.

In other words, if all eight pieces of data (four pieces before and after the error data) are correct, a seventh-order polynomial is used, and if there is no incorrect data among six pieces of data (three pieces before and after the error data), a fifth-order polynomial is used.
If there is one incorrect data, use a fourth-order polynomial; if there are two, use a third-order polynomial; if there is even one correct data among the last five, use a second-order polynomial; if there is none, use a second-order polynomial. Interpolation is performed using the previous value hold.

Figures 5 and 6 show the correct table x 1/2048 sinusoidal wave with a sampling frequency of 48 KHz and a quantization bit number of 16 when three pieces of data are continuous or one piece of data is incorrect, respectively. The results of comparing the maximum value of the interpolation error when using the conventional interpolation method and the interpolation method according to the present invention are shown below.

The horizontal axis represents the frequency of the sine wave, and the vertical axis represents the maximum number of steps for the difference between correct data and interpolated data, where the ○ mark indicates the interpolation method according to the present invention, and the X mark indicates the case of the conventional interpolation method. . It can be seen from both figures that the detection localized wave number is not significantly improved.

In the above embodiment, a case is shown in which interpolation is performed using 7th, 5th, 4th, 3rd, and 2nd order polynomials, but interpolation may be performed using other polynomials.

〔Effect of the invention〕

As described above, according to the present invention, interpolation is performed by selecting the polynomial and coefficients to be used depending on the error pattern, so that interpolation can be performed with few errors and no generation of high frequency components.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a data interpolation device according to an embodiment of the present invention, FIG. 2 is a diagram showing a data error pattern in an embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional data interpolation device. , @Figure 4 shows the conventional data interpolation method, and Figure 5 shows the interpolation error when data is interpolated using the conventional interpolation method and the interpolation method of the present invention when three consecutive data errors occur. Similar to FIG. 5, FIG. 6 is a diagram showing the interpolation error of each interpolation method when one data error occurs, and FIG. 7 is a diagram showing the polynomial interpolation method. (1) is a data input terminal, (2) to (61, +81 to (
), @ ~ (to) is a latch, (8) is a selector, @ is a clock input terminal, α9 to α 燵 and eII- (to) are multipliers, 翰 is an adder, (to) is an error pattern detector , (e)
is a flag input terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) When interpolating erroneous data from the preceding and following correct data, select a polynomial and coefficients to be used according to the position pattern of one or more pieces of erroneous data, and use this polynomial and coefficients to interpolate the erroneous data. A data interpolation device that performs interpolation. (2) Among the one or more pieces of error data, data that has not yet been interpolated and is temporally earliest is set as the center of the position pattern and the interpolation target. Data interpolation device as described in section.