JPH02131018A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02131018A
JPH02131018A JP63284628A JP28462888A JPH02131018A JP H02131018 A JPH02131018 A JP H02131018A JP 63284628 A JP63284628 A JP 63284628A JP 28462888 A JP28462888 A JP 28462888A JP H02131018 A JPH02131018 A JP H02131018A
Authority
JP
Japan
Prior art keywords
circuit
specific
block
power supply
circuit block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63284628A
Other languages
Japanese (ja)
Inventor
Masahito Sato
雅人 佐藤
Hisayasu Sato
久恭 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63284628A priority Critical patent/JPH02131018A/en
Publication of JPH02131018A publication Critical patent/JPH02131018A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption of the entire semiconductor integrated circuit by providing a power pin to a power wire of a reference voltage generating circuit separately and supplying power to the reference voltage generating circuit via other power pin only at a specific time. CONSTITUTION:In the case of activating a specific block 2 such as a test circuit, the same voltage as that to a high voltage side power pin 3 is applied to a high voltage side power pin 9a to activate the block 2 similar to the normal operation circuit block. When the normal operation circuit block 1 is in operation, the same voltage as that to a low voltage side power pin 5 is applied to the high voltage side power pin 9a. In this case, the difference of potential between a wire part 10a of the reference voltage generating circuit 22 and a wire part 6 is lost and the potential goes to a low voltage. Since the bias voltage between the base and emitter of a transistor(TR) Q3 for a constant current source in the specific circuit block 2 is zero, the TR Q3 is always turned off. Thus, the specific circuit block is stopped.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、通常時に動作を行なう回路ブロックと特定時
に動作を行なう特定回路ブロックと備えた半導体集積回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that includes a circuit block that operates normally and a specific circuit block that operates at a specific time.

〔従来の技術〕[Conventional technology]

第3図は従来の半導体集積回路(エミッタ結合型論理回
路)のブロック図である。図において、1は通常動作す
る通常動作回路ブロック、2はある特定時のみ使用し通
常動作時は使用しない特定回路ブロック、3は高電圧側
電源ピン、4は高電圧側電源配線、5は低電圧側電源ピ
ン、6は低電圧側電源配線、7は図示してきないが各回
路ブロックに接続した入力ピン群、8は図示してきない
が各回路ブロックに接続した出力ピン群である。
FIG. 3 is a block diagram of a conventional semiconductor integrated circuit (emitter-coupled logic circuit). In the figure, 1 is a normal operation circuit block that normally operates, 2 is a specific circuit block that is used only at a certain time and is not used during normal operation, 3 is a high voltage side power supply pin, 4 is a high voltage side power supply wiring, and 5 is a low voltage side power supply pin. Voltage side power supply pins, 6 are low voltage side power supply wiring, 7 is a group of input pins connected to each circuit block (not shown), and 8 is a group of output pins connected to each circuit block (not shown).

また、特定回路ブロック2は基準電圧発生回路22、抵
抗R1〜R4及びトランジスタQ1〜Q4からなる差動
増幅器より構成されている。なお、19は差動増幅器の
出力、20.21は差動増幅器に与える基準電位である
Further, the specific circuit block 2 includes a reference voltage generating circuit 22, a differential amplifier including resistors R1 to R4, and transistors Q1 to Q4. Note that 19 is the output of the differential amplifier, and 20.21 is the reference potential given to the differential amplifier.

さて、このエミッタ結合型論理回路は、高電圧側電源ピ
ン3.低電圧側電源ピン5の各電源ピンにそれぞれ規定
の電圧を印加し、入力ピン群7に入力信号を入力するこ
とにより、通常動作回路ブロック1及び特定回路ブロッ
ク2を動作する。
Now, this emitter-coupled logic circuit has high voltage side power supply pin 3. By applying a prescribed voltage to each of the low-voltage side power supply pins 5 and inputting an input signal to the input pin group 7, the normal operation circuit block 1 and the specific circuit block 2 are operated.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら従来の半導体集積回路は、上記のように構
成されているので、通常動作時においても特定回路ブロ
ックに電力が供給されてしまい、半導体集積回路全体の
消費電力が増加する欠点があった。
However, since the conventional semiconductor integrated circuit is configured as described above, power is supplied to a specific circuit block even during normal operation, resulting in an increase in power consumption of the entire semiconductor integrated circuit.

本発明は上記の欠点を解決するためになされたもので、
通常動作時に特定回路ブロック2内の消費電力が零とな
る半導体集積回路を得ることを目的とする。
The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to obtain a semiconductor integrated circuit in which power consumption in a specific circuit block 2 becomes zero during normal operation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体集積回路は、基準電圧発生回路の電
源配線に別個の電源ピンを設けている。
In the semiconductor integrated circuit according to the present invention, a separate power supply pin is provided in the power supply wiring of the reference voltage generation circuit.

〔作用〕[Effect]

特定時のみ基準電圧発生回路に別個の電源ピンを介して
電源を供給する。
Power is supplied to the reference voltage generation circuit through a separate power supply pin only at specific times.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示した半導体集積回路(エ
ミッタ結合型論理回路)の回路図である。
FIG. 1 is a circuit diagram of a semiconductor integrated circuit (emitter-coupled logic circuit) showing one embodiment of the present invention.

図において、第3図と同一部分には同一符号を付する。In the figure, the same parts as in FIG. 3 are given the same reference numerals.

9aは特定回路ブロック2の基準電圧発生回路22に接
続された別途の電源ピンにあたる高電圧側電源ピン、1
0aは特定回路ブロックに接続された高電圧側電源配線
である。
9a is a high voltage side power supply pin that is a separate power supply pin connected to the reference voltage generation circuit 22 of the specific circuit block 2;
0a is a high voltage side power supply wiring connected to a specific circuit block.

次に、上記構成によるエミッタ結合型論理回路の動作に
ついて説明する。半導体集積回路内に内蔵された、例え
ばテスト回路のような特定ブロック2を動作させる場合
は、特定回路ブロック2の基準電圧発生回路22に接続
された高電圧側電源ビン9aに高電圧側電源ビン3と同
一の電圧を印加して、通常動作回路ブロックと同様に動
作させることができる。
Next, the operation of the emitter-coupled logic circuit having the above configuration will be explained. When operating a specific block 2 such as a test circuit built in a semiconductor integrated circuit, a high voltage side power supply bin 9a connected to the reference voltage generation circuit 22 of the specific circuit block 2 is connected to a high voltage side power supply bin 9a. By applying the same voltage as 3, it can be operated in the same way as the normal operation circuit block.

一方、特定回路ブロック2を動作させない場合(通常回
路動作ブロック1が動作している場合)は、特定回路ブ
ロック2の基準電圧発生回路22に接続された高電圧側
電源ビン9aに低電圧側電源ピン5と同一の電圧を印加
する。このとき、基準電圧発生回路22の配線部10a
の電位と配線部6の電位との位差が無くなり低電位とな
る。そして、基準電圧発生回路22の電位20.21も
共に低電位となる。これにより、特定回路ブロック2内
の停電流源用のトランジスタQ3のベース−エミッタ間
のバイアス電圧がOとなるため、トランジスタQ3は常
にオフ状態となる。従って、差動増幅器を構成するスイ
ッチングトランジスタQl、Q2も共にオフ状態となる
。また、差動増幅器の出カニミッタフォロアトランジス
タQ4において、ベース−エミッタ間が逆バイアス状態
となり、常にオフであるので出力端22の電位は低電位
となる。このため、特定回路ブロックは停止状態となる
On the other hand, when the specific circuit block 2 is not operated (when the normal circuit operation block 1 is operating), the low voltage side power supply is connected to the high voltage side power supply bin 9a connected to the reference voltage generation circuit 22 of the specific circuit block 2. Apply the same voltage as pin 5. At this time, the wiring section 10a of the reference voltage generation circuit 22
There is no difference in potential between the potential of the wiring portion 6 and the potential of the wiring portion 6, resulting in a low potential. The potentials 20 and 21 of the reference voltage generation circuit 22 also become low potentials. As a result, the base-emitter bias voltage of the power failure current source transistor Q3 in the specific circuit block 2 becomes O, so that the transistor Q3 is always in an off state. Therefore, both switching transistors Ql and Q2 constituting the differential amplifier are also turned off. Further, in the output limiter follower transistor Q4 of the differential amplifier, the base-emitter is in a reverse bias state and is always off, so the potential at the output terminal 22 is a low potential. Therefore, the specific circuit block is in a stopped state.

また、第2図は本発明の別の実施例を示した半導体集積
回路(エミッタ結合型論理回路)の回路図である。図に
おいて、第1図と同一部分には同一符号を付する。9b
は特定回路ブロック2に接続された別途の電源ピンにあ
たる高電圧側電源ビン、10bは特定回路ブロックに接
続された高電圧側電源配線である。
Furthermore, FIG. 2 is a circuit diagram of a semiconductor integrated circuit (emitter-coupled logic circuit) showing another embodiment of the present invention. In the figure, the same parts as in FIG. 1 are given the same reference numerals. 9b
10b is a high voltage side power supply bin corresponding to a separate power supply pin connected to the specific circuit block 2, and 10b is a high voltage side power supply wiring connected to the specific circuit block.

第2図においても第1図と同様に、特定回路ブロックを
高電圧側電源ビン9bへの電圧の切り換えによって動作
または停止状態にすることができる。
In FIG. 2, as in FIG. 1, a specific circuit block can be brought into operation or stopped by switching the voltage to the high-voltage side power supply bin 9b.

このように、特定回路ブロック2における基準電圧発生
回路22のトランジスタ01〜Q4全てがオフ状態とな
るので、特定回路ブロック2の消費電力が零となり、半
導体集積回路全体の消費電力を低く抑えることができる
In this way, all transistors 01 to Q4 of the reference voltage generation circuit 22 in the specific circuit block 2 are turned off, so the power consumption of the specific circuit block 2 becomes zero, and the power consumption of the entire semiconductor integrated circuit can be kept low. can.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、基準電圧発生回路の電源
配線に別個の電源ピンを設けているため、特定時のみ基
準電圧発生回路に別個の電源ピンを介して電源を供給す
ることができる。このため、通常時に動作を行なう回路
ブロックが動作しているときの特定回路ブロックの消費
電力を零にすることができ、半導体集積回路全体の消費
電力を低く抑えることができるという顕著な効果を有す
る。
As described above, in the present invention, since a separate power supply pin is provided in the power supply wiring of the reference voltage generation circuit, power can be supplied to the reference voltage generation circuit through the separate power supply pin only at specific times. This has the remarkable effect of reducing the power consumption of a specific circuit block to zero when the circuit block that normally operates is in operation, and reducing the power consumption of the entire semiconductor integrated circuit. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す半導体集積回路の回路
図、第2図は別の実施例を示す半導体集積回路の回路図
、第3図は従来の半導体集積回路の回路図である。 1・・・通常動作回路ブロック、2・・・特定回路ブロ
ック、9a、9b・・・高電圧側電源ピン、22・・・
基準電圧発生回路。
FIG. 1 is a circuit diagram of a semiconductor integrated circuit showing one embodiment of the present invention, FIG. 2 is a circuit diagram of a semiconductor integrated circuit showing another embodiment, and FIG. 3 is a circuit diagram of a conventional semiconductor integrated circuit. . 1... Normal operation circuit block, 2... Specific circuit block, 9a, 9b... High voltage side power supply pin, 22...
Reference voltage generation circuit.

Claims (1)

【特許請求の範囲】 通常時に動作を行なう回路ブロックと特定時に動作を行
なう基準電圧発生回路を設けた特定回路ブロックとを備
え、各回路ブロックを電源配線を介して電源ピンに接続
した半導体集積回路において、 前記基準電圧発生回路の電源配線に別個の電源ピンを設
け、 特定時のみ前記基準電圧発生回路に前記別個の電源ピン
を介して電源を供給することを特徴とする半導体集積回
路。
[Claims] A semiconductor integrated circuit comprising a circuit block that operates normally and a specific circuit block provided with a reference voltage generation circuit that operates at a specific time, each circuit block being connected to a power supply pin via a power supply wiring. A semiconductor integrated circuit, wherein a separate power supply pin is provided in the power supply wiring of the reference voltage generation circuit, and power is supplied to the reference voltage generation circuit via the separate power supply pin only at specific times.
JP63284628A 1988-11-10 1988-11-10 Semiconductor integrated circuit Pending JPH02131018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63284628A JPH02131018A (en) 1988-11-10 1988-11-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63284628A JPH02131018A (en) 1988-11-10 1988-11-10 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02131018A true JPH02131018A (en) 1990-05-18

Family

ID=17680929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63284628A Pending JPH02131018A (en) 1988-11-10 1988-11-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02131018A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167619A (en) * 1990-10-26 1992-06-15 Toshiba Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167619A (en) * 1990-10-26 1992-06-15 Toshiba Corp Semiconductor integrated circuit

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