JPH02129962A - Read only memory - Google Patents

Abstract

PURPOSE:To prevent a penetration current and assure high speed and balanced readout by more increasing threshold voltage of an enhancement type MIS transistor among MIS transistors constituting a memory cell than that of peripheral circuit MIS transistors. CONSTITUTION:The threshold voltage of enhancement type MOS transistors in memory cell arrays 1, 2 is made higher than that of a peripheral circuit enhancement type MOS transistors. Therefore, when the enhancement type MOS transistor is selected, the transistor is switched off in an early stage. Hereby, a penetration current can be restricted and readout can be made a high speed together with assurance of balanced readout by optimization of the threshold voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides depletion type and enhancement type M
Read-only memory (ROM; Read) that stores data by combining IS transistors.
0nly Memory).

[Summary of the Invention] The present invention provides a read-only memory in which a memory cell array is configured by serially connected MIS transistors, and the M[S transistors are a combination of an enhancement type and a depletion type.
By making the threshold voltage of the enhancement type MIS transistor among the IS transistors higher than the threshold voltage of the MIS transistor in the peripheral circuit, through current is prevented and high-speed access time is realized.

[Conventional technology]

A read-only memory is known in which a memory cell array is constructed by combining a depletion type MOS transistor and an enhancement type MOS transistor, and each of these MOS transistors is arranged vertically. In addition, some of these read-only memories are provided with a potential supply means such as a precharge circuit on a common output terminal, and for example, the technology described in Japanese Patent Publication No. 63-29833 exists as an earlier technology. do.

FIG. 8 shows the configuration of the vertical memory cell (NAND type), and the terminal 81 is connected to a focus line (not shown). Each MO3 transistor is connected in series and selected by selection lines XI, X2 and words lX0I-XO8. In the illustrated example, the selection line χ2 and the word line XO2
, XO8 as gates are depletion type MO3 transistors, and these transistors are normally on. When reading, after the precharge operation,
For example, the selection line X1 is at a high level (for example, the voltage Vcc)
This means that the current memory block has been selected. Then, one of the word lines X01 to XO8
is set to a low level (for example, ground voltage GND), and if the MOS transistor connected to that word line is an enhancement type, the voltage at the terminal 81 (that is, the bit line) remains unchanged, and if it is a depletion type, the potential at the terminal 81 is grounded. It is pulled towards the voltage GND. In other words, the stored data appears as a change in the potential of the bit line.

[Problem to be solved by the invention]

However, in the read-only memory having the above-described structure, a problem arises in that a through current flows when the next transistor is selected from the transistor used for reading.

This will be explained with reference to FIG. 9, which is a waveform diagram at the time of reading. The signal Φ is a signal from the address transition detection circuit (ATD) and falls at the time of address transition, and as a result, the potential of the bit lines bit is raised by the bias circuit. Here, M of depletion type
Considering the case where an enhancement type MOS transistor (word line X01) is selected next to the OS transistor (word 1XO8), the potential of the already selected word line X08 changes from the ground voltage GND level (for example, OV) to the power supply voltage. Vcc level (for example, 5 V), and the potential of the word line XOI to be selected next changes from the power supply voltage Vcc level to the ground voltage GND level. At this time, the threshold voltage Vth of the enhancement type MOS transistor
(E) is about IV, so even after the bias circuit is activated by the signal Φ, the word line χ01 remains until time to+.
The MOS) switch is turned on. As a result, a through current flows from the bit line to the ground voltage GND through the memory cell block, and even though an enhancement type MOS transistor is selected, the through current causes a flow similar to a depletion type MOS transistor. A potential drop occurs on the bit line. This causes a problem in that the potential of one of the precharged data lines drops, resulting in a delay in data reading.

To address this problem, the potential drop on one data line can be suppressed by lengthening the precharge period, but this does not solve the problem because the access time becomes longer. Furthermore, by shortening the word line, the potential rise of the word line can be made faster; however, it becomes necessary to arrange an extra row decoder, and the degree of integration is sacrificed.

In view of the above-mentioned technical problems, the present invention aims to provide a read-only memory that prevents through-current and realizes high-speed reading.

[Means to solve the problem]

In order to achieve the above object, in the read-only memory of the present invention, a memory cell array is configured with a plurality of MIS transistors connected in series. The gates of these MIS transistors are connected to selection lines and word lines. Data from the memory cell is read out via a focus line or a data line, and a precharge means such as a bias circuit can be connected to the bit line or data line. Reading can be performed using, for example, a sense amplifier, and it is also possible to amplify data using a dummy cell in order to read data related to selection. Data storage is performed using depletion type and enhancement type MIS transistors. It is done by combination.

In the read-only memory of the present invention, the peripheral circuit in which the threshold voltage of the enhancement type MIS transistor constituting the memory cell is higher than the threshold voltage of the MIS transistor constituting the peripheral circuit includes a sense amplifier,
These are decoders, human output buffers, and other various circuits. The threshold voltage of the enhancement-type MIS transistor that constitutes the memory cell may be sufficient to suppress the through current, and by increasing the threshold voltage, the through current can be reduced. However, the remainder threshold (
+! When the lightning voltage is high, when a depletion type MIS transistor is accessed, the channel conductance of an enhancement type MIS transistor connected in series with the depletion type MIS transistor becomes low, so that the access time becomes longer. Therefore, it is also possible to set the threshold voltage of the enhancement type MIS transistor so that the access time is shortest.

[Effect]

By increasing the threshold voltage of the enhancement type MrS transistor of the memory cell, the period during which the enhancement type MIS transistor is in an on state at the time of address transition is shortened, and therefore the through current is suppressed. Further, since the threshold voltage of the enhancement type MIS transistor in the peripheral circuit does not change, no problem arises in its operation.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

In the read-only memory of this embodiment, the threshold voltage V of the enhancement-type MOS transistor of the memory cell is increased, so that the through current is suppressed and high-speed reading is realized.

First, its configuration will be explained with reference to FIGS. 2 to 6.

FIG. 2 shows the block configuration of the read-only memory of this embodiment, in which a memory cell array 1.2 consisting of a plurality of memory cell blocks is provided, and between the memory cell arrays 1 and 2, there is a A sense amplifier 3 is provided to amplify the signal. The memory cells of each memory cell array 1 and 2 are selected by a decoder 4.5, and the memory cell array 1 side is accessed by the decoder 4 when the MSB is "1", while the memory cell array 2 side is accessed when the MSB is "1". It is accessed by the decoder 5 when the MSB is "0". Both data lines of the memory cell array 1.2 are connected to the sense amplifier 3. When one memory cell array starts reading, a dummy selector circuit 8.9 and a dummy cell circuit 10.9 having a structure described later are used to apply a reference voltage (reference voltage Vref) to the data line connected to the other memory cell array. 11 connects. The MSB is input to the dummy selector circuit 8.9, and when the MSB is "0", the dummy selector circuit 8 is selected, and conversely, when the MSB is "1", the dummy selector circuit 9 is selected. Each line is connected to a sense amplifier 3 to set the potential of the data line.
Bias circuit for making the potential easily amplified by 6.
7 is formed.

The structure of the memory cell array 1.2 will be explained with reference to FIG. 3. The data line 21 has two column selection gates 1-22.2 arranged in series. 23 are formed, and gate electrodes Y1 to Y1 of these column selection gates 22 and 23 are formed.
Y8. A column selection signal is supplied to YOI-YO8. A focus line 24 is connected to each column selection gate 23 . The bit lines 24 are connected to a memory cell block 2 consisting of two series-connected MOS transistor groups.
A plurality of each number 5 are connected. Memory cell block 25
Among the MOS transistors connected in series, the MOS transistors selected by the selection lines Xi and X2 are arranged so that the enhancement type and depletion type are different selection lines between the two columns. There is a function to select one of the two. Also, the word line XO is connected in series.
Other MOS transistors selected as I to X08 store data. The memory of this data is "1" (or "'0") if the MOS' transistor involved in selecting the word line is an enhancement type, and "O" (or "1") if it is a depletion type. Here,
Enhancement type M of these memory cell arrays l and 2
The threshold voltage v of the O3 transistor is set higher than the threshold voltage v of the enhancement type MOS transistor in the peripheral circuit. In this way, by increasing the threshold voltage V by the memory cell array, it becomes possible to suppress the through current, as will be described later. In order to increase the threshold voltage of only the memory cell array 12, the threshold voltage V can be adjusted by selectively implanting ions using a mask, for example.

Next, the bias circuit will be explained with reference to FIG. pMO3 to which chip enable signal CE is input
The output of the inverter consisting of the transistor 41 and the nMOS transistor 42 is supplied to the drain of the nMOS transistor 43 and the gates of the nMOS transistors 44 and 46.

The source of the nMOS transistor 43 is connected to the ground voltage GND, and its gate is connected to the data line.

nMOS transistor 44 is nMOS transistor 45
The nMOS transistor 45 is connected in series between the t source voltage Vcc and the ground voltage GND, and the power supply voltage Vcc is supplied to the gate of the nMOS transistor 45. In this bias circuit, n
Since the MOS transistor 43 functions as part of the feedback loop, the potential of the data line is stabilized. When the signal Φ is at a high level, the potential of the data line is approximately 1.
It is biased to about 5V. A precharge function using the signal Φ is added to this. Signal Φ is PMOS transistor 4
When the signal Φ becomes low level, the potential of the data line is raised to about 2V via the nMOS transistor 46. the result,
The sensitivity of the sense amplifier can be increased.

Next, the configurations of the dummy selector circuit and the dummy cell circuit will be explained with reference to FIGS. 5 and 6.

The dummy selector circuit and the dummy cell circuit are circuits for making the data line connected to the non-selected memory cell array reach the reference voltage Vref after precharging. Here, to explain the reference voltage V ref, first,
The combination in which the ability to lower the voltage by a plurality of series-connected MOS transistors in a memory cell block is the smallest is when the MOS transistor involved in selection is a depletion type, and all the others are enhancement types. Therefore, by configuring the dummy selector circuit and the dummy cell circuit so as to have the ability to lower half the voltage of the combination, it is possible to distinguish whether the selected MOS transistor is an enhancement type or a depletion type.

Specifically, the dummy selector circuit includes four enhancement type MOSs connected in series, as shown in FIG.
It is composed of transistors 51 to 54. M.O.S.
A signal MSB (MSB) is supplied to the transistor 51, and this MOS transistor 51 functions as a switch.

MOS) transistors 52 to 54 have power supply voltage Vc on their gates.
c is supplied.

These MOS transistors 51 to 54 are column selection gates)
It corresponds to twice the configuration of 22.23. The series-connected terminals of the 51 MOS transistors are connected to a data line on the dummy side. Further, the terminal on the MOS transistor 54 side is connected to a dummy cell circuit.

Further, as shown in FIG. 6, the dummy cell circuit has twice as many elements as one memory cell block (see FIG. 8), and includes four depletion type MO3 transistors RO1 and Although not shown here, it consists of 16 enhancement type MO3 transistors 2. The gate voltage of the depletion type MOS transistor 61 is the ground voltage CH
D, enhancement type MO5 transistor Ro 2
gate voltage and power supply voltage Vcc. Therefore, all the transistors are in the on state, and the potential of the dummy data line is set to a level that is half the level at which the voltage drops to the minimum and the level at which the voltage does not drop at all.
It is possible to make the voltage Vrer. A terminal 63 of the dummy cell circuit is connected to the dummy selector circuit. Therefore, the dummy cell circuit is connected to the data line via the dummy selector circuit.

In the read-only memory having the above configuration, the threshold voltage Vth of the enhancement type MOS transistors of the memory cell arrays 1 and 2 is higher than that of the enhancement type MOS transistor of the peripheral circuit.
Since the threshold voltage of the S transistor is made higher than the threshold voltage ■l,
When the enhancement type MOS transistor is selected, the transistor is turned off early, making it possible to suppress the through current.

FIG. 1 shows depletion-type MOs that constitute memory cell blocks in a read-only memory according to this embodiment.
) After selecting Ranjisk, enhancement type MOS
It is a waveform diagram when a transistor is selected. First, if it is assumed that among the MOS transistors forming the memory cell, for example, a depletion type MOS transistor is selected for the word line XO8, the potential of the word line XO8 is the ground voltage GND. Also, non-i! The potential of the other selected word lines X0I-XO7 is the power supply voltage Vcc. Then, at time t, the signal Φ from the address transition detection circuit etc. changes from the voltage Vcc to the ground voltage GN.
Changes to D. Then, the bias circuits 6 and 7 are activated, and the potential of the data line (focus line) is raised from approximately 1.5V to 2V. Here, following the depletion type MOS transistor, for example, a word line XOI
If the enhancement type Mo3L transistor is selected, the word line X serving as its gate electrode is selected.
The potential of OI will fall from power supply voltage Vcc to ground voltage GND.

The enhancement type Mo3! - The transistor is on when the gate voltage is close to the power supply voltage Vcc, but changes to the off state when it approaches the threshold voltage Vth (EM). In particular, in the read-only memory of this embodiment, the threshold voltage (a voltage (EM)) is a quotient compared to the threshold voltage (tk (E)) of the enhancement type MOS transistor in the peripheral circuit, and therefore, the gate voltage is The enhancement type MOS transistor of the memory cell involved in selection is turned off at an early stage on the way down (for example, time t2).In this way, the Mo3 transistor is turned off at an early stage, so the time during which the through current flows is shortened. Therefore, the time (for example, time ta) during which data is determined by the bit lines BIT and BIT becomes faster.

By the way, as mentioned above, the threshold voltage Vt of the enhancement type MOS transistor of the memory cell array 1.2
By raising b (EM) higher than the threshold voltage (E) of the Mo5 transistor in the peripheral circuit, it is possible to suppress the through current and increase the speed. If you do this, on the other hand, when you access the debrisigon type MO3 transistor,
The time it takes for the enhancement type MO3 transistor to turn on becomes longer. For this reason, - as an example, the seventh
By setting the threshold voltage (EM) as shown in the figure, it is possible to speed up the entire read operation.

Figure 7C: Enhancement type MO of memory cell array
This shows the change in access time between enhancement type MOS transistor access (curve E) and depletion type MOS transistor access (curve D) when the threshold voltage (EM) of the S transistor is increased. It is a diagram.

Following the curve, the access time can be shortened by increasing the threshold voltage (EM).

However, in the same memory cell array, by increasing the threshold voltage (EM), the resistance bone in the enhancement type MOS transistor increases as shown by the curve, and the access time of the depletion type MOS transistor increases. . Therefore, the threshold voltage VL of the enhancement type MO3 transistor of the memory cell array is set to the threshold voltage VLkX that minimizes the difference in time between the access time of the enhancement type MO3 transistor and the access time of the Divry Silane type MOS transistor.
By setting h(EM), balanced readout will be achieved.

In the read-only memory of this embodiment, the peripheral circuits include a sense amplifier, a decoder, an input/output cover sofa,
Refers to various other circuits. Furthermore, although the MOS transistors in which the threshold voltage Vth is a problem are n-type MOS transistors, they may be of opposite conductivity type.

〔Effect of the invention〕

In the read-only memory of the present invention, the threshold voltage of the enhancement-type MIS (MOS) transistor in the memory cell array is set higher than the threshold voltage of the enhancement-type MIS transistor in the peripheral circuit, as described above. When a transistor is selected, it is possible to turn off the transistor at an early stage, thereby suppressing the through current and speeding up the readout. Further, by optimizing the threshold voltage, a balanced read operation is also possible.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram for explaining the read operation of an example of the read-only memory of the present invention, FIG. 2 is a block diagram showing a bronch configuration of the example, and FIG. 3 is a diagram showing the configuration of a memory cell array of the example. 4 is a circuit diagram showing the configuration of a bias circuit as an example, FIG. 5 is a circuit diagram showing the configuration of a dummy selector circuit as an example, and FIG. 6 is a circuit diagram showing the configuration of a dummy cell circuit as an example. Figure 7 shows the threshold voltage of the enhancement type MOS transistor ■tk(
EM) and access time, Figure 8 is a circuit diagram of a memory cell block of a general read-only memory, and Figure 9 is a waveform diagram to explain problems with conventional read-only memory. be. 1.2...Memory cell array 3...Sense amplifier 4.5...Decoder 6.7...Bias circuit 8.9...Dummy selector circuit 10.11...Dummy cell circuit

Claims (1)

[Claims] In a read-only memory in which a memory cell array is configured by a plurality of MIS transistors connected in series, and data is stored by a combination of depletion type and enhancement type MIS transistors, the memory cells are configured. A read-only memory in which the threshold voltage of an enhancement-type MIS transistor is set higher than the threshold voltage of an MIS transistor constituting a peripheral circuit.