JPH02128399A - Eprom type nonvolatile memory - Google Patents
Eprom type nonvolatile memoryInfo
- Publication number
- JPH02128399A JPH02128399A JP63283339A JP28333988A JPH02128399A JP H02128399 A JPH02128399 A JP H02128399A JP 63283339 A JP63283339 A JP 63283339A JP 28333988 A JP28333988 A JP 28333988A JP H02128399 A JPH02128399 A JP H02128399A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- floating gate
- oxide film
- floating
- control gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、EPROM型不揮発性メモリーに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an EPROM type non-volatile memory.
従来、プログラムデータを電気的に書込、光学的に消去
可能な、いわゆるEPROM型不揮発性メモリー集積回
路(以後EPROMと称す)において、電荷を蓄積する
浮遊ゲートに光照射を行い、光励起により浮遊ゲートに
蓄積された電荷を放出させ、プログラムデータを消去し
ていた。Conventionally, in a so-called EPROM type nonvolatile memory integrated circuit (hereinafter referred to as EPROM) in which program data can be electrically written and optically erased, a floating gate that stores charge is irradiated with light, and the floating gate is activated by light excitation. The stored charge was released and the program data was erased.
第3図は従来のEPROMの一例の断面図である。FIG. 3 is a sectional view of an example of a conventional EPROM.
シリコン基板1の主表面上に比較的厚い0.5〜1.0
μm程度のフィールド酸化膜2を形成し、メモリー素子
を形成する領域に比較的薄い10nm程度の第1のゲー
ト酸化膜3を形成する。A relatively thick layer of 0.5 to 1.0 mm is formed on the main surface of the silicon substrate 1.
A field oxide film 2 with a thickness of about μm is formed, and a relatively thin first gate oxide film 3 of about 10 nm is formed in a region where a memory element is to be formed.
この上に多結晶シリコン層よりなる浮遊ゲート4を形成
する0次いで、第2のゲート酸化膜5を形成後、多結晶
シリコン層よりなる制御ゲート8を形成する。A floating gate 4 made of a polycrystalline silicon layer is formed thereon. Next, a second gate oxide film 5 is formed, and then a control gate 8 made of a polycrystalline silicon layer is formed.
データの消去は、上部より紫外線を照射し、浮遊ゲート
3に蓄積されていた電荷を光励起し、シリコン基板1及
び制御ゲート8へ電荷を放出することにより行なわれる
。Erasing data is performed by irradiating ultraviolet rays from above, photo-exciting the charges accumulated in the floating gate 3, and releasing the charges to the silicon substrate 1 and the control gate 8.
しかしながら、従来の構造では、プログラムデータ消去
のための光照射しても浮遊ゲートに直接光が入射せず、
シリコン基板からの反射光を利用していたため、消去効
率が良好でないという問題がある。However, in the conventional structure, even when light is irradiated to erase program data, the light does not directly enter the floating gate.
Since the method uses reflected light from the silicon substrate, there is a problem in that the erasing efficiency is not good.
本発明のEPROM型不揮発性メモリーは、半導体基板
の一重部に設けられたソース領域及びドレイン領域と、
前記ソース領域とドレイン領域との間の前記半導体基板
表面に第1のゲート絶縁膜を介して設けられた浮遊ゲー
トと、前記浮遊ゲトの上に第2のゲート絶縁膜を介して
設けられた制御ゲートを有するEPROM型不揮発性メ
モリーにおいて、前記浮遊ゲートに紫外線を入射させる
ための開孔を前記制御ゲートに設けるか、または前記制
御ゲートを紫外線透過性導電性材料で構成したことを特
徴とする。The EPROM type nonvolatile memory of the present invention includes a source region and a drain region provided in a single portion of a semiconductor substrate;
A floating gate provided on the surface of the semiconductor substrate between the source region and the drain region via a first gate insulating film, and a control provided on the floating gate via a second gate insulating film. The EPROM type nonvolatile memory having a gate is characterized in that the control gate is provided with an opening for allowing ultraviolet light to enter the floating gate, or the control gate is made of a conductive material that transmits ultraviolet light.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
シリコン基板1の主表面上に比較的厚い0.5〜1.0
ノzm程度のフィールド酸化膜2を形成し、メモリー素
子を形成する領域に比較的薄い10nm程度の第1のゲ
ート酸化膜3を形成する。A relatively thick layer of 0.5 to 1.0 mm is formed on the main surface of the silicon substrate 1.
A field oxide film 2 with a thickness of about 10 nm is formed, and a relatively thin first gate oxide film 3 of about 10 nm is formed in a region where a memory element is to be formed.
この上に多結晶シリコン層よりなる浮遊ゲート4を形成
する。次いで、第2のゲート酸化膜5を形成後、多結晶
シリコン層よりなる制御ゲート6を浮遊ゲート4が露出
するように形成する。つまり、消去制御ゲート6は浮遊
ゲート4の全面を覆わないようにする。A floating gate 4 made of a polycrystalline silicon layer is formed on this. Next, after forming the second gate oxide film 5, a control gate 6 made of a polycrystalline silicon layer is formed so that the floating gate 4 is exposed. In other words, the erase control gate 6 is made not to cover the entire surface of the floating gate 4.
このような構造にすることにより、消去用の紫外線は薄
い第2のゲート酸化JL%5を通して浮遊ゲート4に入
射するので、浮遊ゲートから電荷を放出しやすくなり、
消去効率を大幅に改善することができる。With this structure, the ultraviolet rays for erasing enter the floating gate 4 through the thin second gate oxide JL%5, making it easier to release charges from the floating gate.
Erasing efficiency can be significantly improved.
第2図は本発明の第2の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
この実施例においては、紫外線が浮遊ゲート4に到達し
やすいように、制御ゲート7を透明導電性膜で形成して
いる。透明導電性材料としては、例えばIn2O3とS
nO□との混合物が選ばれる。In this embodiment, the control gate 7 is formed of a transparent conductive film so that ultraviolet rays can easily reach the floating gate 4. Examples of transparent conductive materials include In2O3 and S
A mixture with nO□ is chosen.
このように、制御ゲートを透明導電性材料で形成すると
、紫外線が浮遊ゲートに到着するので、浮遊ゲートから
電荷を放出しやすくなり、消去効率を大幅に改善するこ
とができる。従って、浮遊ゲート4の全面を覆うように
制御ゲート7を設けることができ、第1の実施例のよう
に、制御ゲートの一部を削除して浮遊ゲートを露出させ
る必要はない。When the control gate is formed of a transparent conductive material in this manner, ultraviolet rays reach the floating gate, making it easier to release charges from the floating gate, and erasing efficiency can be greatly improved. Therefore, the control gate 7 can be provided so as to cover the entire surface of the floating gate 4, and there is no need to remove a part of the control gate to expose the floating gate as in the first embodiment.
以上説明したように、本発明は、制御ゲートの一部を削
除して浮遊ゲートを露出させるか、あるいは制御ゲート
を透明導電膜で形成するかのいづれかによって浮遊ゲー
トに紫外線が到達しやすいようにしたので、浮遊ゲート
からの電荷放出が容易になり、消去光率が向上するとい
う効果を有する。As explained above, the present invention makes it easier for ultraviolet rays to reach the floating gate by either removing a part of the control gate to expose the floating gate or forming the control gate with a transparent conductive film. Therefore, the discharge of charges from the floating gate becomes easy, and the erase light rate is improved.
第1図は本発明の第1の実施例の断面図、第2図は本発
明の第2の実施例の断面図、第3図は従来のEPROM
の一例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIG. 3 is a conventional EPROM.
It is a sectional view of an example.
Claims (1)
ン領域と、前記ソース領域とドレイン領域との間の前記
半導体基板表面に第1のゲート絶縁膜を介して設けられ
た浮遊ゲート、と、前記浮遊ゲトの上に第2のゲート絶
縁膜を介して設けられた制御ゲートを有するEPROM
型不揮発性メモリーにおいて、前記浮遊ゲートに紫外線
を入射させるための開孔を前記制御ゲートに設けるか、
または前記制御ゲートを紫外線透過性導電性材料で構成
したことを特徴とするEPROM型不揮発性メモリー。a source region and a drain region provided on one main surface of a semiconductor substrate; a floating gate provided on the surface of the semiconductor substrate between the source region and the drain region via a first gate insulating film; EPROM having a control gate provided above a floating gate via a second gate insulating film
type nonvolatile memory, the control gate is provided with an opening for allowing ultraviolet rays to enter the floating gate;
Alternatively, an EPROM type nonvolatile memory characterized in that the control gate is made of an ultraviolet-transparent conductive material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63283339A JPH02128399A (en) | 1988-11-08 | 1988-11-08 | Eprom type nonvolatile memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63283339A JPH02128399A (en) | 1988-11-08 | 1988-11-08 | Eprom type nonvolatile memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02128399A true JPH02128399A (en) | 1990-05-16 |
Family
ID=17664201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63283339A Pending JPH02128399A (en) | 1988-11-08 | 1988-11-08 | Eprom type nonvolatile memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02128399A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011139052A (en) * | 2009-12-04 | 2011-07-14 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
-
1988
- 1988-11-08 JP JP63283339A patent/JPH02128399A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011139052A (en) * | 2009-12-04 | 2011-07-14 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device |
US9153338B2 (en) | 2009-12-04 | 2015-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
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