JPH02127012U - - Google Patents

Info

Publication number
JPH02127012U
JPH02127012U JP3518989U JP3518989U JPH02127012U JP H02127012 U JPH02127012 U JP H02127012U JP 3518989 U JP3518989 U JP 3518989U JP 3518989 U JP3518989 U JP 3518989U JP H02127012 U JPH02127012 U JP H02127012U
Authority
JP
Japan
Prior art keywords
magnetic material
multilayer chip
chip inductor
external electrodes
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3518989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3518989U priority Critical patent/JPH02127012U/ja
Publication of JPH02127012U publication Critical patent/JPH02127012U/ja
Pending legal-status Critical Current

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  • Coils Or Transformers For Communication (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この考案の一実施例に係る積層チツ
プインダクタを示す平面図である。第2図は、第
1図の線−に沿う断面図である。第3図は、
従来の積層チツプインダクタの一例を示す斜視図
である。第4図は、インダクタの周波数とインピ
ーダンスとの関係の例を示す図である。第5図は
、LRの並列回路を示す等価回路図である。 12…磁性体、14…導体、16…積層体、1
8…外部電極。
FIG. 1 is a plan view showing a multilayer chip inductor according to an embodiment of this invention. FIG. 2 is a sectional view taken along line - in FIG. 1. Figure 3 shows
FIG. 2 is a perspective view showing an example of a conventional multilayer chip inductor. FIG. 4 is a diagram showing an example of the relationship between the frequency and impedance of an inductor. FIG. 5 is an equivalent circuit diagram showing a parallel circuit of LR. 12...Magnetic material, 14...Conductor, 16...Laminated body, 1
8...External electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 磁性体中にコイルを形成する導体が積層されて
成る積層体の両端部に、内部のコイルの両端にそ
れぞれ電気的につながる外部電極を設けた構造の
積層チツプインダクタにおいて、前記磁性体に導
電率の高いものを用い、それによつて当該磁性体
自身の外部電極間の抵抗値が10Ωないし10K
Ωの範囲内になるようにしたことを特徴とする積
層チツプインダクタ。
A multilayer chip inductor has a structure in which external electrodes electrically connected to both ends of an internal coil are provided at both ends of a laminate in which a conductor forming a coil is laminated in a magnetic material. The resistance value between the external electrodes of the magnetic material itself is 10Ω to 10K.
A multilayer chip inductor characterized in that it is within the range of Ω.
JP3518989U 1989-03-28 1989-03-28 Pending JPH02127012U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3518989U JPH02127012U (en) 1989-03-28 1989-03-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3518989U JPH02127012U (en) 1989-03-28 1989-03-28

Publications (1)

Publication Number Publication Date
JPH02127012U true JPH02127012U (en) 1990-10-19

Family

ID=31540330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3518989U Pending JPH02127012U (en) 1989-03-28 1989-03-28

Country Status (1)

Country Link
JP (1) JPH02127012U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122505A (en) * 1988-10-31 1990-05-10 Taiyo Yuden Co Ltd Manufacture of laminated chip inductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122505A (en) * 1988-10-31 1990-05-10 Taiyo Yuden Co Ltd Manufacture of laminated chip inductor

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