JPH02125516A - Switching circuit - Google Patents

Abstract

PURPOSE:To prevent production of an insertion loss by using an amplifier FET as a switch circuit. CONSTITUTION:A signal inputted from input terminals 1, 2 is switched by a switching voltage fed to terminals 27, 26 and any signal is outputted from an output terminal 25. With a control voltage at the terminal 27 kept to a high level and a control voltage at the terminal 26 kept to a low level, a FET 3 as a source input amplifier connecting to the input terminal 1 and a FET 7 as a gate input amplifier are turned on, the source input amplifier FET 4 and the gate input amplifier FET 8 connecting to the input terminal 2 are turned off and a signal inputted from the input terminal 1 is amplified and outputted from the output terminal 25 via a source follower FET 19.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a switching circuit using FETs (field effect transistors), and more specifically,
A switching circuit for an IC-based receiving circuit, that is, the first
, selects one of the signals input from the second two input terminals by a combination of high and low voltages applied to the first and second voltage control terminals, and outputs the selected signal from the output terminal. It relates to switching circuits.

An example of such a receiving circuit is, for example, 2 for satellite broadcasting.
If a different type of broadcast is made and received by two antennas, a receiving circuit can be considered that can selectively switch and receive either of the broadcasts using one receiving circuit. It can be suitably used for receiving circuits.

[Conventional technology]

Conventional switch circuits using FETs (field effect transistors) perform switching by controlling the gate voltage and changing the resistance value between the drain and source, as seen in Japanese Patent Application Laid-Open No. 59-80974. something is known.

[Problem to be solved by the invention]

Since such conventional switch circuits do not use FETs as active devices with amplification,
Even when the ET is turned on, on-resistance remains, causing a problem in signal loss.

In addition, by combining several conventional switch circuits, two-man power, l
When configuring an output switching circuit (switching circuit),
When the FET switch circuit constituting one input system was turned off, the impedance in the off state suddenly increased to a large value, causing reflection of the input signal waveform and adversely affecting other circuits. In other words, it is desired that the impedance of the switch circuit when it is in the off state is large enough to turn off the input signal waveform without causing any reflection.

Furthermore, in such a two-manpower, one-output switching circuit, there is good isolation between one input system and the other input system (that is, when one input system is on and the other is off,
Although it is desired that signals do not leak from the on input system to the off system, such good characteristics cannot be expected if conventional switch circuits are used as they are.

An object of the present invention is to realize a switch circuit that has no signal loss in the OFF state by functioning as an active device, and to realize a switching circuit that uses such a switch circuit as a two-man power, one-output switching circuit (switching circuit) in the OFF state. It is an object of the present invention to provide a switching circuit which does not cause reflection of an input signal waveform when the input signal waveform becomes low and has good isolation between both input systems.

[Means to solve the problem]

The above purpose uses an amplification FET as a switch circuit,
And the amplification FET is a source input method, or a dummy FET is connected in parallel, and the FE that configures the input system
This is achieved by applying a reverse bias between the gate and drain of the FET when the FET is off.

[Effect]

Since the amplifying FET is used as a switch circuit, the FET as a switch circuit has a gain, and therefore no insertion loss occurs as in the conventional case.

In addition, if the FET is made into a source input type, a resistor can be connected in parallel to the source terminal, and even if the FET is turned off, the impedance of the switch circuit made up of the FET will be extremely large, like infinite. Since it does not become large, there is no reflection of the input signal. Dummy FE
Even if you connect T in parallel to the FET switch and turn off the dummy FET when the FET switch is turned on, and turn on the dummy FET when the FET switch is turned off, the impedance of the FET switch circuit when it is off. can be prevented from becoming extremely large, and reflection of the input signal can be prevented.

The FET between the gate and drain of the FET that makes up the input system
By applying a reverse bias (the drain voltage is higher than the gate voltage) when the ET is off, the capacitance between the gate and drain becomes extremely small, which is useful for isolation from other circuits.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This embodiment can be used, for example, as an input switching circuit in the input section of a BS tuner of a satellite broadcasting receiver.

This means that when two types of satellite broadcasting are being performed and the signals are received using two antennas, the signals from the two antennas are guided to input terminals 1 and 2, respectively, and the voltage applied to control voltage terminals 27 and 26 is applied. This is a switching circuit that outputs one of two signals to the output terminal 25 and receives it based on a combination of high and low signals.

In the switching circuit shown in Figure 1, the important point is that FET 3 connected to input terminal 1 adopts the source input method, and resistor 5 is connected in parallel (FET 4
(The same applies to
T8 is reverse biased, FET7 is off and FET8 is
The point is that when FET 7 is on, a reverse bias is applied to FET 7. It goes without saying that each FET is also an amplification FET.

The circuit operation will be explained below. Signals input from input terminals 1 and 2 are switched by switching voltages applied to terminals 27 and 26, and either signal is output from output terminal 25.

Now, the terminal 270 control voltage is set to High level, and the terminal 26
When the control voltage of is set to Low level, FET 3 as a source input amplifier connected to input terminal 1 and FET 7 as a gate input amplifier are turned ON, and FET 4 for source input amplifier and FET 7 as a gate input amplifier connected to input terminal 2 are turned on. FET8 is turned off, and the signal input from input terminal I is amplified and output from output terminal 25 via source follower FE719.

On the other hand, the control voltage level of terminal 27 is set to Low, and terminal 2
6 is set to High, FET3 as a source input amplifier connected to input terminal 1, FET7 as a gate input amplifier connected to input terminal 1 is 0FFL, FET4 as a source input amplifier connected to input terminal 2, and FET8 as a gate input amplifier are 0FFL. The signal from the input terminal 2 is output from the output terminal 25.

Here, the control voltage of the drain D of FET3 and the gate G of FET7 is supplied from the terminal 27 via the resistor 9 and the diode 11 (or more than one), and the control voltage of the drain D of FET7 is also supplied from the resistor 13 and the diode 15. (?j!
It is supplied from the terminal 27 via the
The control voltage of the drain D of FET4 and the gate G of FET8 is controlled by a resistor 10 and a diode 12 (or more than one).
is supplied from the terminal 26 via the drain D of FET8.
The voltage of the resistor 14 and diode 16 (more than one is fine)
The drain bias of FET 19 is supplied from terminal 26 via terminal 26.27 to diode 21.20.
Supplied via. The FET 19 is configured such that a DC bias is always applied regardless of whether the terminals 26 and 27 are at High or Low level.

The feature of this embodiment is that, as mentioned earlier, the signal from the input terminal 1 and the signal from the input terminal 2 are combined at the gate side of the FET 19 whose output is a source follower. is on and FET8 is off, FET8
is reverse biased, the capacitance between the gate and drain of FET8 is reduced, and the signal leaking from the FET7 side to the FETB side is reduced (the opposite is true when FET7 is off and FET8 is on), and input terminals 1 and 2 are There is sufficient isolation between the two. In addition, amplification FET
Since it is used as a switch, there is no loss, and since it is a source input type switch (3, 4), the resistance (5, 6)
) can be connected, and an appropriate input impedance exists even when it is off, so there is no reflection of the input signal and there is no adverse effect on other circuits.

FIG. 2 shows a second embodiment of the invention. In the same figure,
Signals input from input terminals 1 and 2 are input to terminals 27.
Switching is performed by the switching voltage applied to 26, and one of the signals is output from the output terminal 25.

Now, the control voltage of terminal 27 is set to High level, and the control voltage of terminal 26 is set to High level.
When the control voltage of is set to Low level, FET3 as a source input amplifier connected to input terminal 1, FET7 as a gate input amplifier, and source follower FET2 are connected to input terminal 1.
8 is ONL, source input amplifier FET 4, gate input amplifier FET 8 and source follower FET 29 connected to input terminal 2 are 0FFL, and the signal input from input terminal 1 is amplified and sent to output terminal 25 via source follower FE728. It is output from

On the other hand, when the control voltage level of the terminal 27 is set to Low and the terminal 26 is set to High, the FET3 as a source input amplifier connected to the input terminal 1, the FET7 as a human power amplifier connected to the input terminal 1, and the source follower FET28 are set to 0FFL,
FE as source input amplifier connected to input terminal 2
T4, the FET8 as a gate input amplifier, and the source follower FET29 are ONL, and the signal from the input terminal 2 is outputted from the output terminal 25.

Here, the control voltage of the drain D of FET3 and the gate G of FET7 is supplied from the terminal 27 via the resistor 9 and the diode l (multiple diodes may be used), and the control voltage of the drain of FET7 is also supplied via the resistor 13. The control voltage of the drain D of FET4 and the gate G of FET8 is supplied from the terminal 26 via the resistor lO and the diode 12 (or more than one), and the voltage of the drain of FET8 is also supplied from the resistor 14. The drain bias of FET 28 is supplied from terminal 26 via terminal 27,
Drain bias of ET29 is supplied from terminal 26, respectively.

The feature of this embodiment is that the output is a source follower FET.
Since the signal from input terminal 1 and the signal from input terminal 2 are combined at the point on each source S side of 28.29, the isolation between input terminals 1 and 2 is better than in the first embodiment. There is enough available. Furthermore, since the amplifying FET is used as a switch, there is no loss, and since the resistor is connected to the source input type switch, the input impedance when turned off is appropriate, and no reflected waves are generated.

To add an explanation here, it is the same as mentioned earlier, but for example, if FET 3°7.28 of the terminal 1 system is set to 0F
Fj, between the source and gate of FET28, FET7
Since a reverse bias is applied between the source and gate of FET 3, sufficient signal isolation can be achieved.

FIG. 3 shows a third embodiment of the present invention. Figure 3 shows the first
In the first embodiment shown in the figure, the source of FET7 and the source of FET8
This corresponds to the second output terminal 30 taken out from the common connection point M with the source. For example, the signals input from terminals 1.2 are a satellite broadcast signal (hereinafter abbreviated as BS signal) and a terrestrial TV signal (normal VHF, UHF signal).
, the terminal 25 receives a BS signal (900 to 800
MH2) receiver is connected, and the TV signal (MH2) is connected to the terminal 30.
0-80MHz) receiver.

The feature of this embodiment is that a TV signal without attenuation can be obtained from the terminal 30 by selecting the capacitor 18 at a value that provides low impedance in the BS signal band and taking out the TV signal from the terminal 30. Also, FET7, FET
8 operates as a source follower for the TV signal obtained from the terminal 30, so a stable TV signal with no gain and no attenuation or gain is obtained from the output terminal 30.

FIG. 4 shows a fourth embodiment of the present invention. Figure 4 shows the second
In the second embodiment shown in the figure, the source of FET7 and the FET
This corresponds to the second output terminal 30 taken out from the common connection point M with the source of No. 8. For example, the signals input from terminals 1 and 2 are satellite broadcast signals (BS signals) and T
When the signal is a V signal, a BS receiver is connected to the terminal 25, and a TV receiver is connected to the terminal 30.

The features of this embodiment are the same as those described for the embodiment shown in FIG. 3, so they will not be repeated.

FIG. 5 shows a fifth embodiment of the present invention. This is the first embodiment shown in FIG.
Connect the gate G of T31 and connect F to the drain D of FET4.
Connect the gate G of ET32, make the source S of FET31 and 32 common, and use this source S as the output terminal 30,
The drain D of FET31 is connected to terminal 27, and FET3
The drain D of No. 2 corresponds to that connected to the terminal 26.

For example, when the signals input from terminals 1 and 2 are a BS signal and a TV signal, a BS receiver is connected to terminal 25 and a TV receiver is connected to terminal 30.

The feature of this embodiment is that since the FETs 31 and 32 are used as source followers, there is no gain or attenuation, and the terminal 30
This is where you can get a more stable TV signal. Also FE
T31 and T32 are also used as switching FETs, and are configured to be switched by the voltage at terminals 26 and 27.

FIG. 6 shows a sixth embodiment of the present invention. This is the second embodiment shown in FIG.
Connect the gate of FET31 and connect the gate of FET3 to the drain of FET4.
2, the sources of FETs 31 and 32 are common, this source is used as the output terminal 30, the drain D of FET 31 is connected to terminal 27, and the drain D of FET 32 is connected to terminal 26. There is.

For example, when the signals input from terminal 1.2 are a BS signal and a TV signal, a BS receiver is connected to terminal 25, and a TV receiver is connected to terminal 30.

The feature of this embodiment is that since the FETs 31 and 32 are used as source followers, there is no gain or attenuation, and the terminal 30
This is where you can get a more stable TV signal. Also FE
T31 and T32 are also used as switching FETs, and are configured to be switched by the voltage at the terminal 2627.

Other effects are similar to those of the second embodiment shown in FIG.

FIG. 7 shows a seventh embodiment of the present invention. This has the effect of stabilizing the input impedance (so as not to suddenly increase the input impedance during off-state and cause reflection of the input signal) in addition to the first embodiment shown in FIG.
This corresponds to the effect that the input impedance is set to an appropriate size even when the OFF state is turned off, and the previously mentioned effect of preventing reflection of the input signal is strengthened. Connect the source of
The gate of the FET 34 is grounded, and the drain D is connected to the control voltage terminal 26 via a resistor 37. Further, the source S of the FET 35 (dummy FET) is connected to the source S of the FET 4, the gate G of the FET 35 is grounded, and the drain D is connected to the control voltage terminal 27 via the resistor 36.

The operating principle of this embodiment will be explained. When receiving a signal input from terminal l, set terminal 27 to High and terminal 26 to
Set to Low level and turn on FET3゜7.19.35
, turns off FET4, 8.34.

At this time, since the FE'r35 connected to the terminal 2 is turned on, the input impedance from the terminal 2 is stabilized. In other words, the FET 35 operates as a dummy FET for impedance stabilization.

Conversely, when receiving a signal input from terminal 2, terminal 27 is set to Low level, terminal 26 is set to High level, and the FET
3, 7.35 OFF, FET4゜8.19.34 OFF
Do N. At this time, FET34 connected to terminal 1 is turned on.
Therefore, the input impedance from terminal 2 is stabilized.

As described above, the feature of this embodiment is that the input impedance of the turned-off terminal is stabilized. The other effects are similar to those of the first embodiment shown in FIG. 1, and an eighth embodiment is shown in FIG. This is the second embodiment shown in FIG. 2 with an even stronger input impedance stabilization effect, and the FET34 is connected to the source of the FET3.
The gate of the FET 34 is grounded, and the drain of the FET 34 is connected to the control voltage terminal 26 via a resistor 37.

Further, the source of FET 35 is connected to the source of FET 4 , the gate of FET 35 is grounded, and the drain is connected to control voltage terminal 27 via resistor 36 .

The operating principle of this embodiment will be explained. When receiving a signal input from terminal l, set terminal 27 to High and terminal 26 to
Set to Low level and turn on FET3゜7.19.35
, turns off FET4, 8.34. At this time, since the FET 35 connected to the terminal 2 is turned on, the input impedance from the terminal 2 is stabilized. In other words, FE
T35 is operating as an impedance stabilizing gummy-FET.

Conversely, when receiving a signal input from terminal 2, terminal 27 is set to Low level, terminal 26 is set to High level, and the FET
3, 7.35 OFF, FET4゜8.19.34 OFF
Do N. At this time, FET34 connected to terminal 1 is turned on.
Therefore, the input impedance from terminal 2 is stabilized.

As described above, the feature of this embodiment is that the input impedance of the turned-off terminal is stabilized. Other effects are similar to those of the second embodiment shown in FIG.

FIG. 9 shows a ninth embodiment of the present invention. This provides the effect of stabilizing the input impedance in addition to the first embodiment shown in FIG. 1.

The drain D of FET3 and the drain D of FET4 are connected through a resistor 9.10, respectively, and the connection point is connected to a control voltage terminal 27 through a diode 38.39, respectively.
．． 26.

In this embodiment, which of the terminals 27 and 26 is High?
The feature is that the input impedance is stabilized by keeping FET 3°4 in the ON state at all times, whether at high or low level. Other features are similar to those of the first embodiment.

FIG. 10 shows a tenth embodiment of the present invention. This is the second
This embodiment has the effect of stabilizing the input impedance in addition to the second embodiment shown in the figure. The drain D of FET3 and the drain D of FET4 are connected to resistors 9 and 10, respectively.
The connection point is the diode 38.39
are connected to control voltage terminals 27 and 26, respectively.

In this embodiment, which of the terminals 27 and 26 is High?
The feature is that the input impedance is stabilized by keeping FET 3°4 in the ON state at all times, whether at high or low level. Other features are similar to those of the second embodiment shown in FIG.

FIG. 11 shows an eleventh embodiment of the present invention, BS antenna and converter 40 and BS antenna and converter 4.
The two BS signals received at 1 are respectively input to the input terminals 1.2 of the switching circuit 42 according to the present invention,
Either one of them is output to the output terminal 25, and from there B
It is input to the S tuner 43, and is further input to the TV receiver circuit 44.
is input.

The broken line 45 indicates the TV receiver as a whole, and the feature of this embodiment is that the TV receiver has two BS receiving terminals.

In this embodiment, the block 44 is a VTR circuit, and the broken line 45 is a VTR (video tape recorder), which may be a VTR equipped with two BS input terminals. , V.H.
A configuration may be adopted in which only the F signal is branched and output.

FIG. 12 shows a twelfth embodiment of the present invention. This uses a switching circuit for the 21st F signal switching circuit of a BS receiver, for example, and a signal is input from a terminal 46 and connected to the gates of FETs 52 and 53, respectively.

The drain D of the FET 52 is a resistor 55 and a diode 73.
The drain D of the FET 53 is connected to the control voltage terminal 48 via a resistor 56 and a diode 74.

The sources of FETs 52 and 53 are connected to each other to make them common, and when terminal 47 is at High level and 48 is at Low level, the IF multiplied signal is input to the four output terminals, and terminal 47 is at Low level and 48 is at High level. When , output terminal 5
The IF multiplied signal is input to 0.

Inside the SAW filter 59, there are two filters each having a different bandwidth.
Two SAW devices are installed, and output terminals 49 and 50 are switched and used depending on the required bandwidth. A signal whose band is limited by a SAW filter 59 is obtained from the terminal 51 . According to this embodiment, there is no loss with a simple configuration.
A branch circuit is obtained.

FIG. 13 shows a thirteenth embodiment of the present invention. This circuit performs switching using source input FETs 62 and 63, and a control voltage is applied to gate terminals 47 and 48 of FETs 62 and 63. This embodiment is characterized by stable input impedance.

FIG. 14 shows a fourteenth embodiment of the present invention. This is a circuit that uses dual gate FET64.65 in the switching circuit, and a signal is input from the first gate 46,
Switching is performed by applying a control voltage to the second gates 47 and 48 of T64 and T65. The effects and features are similar to those of the twelfth embodiment shown in FIG.

〔Effect of the invention〕

According to the present invention, the FE'l" for amplifying the human power is turned on,
By turning it off, F E "r is switched, and since this FET has a gain, there is an effect that insertion ifl loss does not occur as in the conventional case.

Furthermore, according to the present invention, even if the amplification F)ET is turned off,
By configuring the gummy FET to turn on,
Stable input impedance without reflected waves can be obtained when off.

In addition, since the amplification FET is used as a switch and reverse bias is applied when it is off, the reverse direction at 0FFL is sufficiently attenuated, resulting in an FE with good isolation characteristics.
A T-switching circuit is obtained.

[Brief explanation of drawings]

1 to 14 are circuit diagrams each showing an embodiment of the present invention. Explanation of symbols 1.2...Input terminal, 25.30...Output terminal, 2
6.27, 47.48... Control voltage terminal, 59...
SAW filter, 3 4 7, 8, 19. 23, 28
．． 29,52,53,62.63...FET, 64.
65...Dual gate FET. Agent Patent Attorney Akio Namiki

Claims (1)

[Claims] Either one of the signals input from the two input terminals (1, 2), respectively, is connected to the two voltage control terminals (27, 26). In a switching circuit that selects a combination of high and low voltages to be applied to the output terminal (25) and outputs the selected voltage from the output terminal (25), the first input terminal (1) is connected to a first FET (field effect The source of the first FET (3) is connected to the source of the first FET (3), the gate of the second FET (7) whose source is grounded is connected to the second input terminal (2). The third FET (4
), and the drain of the third FET (4) is connected to the gate of a fourth FET (8) whose source is grounded, and each of the second and fourth FETs (7, 8) Between each source of
Each drain is connected to the common source, the common connection point between the sources is grounded with a parallel circuit of a resistor (17) and a capacitor (18), and the common connection point (K) between the drains is connected to the fifth FET.
(19), and the gate of the second FET (7) is connected to the first voltage control terminal (2) via a resistor (9) and a diode (11).
7), and the drain of the second FET (7) is connected to
The fourth FET (8) is connected to the first voltage control terminal (27) via a resistor (13) and a diode (15).
The gate of the fourth FET (8) is connected to the second voltage control terminal (26) through the resistor (10) and the diode (12), and the drain of the fourth FET (8) is connected to the second voltage control terminal (26) through the resistor (14) and the diode (16). is connected to the second voltage control terminal (26) via the fifth FET (19), and a diode (
The first and second voltage control terminals (27, 26) are connected via a level shift diode (22) to the source of the fifth FET (19). (25) A switching circuit characterized by being connected to (25). 2. High level of the voltage to apply one of the signals input from the first and second two input terminals (1, 2) to the first and second two voltage control terminals (27, 26). , a switching circuit that selects a combination of low and output signals from an output terminal (25), the source of a first FET (3) having a grounded gate connected to the first input terminal (1); The first FET (3)
The gate of a second FET (7) with a grounded source is connected to the drain of the transistor, and the source of a third FET (4) with a grounded gate is connected to the second input terminal (2). The third
The drain of the FET (4) has a fourth FET with a source grounded plane.
The gates of the ET (8) are connected, the sources of the second and fourth FETs (7, 8) are connected to make them common, and the common connection point between the sources is connected to the resistor (17).
) and a capacitor (18), and the drain of the second FET (7) is connected to the fifth FET (2
8), the drain of the fourth FET (8) is connected to the gate of the sixth FET (29), and the source of the fifth and sixth FETs (28, 29) is connected to each other. The source-to-source common connection point (K) is connected to the output terminal (25), and the gate of the second FET (7) is connected via a resistor (9) and a diode (11). The first voltage control terminal (2
7), and the drain of the second FET (7) is connected to
It is connected to the first voltage control terminal (27) via a resistor (13), and the gate of the fourth FET (8) is connected to the resistor (10
) and a diode (12) to a second voltage control terminal (26), and the drain of the fourth FET (8) is connected to a second voltage control terminal (26) via a resistor (14).
The drain of the fifth FET (28) is connected to the first voltage control terminal (27), and the drain of the fifth FET (28) is connected to the sixth FET (29).
) is connected to the second voltage control terminal (26). 3. In the switching circuit according to claim 1, the sources of the second and fourth FETs (7, 8) are connected and shared, and the common connection point between the sources is connected to the second output terminal ( 30) A switching circuit characterized by being connected to. 4. In the switching circuit according to claim 2, the sources of the second and fourth FETs (7, 8) are connected and shared, and the common connection point between the sources is connected to the second output terminal ( 30) A switching circuit characterized by being connected to. 5. The switching circuit according to claim 1, wherein a seventh FET (31) has a gate connected to the drain of the first FET (3) and a drain connected to the first control voltage terminal (27). and the gate is the third FET (
4), an eighth FET (32) whose drain is connected to the second control voltage terminal (26), and the seventh and eighth FETs (31,
32) are connected to make them common, and the common connection point is connected to a second output terminal (30). 6. The switching circuit according to claim 2, wherein a seventh FET (31) has a gate connected to the drain of the first FET (3) and a drain connected to the first control voltage terminal (27). and the gate is the third FET (
4), an eighth FET (32) whose drain is connected to the second control voltage terminal (26), and the seventh and eighth FETs (31,
32) are connected to make them common, and the common connection point is connected to a second output terminal (30). 7. The switching circuit according to claim 1, wherein the source is connected to the source of the first FET (3), and the drain is connected to the second control voltage terminal (26) via a resistor (37). A seventh FET (34) has a source connected to the source of the third FET (4) and a drain connected to the resistor (
36), eighth FETs (35) respectively connected to the first control voltage terminals (27). 8. The switching circuit according to claim 2, wherein the source is connected to the source of the first FET (3), and the drain is connected to the second control voltage terminal (26) via a resistor (37). A seventh FET (34) has a source connected to the source of the third FET (4) and a drain connected to the resistor (
36), eighth FETs (35) respectively connected to the first control voltage terminals (27). 9. High voltage level to apply one of the signals input from the first and second input terminals (1, 2) to the first and second two voltage control terminals (27, 26). , a switching circuit that selects a combination of low and output signals from an output terminal (25), the source of a first FET (3) having a grounded gate connected to the first input terminal (1); The first FET (3)
The gate of a second FET (7) with a grounded source is connected to the drain of the transistor, and the source of a third FET (4) with a grounded gate is connected to the second input terminal (2). The third
The drain of the FET (4) has a fourth FET with a source grounded plane.
between the respective sources of the second and fourth FETs (7, 8), connecting the gate of the ET (8);
Each drain is connected to the common source, the common connection point between the sources is grounded with a parallel circuit of a resistor (17) and a capacitor (18), and the common connection point (K) between the drains is connected to the fifth FET.
(19), and the gate of the second FET (7) and the fourth FET (8).
are connected to the gates of each via resistors (9, 10), and diodes (38, 39) are connected to the connection points, respectively.
) to the first voltage control terminal (27) and the second voltage control terminal (26), and the second FET (7
) is a resistor (13) and a diode (15).
The drain of the fourth FET (8) is connected to the second voltage control terminal (26) via a resistor (14) and a diode (16). and a diode (
The first and second voltage control terminals (27, 26) are connected via a level shift diode (22) to the source of the fifth FET (19). (25) A switching circuit characterized by being connected to (25). 10. High voltage level to apply one of the signals inputted from the first and second input terminals (1, 2) to the first and second two voltage control terminals (27, 26). , a switching circuit that selects a combination of low and output signals from an output terminal (25), the source of a first FET (3) having a grounded gate connected to the first input terminal (1); The first FET (3)
The gate of a second FET (7) with a grounded source is connected to the drain of the transistor, and the source of a third FET (4) with a grounded gate is connected to the second input terminal (2). The third
The drain of the FET (4) has a fourth FET with a source grounded plane.
The gates of the ET (8) are connected, the sources of the second and fourth FETs (7, 8) are connected to make them common, and the common connection point between the sources is connected to the resistor (17).
) and a capacitor (18), and the drain of the second FET (7) is connected to the fifth FET (2
8), the drain of the fourth FET (8) is connected to the gate of the sixth FET (29), and the source of the fifth and sixth FETs (28, 29) is connected to each other. The source-to-source common connection point (K) is connected to the output terminal (25), and the gate of the second FET (7) and the fourth FET (8) are connected to each other.
are connected to the gates of each via resistors (9, 10), and diodes (38, 39) are connected to the connection points, respectively.
) to the first voltage control terminal (27) and the second voltage control terminal (26), and the second FET (7
) is connected to the first voltage control terminal (27) through a resistor (13), and the drain of the fourth FET (8) is connected to the second voltage control terminal (27) through a resistor (14). (2
6), the drain of the fifth FET (28) is connected to the first voltage control terminal (27), and the drain of the fifth FET (28) is connected to the sixth FET (29).
) is connected to the second voltage control terminal (26).